coreboot-gerrit May 2017

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Change in coreboot[master]: google/parrot: add board-specific USB port info
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19963 ) Change subject: google/parrot: add board-specific USB port info ...................................................................... google/parrot: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Move inclusion of mainboard.asl after southbridge asl files so scopes referenced in usb.asl are valid. Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19963 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/parrot/acpi/mainboard.asl A src/mainboard/google/parrot/acpi/usb.asl M src/mainboard/google/parrot/dsdt.asl 3 files changed, 155 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 6b37e48..98208e0 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -101,3 +101,6 @@ } } + +/* USB port entries */ +#include "acpi/usb.asl" diff --git a/src/mainboard/google/parrot/acpi/usb.asl b/src/mainboard/google/parrot/acpi/usb.asl new file mode 100644 index 0000000..fc992db --- /dev/null +++ b/src/mainboard/google/parrot/acpi/usb.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.EHC1.HUB7.PRT1) +{ + // Hub Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + + Device (USB2) + { + Name (_ADR, 2) + + // Left USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + + } + + Device (USB3) + { + Name (_ADR, 3) + + // Bottom Right USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + } + + Device (USB4) + { + Name (_ADR, 4) + + // Top Right USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + } + +} + +Scope (_SB.PCI0.EHC2.HUB7.PRT1) +{ + // Hub Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + + Device (USB1) + { + Name (_ADR, 1) + + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + } + + Device (USB3) + { + Name (_ADR, 3) + + // Webcam + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + } +} diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 3e13a41..d179dea 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -27,7 +27,6 @@ // Some generic macros #include "acpi/platform.asl" - #include "acpi/mainboard.asl" // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> @@ -50,6 +49,8 @@ } } + #include "acpi/mainboard.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ -- To view, visit https://review.coreboot.org/19963 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/bd82x6x: add ACPI method to generate USB port info
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has submitted this change and it was merged. ( https://review.coreboot.org/19962 ) Change subject: sb/bd82x6x: add ACPI method to generate USB port info ...................................................................... sb/bd82x6x: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> Reviewed-on: https://review.coreboot.org/19962 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Martin Roth <martinroth(a)google.com> --- M src/southbridge/intel/bd82x6x/acpi/usb.asl 1 file changed, 40 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Martin Roth: Looks good to me, approved diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index e76acb8..5f78e3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -40,6 +40,27 @@ { Name (_ADR, 0x00000000) + + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) + { + + Name (PCKG, Package (0x01) + { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 @@ -74,6 +95,25 @@ { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) + { + Name (PCKG, Package (0x01) + { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 -- To view, visit https://review.coreboot.org/19962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19954 ) Change subject: sb/intel/bd82x6x/early_usb: Use register name ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54635/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/10347/ : SUCCESS -- To view, visit https://review.coreboot.org/19954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name
by Patrick Rudolph (Code Review) 31 May '17

31 May '17

Hello Philippe Mathieu-Daudé, Arthur Heymans, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19954 to look at the new patch set (#5). Change subject: sb/intel/bd82x6x/early_usb: Use register name ...................................................................... sb/intel/bd82x6x/early_usb: Use register name Use register name instead of magic value. Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19954/5 -- To view, visit https://review.coreboot.org/19954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/early_usb: Use register name
by Patrick Rudolph (Code Review) 31 May '17

31 May '17

Hello Philippe Mathieu-Daudé, Arthur Heymans, build bot (Jenkins), Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19954 to look at the new patch set (#4). Change subject: sb/intel/bd82x6x/early_usb: Use register name ...................................................................... sb/intel/bd82x6x/early_usb: Use register name Use register name instead of magic value. Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/southbridge/intel/bd82x6x/early_usb.c M src/southbridge/intel/bd82x6x/pch.h 2 files changed, 8 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19954/4 -- To view, visit https://review.coreboot.org/19954 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4f2f3f196c12489613333ab9f6098443edda927f Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: [WIP]nb/intel/sandybridge/raminit: Advertise correct frequency
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19995 ) Change subject: [WIP]nb/intel/sandybridge/raminit: Advertise correct frequency ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54634/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/10346/ : SUCCESS -- To view, visit https://review.coreboot.org/19995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]nb/intel/sandybridge/raminit: Advertise correct frequency
by Patrick Rudolph (Code Review) 31 May '17

31 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19995 ) Change subject: [WIP]nb/intel/sandybridge/raminit: Advertise correct frequency ...................................................................... [WIP]nb/intel/sandybridge/raminit: Advertise correct frequency As of Change-Id: I780d34ded2c1e3737ae1af685c8c2da832842e7c the reference clock can be 100Mhz. Decode the register and use the reference clock to calculate the selected DDR frequency. Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/northbridge/intel/sandybridge/raminit.c 1 file changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/19995/1 diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 4b92d18..b505556 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -123,14 +123,17 @@ static void report_memory_config(void) { u32 addr_decoder_common, addr_decode_ch[NUM_CHANNELS]; - int i; + int i, refclk; addr_decoder_common = MCHBAR32(0x5000); addr_decode_ch[0] = MCHBAR32(0x5004); addr_decode_ch[1] = MCHBAR32(0x5008); + refclk = MCHBAR32(MC_BIOS_REQ) & 0x100 ? 100 : 133; + + printk(BIOS_DEBUG, "memcfg DDR3 ref clock %d MHz\n", refclk); printk(BIOS_DEBUG, "memcfg DDR3 clock %d MHz\n", - (MCHBAR32(MC_BIOS_DATA) * 13333 * 2 + 50) / 100); + (MCHBAR32(MC_BIOS_DATA) * refclk * 100 * 2 + 50) / 100); printk(BIOS_DEBUG, "memcfg channel assignment: A: %d, B % d, C % d\n", addr_decoder_common & 3, (addr_decoder_common >> 2) & 3, (addr_decoder_common >> 4) & 3); -- To view, visit https://review.coreboot.org/19995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I8481564fe96af29ac31482a7f03bb88f343326f4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

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Change in coreboot[master]: src/cpu/amd/quadcore Fix checkpatch errors/warnings
by Philipp Deppenwiese (Code Review) 31 May '17

31 May '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19987 ) Change subject: src/cpu/amd/quadcore Fix checkpatch errors/warnings ...................................................................... Patch Set 1: Code-Review+1 (3 comments) https://review.coreboot.org/#/c/19987/1/src/cpu/amd/quadcore/quadcore.c File src/cpu/amd/quadcore/quadcore.c: PS1, Line 5: * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, : * Raptor Engineering same again https://review.coreboot.org/#/c/19987/1/src/cpu/amd/quadcore/quadcore_id.c File src/cpu/amd/quadcore/quadcore_id.c: PS1, Line 5: * Raptor Engineering same again PS1, Line 10: * the Free Software Foundation; version 2 of the License. wrong alignment of the comment -- To view, visit https://review.coreboot.org/19987 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib0a28c12e209547b3625f4ca1696f9c26dc2b6d0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: arch/arm/include/armv7/arch: Correct keyword organization in...
by Philipp Deppenwiese (Code Review) 31 May '17

31 May '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19991 ) Change subject: arch/arm/include/armv7/arch: Correct keyword organization in cpu.h ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19991 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ibacc5ee9fabff7fec2abd5534312cf3ab1bb28cf Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Logan Carlson <logancarlson(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: cpu/amd/car: Fix checkpatch warnings
by Philipp Deppenwiese (Code Review) 31 May '17

31 May '17

Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19988 ) Change subject: cpu/amd/car: Fix checkpatch warnings ...................................................................... Patch Set 1: Code-Review+1 (1 comment) https://review.coreboot.org/#/c/19988/1/src/cpu/amd/car/disable_cache_as_ra… File src/cpu/amd/car/disable_cache_as_ram.c: PS1, Line 7: * Copyright (C) 2015 Timothy Pearson <tpearson(a)raptorengineeringinc.com>, : * Raptor Engineering Please align the company name with the beginning of the contributor name. -- To view, visit https://review.coreboot.org/19988 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id5a5abaa06f8e285ff58436789318cb9cd3b7ac3 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Evelyn Huang <evhuang(a)google.com> Gerrit-Reviewer: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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coreboot-gerrit May 2017