coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19978 ) Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10341/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54630/ : SUCCESS -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mc_bdx1: Switch to RTC RX6110SA
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19979 ) Change subject: mc_bdx1: Switch to RTC RX6110SA ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-checkpatch/10342/ : FAILURE https://qa.coreboot.org/job/coreboot-gerrit/54629/ : SUCCESS -- To view, visit https://review.coreboot.org/19979 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Bring in delta for GLK SOC
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19603 ) Change subject: soc/intel/apollolake: Bring in delta for GLK SOC ...................................................................... Patch Set 50: (1 comment) https://review.coreboot.org/#/c/19603/50/src/soc/intel/apollolake/include/s… File src/soc/intel/apollolake/include/soc/gpio_apl.h: Line 34: PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) > But those macros are what determines what is settable in the register. Howe because some of the bits could be not relevant for this SOC -- To view, visit https://review.coreboot.org/19603 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Gerrit-PatchSet: 50 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by Werner Zeh (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19978 to look at the new patch set (#5). Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... rx6110sa: Add possibility to use both I2C and SMBus for the RTC The driver for the RTC RX6110SA is designed to be used with I2C bus. This patch adds the possibility to use SMBus operations to access the RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It is not enabled per default so that I2C will be used. One can set this switch on board level to use SMBus instead. Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/Kconfig M src/drivers/i2c/rx6110sa/rx6110sa.c 2 files changed, 60 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19978/5 -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/apollolake: Bring in delta for GLK SOC
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19603 ) Change subject: soc/intel/apollolake: Bring in delta for GLK SOC ...................................................................... Patch Set 50: (1 comment) https://review.coreboot.org/#/c/19603/50/src/soc/intel/apollolake/include/s… File src/soc/intel/apollolake/include/soc/gpio_apl.h: Line 34: PAD_CFG0_RXPADSTSEL_MASK | PAD_CFG0_RESET_MASK) > What is the point of this? I didn't understand. These are the things we can Yes and any of the bits not set here will get populated from default values. In fact, I should remove the bits that do not get set from pad config macros. gpio_configure pad does following pad_conf0 = pcr_read32(comm->port, config_offset); pad_conf0 &= ~PAD_DW0_MASK; pcr_write32(comm->port, config_offset, pad_conf0 | (cfg->pad_config0 & PAD_DW0_MASK)); Same logic for pad_config1 -- To view, visit https://review.coreboot.org/19603 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I3e76726bb77f0277ab5776ae9d3d42b7eb389fe3 Gerrit-PatchSet: 50 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Brenton Dong <brenton.m.dong(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Han Lim Ng <nhlhanlim93(a)gmail.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: change GPI RXEVCFG default to edge
by Kane Chen (Code Review) 31 May '17

31 May '17

Kane Chen has posted comments on this change. ( https://review.coreboot.org/19992 ) Change subject: soc/intel/skylake: change GPI RXEVCFG default to edge ...................................................................... Patch Set 3: Should we ask the driver owner to take a look? >From my observation, the driver seems to enable interrupt first then config the pin to edge trigger during s3 resume. -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by Werner Zeh (Code Review) 31 May '17

31 May '17

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/19978 ) Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... Patch Set 4: (3 comments) https://review.coreboot.org/#/c/19978/4/src/drivers/i2c/rx6110sa/rx6110sa.c File src/drivers/i2c/rx6110sa/rx6110sa.c: Line 16: > Why the extra line? It slipped in, will remove it. PS4, Line 32: CONFIG_RX6110SA_USE_SMBUS > IS_ENABLED(...) Oh yes, definitively. Line 41: uint8_t val; > You probably want to initialize this to 0 as there isn't any error checking Sure. -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: change GPI RXEVCFG default to edge
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19992 ) Change subject: soc/intel/skylake: change GPI RXEVCFG default to edge ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54628/ : SUCCESS -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: change GPI RXEVCFG default to edge
by Kane Chen (Code Review) 31 May '17

31 May '17

Kane Chen has posted comments on this change. ( https://review.coreboot.org/19992 ) Change subject: soc/intel/skylake: change GPI RXEVCFG default to edge ...................................................................... Patch Set 2: > (1 comment) Hi Aaron, The issue happens in below scenario. The SD_CD is edge trigger. BIOS sets GPI for SD_CD in gpio.h and claims GpioInt in asl code. When BIOS hands over to OS, the gpio interrupt is not enabled yet. But with original macro, it leaves all GPI to Level trigger.(GPI_IE is not yet set here) Once OS takes control and init GpioInt for SD_CD, then issue happens in a very small window (it's still level trigger) After OS correctly config the interrupt to EDGE from level, then the unused interrupts stop immediately. Thanks. -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: change GPI RXEVCFG default to edge
by Kane Chen (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19992 to look at the new patch set (#3). Change subject: soc/intel/skylake: change GPI RXEVCFG default to edge ...................................................................... soc/intel/skylake: change GPI RXEVCFG default to edge The original gpio macro sets GPI or native pin RXEVCFG to LEVEL trigger. This would cause unused interrupts happen while OS is trying to enable GPIO interrupt and set RXEVCFG to edge trigger for SD_CD pin. By changing GPI RXEVCFG default to edge can prevent unused interrupts happen while OS is setting gpio RXEVCFG from level to edge. BUG=b:62067569 TEST=checked unused interrupt on SD_CD dose not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/include/soc/gpio.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19992/3 -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit May 2017