coreboot-gerrit May 2017

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Change in coreboot[master]: soc/amd/stoneyridge: Add CPU files
by Martin Roth (Code Review) 31 May '17

31 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19723 ) Change subject: soc/amd/stoneyridge: Add CPU files ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19723/3/src/soc/amd/common/Kconfig File src/soc/amd/common/Kconfig: Line 13 > So is there a solution already figured out or we should be doing something I don't understand Aaron's comment about someone needing to include the kconfig files. Of course they need to be added - it's WHERE they're added that is the problem. So long as they get sourced after the rest of the SOC files, it isn't an issue for overriding default values. I stick by my initial suggestion as the solution. -- To view, visit https://review.coreboot.org/19723 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8b6b1991372c2c6a02709777a73615a86e78ac26 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: vendorcode/intel/skykabylake: change GPI RXEVCFG default to ...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19992 ) Change subject: vendorcode/intel/skykabylake: change GPI RXEVCFG default to edge ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/54627/ : SUCCESS -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use common gpio for apollolake[WIP]
by Hannah Williams (Code Review) 31 May '17

31 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19949 ) Change subject: soc/intel/apollolake: Use common gpio for apollolake[WIP] ...................................................................... Patch Set 3: > (7 comments) Just working on the 38 comments in the other CL - https://review.coreboot.org/#/c/19603/50/src/soc/intel/apollolake/gpio_apl.… -- To view, visit https://review.coreboot.org/19949 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0fcc22df5eaec014f3b89755415f051b05aa554a Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: vendorcode/intel/skykabylake: change GPI RXEVCFG default to ...
by Kane Chen (Code Review) 31 May '17

31 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19992 to look at the new patch set (#2). Change subject: vendorcode/intel/skykabylake: change GPI RXEVCFG default to edge ...................................................................... vendorcode/intel/skykabylake: change GPI RXEVCFG default to edge The original gpio macro sets GPI or native pin RXEVCFG to LEVEL trigger. This would cause unused interrupts happen while OS is trying to enable GPIO interrupt and set RXEVCFG to edge trigger for SD_CD pin. By changing GPI RXEVCFG default to edge can prevent unused interrupts happen while OS is setting gpio RXEVCFG from level to edge. BUG=b:62067569 TEST=checked unused interrupt on SD_CD dose not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/include/soc/gpio.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19992/2 -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: vendorcode/intel/skykabylake: change gpio RXEVCFG default to...
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19992 ) Change subject: vendorcode/intel/skykabylake: change gpio RXEVCFG default to edge ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10340/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54626/ : SUCCESS -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: vendorcode/intel/skykabylake: change gpio RXEVCFG default to...
by Kane Chen (Code Review) 31 May '17

31 May '17

Kane Chen has uploaded a new change for review. ( https://review.coreboot.org/19992 ) Change subject: vendorcode/intel/skykabylake: change gpio RXEVCFG default to edge ...................................................................... vendorcode/intel/skykabylake: change gpio RXEVCFG default to edge The original gpio macro sets GPI or native pin RXEVCFG to LEVEL trigger. This would cause unused interrupts happen while OS is trying to enable GPIO interrupt and set RXEVCFG to edge trigger. BUG=b:62067569 TEST=checked unused interrupt on SD_CD dose not happen after s3 resume Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/include/soc/gpio.h 1 file changed, 5 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/19992/1 diff --git a/src/soc/intel/skylake/include/soc/gpio.h b/src/soc/intel/skylake/include/soc/gpio.h index ae534cd..1129c45 100644 --- a/src/soc/intel/skylake/include/soc/gpio.h +++ b/src/soc/intel/skylake/include/soc/gpio.h @@ -110,24 +110,24 @@ /* Native Function - No Rx buffer manipulation */ #define PAD_CFG_NF(pad_, term_, rst_, func_) \ _PAD_CFG(pad_, term_, \ - _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, func_, NO, NO)) + _DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, func_, NO, NO)) /* Native 1.8V tolerant pad, only applies to some pads like I2C/I2S. */ #define PAD_CFG_NF_1V8(pad_, term_, rst_, func_) \ _PAD_CFG_ATTRS(pad_, term_, \ - _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, \ NO, NO, NO, NO, func_, NO, NO), PAD_FIELD(PAD_TOL, 1V8)) /* Unused PINS will be controlled by GPIO controller (PMODE = GPIO) and GPIO TX/RX will be disabled. */ #define PAD_CFG_NC(pad_) \ _PAD_CFG(pad_, NONE, \ - _DW0_VALS(DEEP, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, YES)) + _DW0_VALS(DEEP, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, YES, YES)) /* General purpose output with termination. */ #define PAD_CFG_TERM_GPO(pad_, val_, term_, rst_) \ _PAD_CFG(pad_, term_, \ - _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, YES, NO) \ | PAD_FIELD_VAL(GPIOTXSTATE, val_)) /* General purpose output. By default no termination. */ @@ -137,7 +137,7 @@ /* General purpose input with no special IRQ routing. */ #define PAD_CFG_GPI(pad_, term_, rst_) \ _PAD_CFG_ATTRS(pad_, term_, \ - _DW0_VALS(rst_, RAW, NO, LEVEL, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\ + _DW0_VALS(rst_, RAW, NO, EDGE, NO, NO, NO, NO, NO, NO, GPIO, NO, YES),\ PAD_FIELD(HOSTSW, GPIO)) /* General purpose input passed through to IOxAPIC. Assume APIC logic can -- To view, visit https://review.coreboot.org/19992 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I42b9cd80b494e24c55b97e54cdf59bfd24dd9054 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 31 May '17

31 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19668 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 5: (8 comments) https://review.coreboot.org/#/c/19668/5/src/soc/intel/common/block/systemag… File src/soc/intel/common/block/systemagent/systemagent.c: Line 43: return 0; > This should not return 0 since index is the resource index passed in. we should use index as return Line 46: __attribute__((weak)) void soc_add_imr_resources(device_t dev, int index) > It seems odd that this and soc_add_dram_resources() not symmetric in that t got it, you want to unify behavior, i had focused on function caling order. Line 55: #define DPR_SIZE_MASK 0xff0 > These are only for what chipsets? Mostly core platform Line 57: int sa_get_pcie_base_addr(device_t dev, unsigned int index, uintptr_t *base, > Why is this exposed globally? i guess we are calling this from ramstage https://review.coreboot.org/#/c/19796/3/src/soc/intel/skylake/systemagent.c PS5, Line 93: len > len isn't set? i guess this is a miss, we don't need to get the len, purpose for this API to get the base address PS5, Line 115: *len) > again, no len being set. You made this whole API so PCIE mmconfig area leng i guess we need to get the base address, len is needed only for PCIEX and in order to make this API generic, we have added length field, we will use Kconfig to achieve that and remove this from here Line 166: static void read_map_entry(device_t dev, const struct sa_map_entry *entry, > This map_entry concept and sa_mmio_descriptor have become way too complicat this API is static hence user side shouldn't bother abut how map entry happen. We havn't done anything specific to make this whole stuff complicated, just taken out soc delta specific stuff and provides same input from soc. Do you think https://review.coreboot.org/#/c/19796/3/src/soc/intel/skylake/systemagent.c this soc part is complicated? i had only opinion in mind that when we port new SOC, we should see BWG system map file and know what all range need to program. PS5, Line 310: SA_TSEG_REG > So you're reliant on all these enums to be provided by the SoCs? yes -- To view, visit https://review.coreboot.org/19668 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I969ff187e3d4199864cb2e9c9a13f4d04158e27c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/amd/stoneyridge: Enable early cbmem
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19751 ) Change subject: soc/amd/stoneyridge: Enable early cbmem ...................................................................... Patch Set 4: Build Failed https://qa.coreboot.org/job/coreboot-gerrit/54601/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/10315/ : SUCCESS -- To view, visit https://review.coreboot.org/19751 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I11ad7190031c912642a7312f2fc6f792866288b7 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Enable TPM
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19848 ) Change subject: google/kahlee: Enable TPM ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10339/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54625/ : SUCCESS -- To view, visit https://review.coreboot.org/19848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iab92259ebeaa40937309fad05cc45d9ca6d41357 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/kahlee: Set DDI port 2 to DP
by build bot (Jenkins) (Code Review) 31 May '17

31 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19846 ) Change subject: google/kahlee: Set DDI port 2 to DP ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10337/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54623/ : SUCCESS -- To view, visit https://review.coreboot.org/19846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Idc5e57e01d4f0073ac50533c1b04a95bcae67473 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017