coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: soc/skylake: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19975 ) Change subject: soc/skylake: add ACPI method to generate USB port info ...................................................................... soc/skylake: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/skylake/acpi/xhci.asl 1 file changed, 20 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19975/1 diff --git a/src/soc/intel/skylake/acpi/xhci.asl b/src/soc/intel/skylake/acpi/xhci.asl index 4c6625e..08f35bc 100644 --- a/src/soc/intel/skylake/acpi/xhci.asl +++ b/src/soc/intel/skylake/acpi/xhci.asl @@ -223,6 +223,26 @@ { Name (_ADR, Zero) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) + { + + Name (PCKG, Package (0x01) + { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + Return (PCKG) + } + /* USB2 */ Device (HS01) { Name (_ADR, 1) } Device (HS02) { Name (_ADR, 2) } -- To view, visit https://review.coreboot.org/19975 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: sb/bd82x6x: add ACPI method to generate USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19962 ) Change subject: sb/bd82x6x: add ACPI method to generate USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10225/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54506/ : SUCCESS -- To view, visit https://review.coreboot.org/19962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/beltino: add board-specific USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19966 ) Change subject: google/beltino: add board-specific USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10229/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54510/ : SUCCESS -- To view, visit https://review.coreboot.org/19966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: sb/lynxpoint: add ACPI method to generate USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19964 ) Change subject: sb/lynxpoint: add ACPI method to generate USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10227/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54508/ : SUCCESS -- To view, visit https://review.coreboot.org/19964 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: google/rambi: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19974 ) Change subject: google/rambi: add board-specific USB port info ...................................................................... google/rambi: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each rambi variant has a different USB port config. Port data currently available for only candy and squawks; other variants to be added once data obtained. Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/rambi/acpi/mainboard.asl A src/mainboard/google/rambi/variants/banjo/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/clapper/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/heli/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/kip/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/ninja/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/orco/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/quawks/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/rambi/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/sumo/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/swanky/include/variant/acpi/usb.asl A src/mainboard/google/rambi/variants/winky/include/variant/acpi/usb.asl 17 files changed, 227 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/19974/1 diff --git a/src/mainboard/google/rambi/acpi/mainboard.asl b/src/mainboard/google/rambi/acpi/mainboard.asl index 84136d9..415065e 100644 --- a/src/mainboard/google/rambi/acpi/mainboard.asl +++ b/src/mainboard/google/rambi/acpi/mainboard.asl @@ -136,3 +136,6 @@ } #include <variant/acpi/mainboard.asl> + +/* USB port entries */ +#include <variant/acpi/usb.asl> diff --git a/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/banjo/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl new file mode 100644 index 0000000..028a546 --- /dev/null +++ b/src/mainboard/google/rambi/variants/candy/include/variant/acpi/usb.asl @@ -0,0 +1,132 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.RHUB.PRT1) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT2) +{ + // USB HUB + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + + Device (USB1) + { + Name (_ADR, 4) + + // Right USB 2.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + } + + Device (USB3) + { + Name (_ADR, 5) + + // SIM Card Slot + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/clapper/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/enguarde/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/glimmer/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/gnawty/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/heli/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/heli/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/kip/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/kip/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/ninja/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/orco/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/orco/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/quawks/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/rambi/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl new file mode 100644 index 0000000..cacf40f --- /dev/null +++ b/src/mainboard/google/rambi/variants/squawks/include/variant/acpi/usb.asl @@ -0,0 +1,92 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.RHUB.PRT1) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT2) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.RHUB.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/sumo/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/swanky/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/rambi/variants/winky/include/variant/acpi/usb.asl b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/rambi/variants/winky/include/variant/acpi/usb.asl -- To view, visit https://review.coreboot.org/19974 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: soc/baytrail: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19973 ) Change subject: soc/baytrail: add ACPI method to generate USB port info ...................................................................... soc/baytrail: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/acpi/xhci.asl 1 file changed, 17 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/19973/1 diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index bef0b9f..339537c 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -23,6 +23,23 @@ Device (RHUB) { Name (_ADR, 0x00000000) + + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + Device (PRT1) { Name (_ADR, 1) } Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } -- To view, visit https://review.coreboot.org/19973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: soc/baytrail: add missing USB port defs
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19972 ) Change subject: soc/baytrail: add missing USB port defs ...................................................................... soc/baytrail: add missing USB port defs Add device/address stub for XHCI USB port 7. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/baytrail/acpi/xhci.asl 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/72/19972/1 diff --git a/src/soc/intel/baytrail/acpi/xhci.asl b/src/soc/intel/baytrail/acpi/xhci.asl index dbd3447..bef0b9f 100644 --- a/src/soc/intel/baytrail/acpi/xhci.asl +++ b/src/soc/intel/baytrail/acpi/xhci.asl @@ -27,5 +27,6 @@ Device (PRT2) { Name (_ADR, 2) } Device (PRT3) { Name (_ADR, 3) } Device (PRT4) { Name (_ADR, 4) } + Device (SSP1) { Name (_ADR, 7) } } } -- To view, visit https://review.coreboot.org/19972 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iae874a9ba01e9428e07cf7ff15e663365b2354a9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/jecht: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19971 ) Change subject: google/jecht: add board-specific USB port info ...................................................................... google/jecht: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each jecht variant has a different USB port config. Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/jecht/acpi/mainboard.asl A src/mainboard/google/jecht/variants/guado/include/variant/acpi/usb.asl A src/mainboard/google/jecht/variants/jecht/include/variant/acpi/usb.asl A src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl A src/mainboard/google/jecht/variants/tidus/include/variant/acpi/usb.asl 5 files changed, 163 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/19971/1 diff --git a/src/mainboard/google/jecht/acpi/mainboard.asl b/src/mainboard/google/jecht/acpi/mainboard.asl index 16e6352..4b2d9ca 100644 --- a/src/mainboard/google/jecht/acpi/mainboard.asl +++ b/src/mainboard/google/jecht/acpi/mainboard.asl @@ -67,3 +67,6 @@ } } } + +/* USB port entries */ +#include <variant/acpi/usb.asl> diff --git a/src/mainboard/google/jecht/variants/guado/include/variant/acpi/usb.asl b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/jecht/variants/guado/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/usb.asl b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/jecht/variants/jecht/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl new file mode 100644 index 0000000..52d7e3e --- /dev/null +++ b/src/mainboard/google/jecht/variants/rikku/include/variant/acpi/usb.asl @@ -0,0 +1,160 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Front Top USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Front Bottom USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Back Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT6) +{ + // Back Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + // Connected, OEM Connector, Reserved, Reserved + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP3) +{ + // Front Top USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP4) +{ + // Front Bottom USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP5) +{ + // Back Right USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP6) +{ + // Back Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/usb.asl b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/jecht/variants/tidus/include/variant/acpi/usb.asl -- To view, visit https://review.coreboot.org/19971 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I3b15aac9c4971e2ae230106016fba3a583ec6c9a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/auron: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19970 ) Change subject: google/auron: add board-specific USB port info ...................................................................... google/auron: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each auron variant has a different USB port config. Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/acpi/mainboard.asl A src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl A src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl A src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl A src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl A src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl 6 files changed, 632 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/19970/1 diff --git a/src/mainboard/google/auron/acpi/mainboard.asl b/src/mainboard/google/auron/acpi/mainboard.asl index 46aaea1..2584015 100644 --- a/src/mainboard/google/auron/acpi/mainboard.asl +++ b/src/mainboard/google/auron/acpi/mainboard.asl @@ -44,3 +44,6 @@ } #include <variant/acpi/mainboard.asl> + +/* USB port entries */ +#include <variant/acpi/usb.asl> diff --git a/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl new file mode 100644 index 0000000..9227680 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_paine/include/variant/acpi/usb.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // WWAN M.2 Slot + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e3c8659 --- /dev/null +++ b/src/mainboard/google/auron/variants/auron_yuna/include/variant/acpi/usb.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e3c8659 --- /dev/null +++ b/src/mainboard/google/auron/variants/gandof/include/variant/acpi/usb.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl new file mode 100644 index 0000000..4f931e2 --- /dev/null +++ b/src/mainboard/google/auron/variants/lulu/include/variant/acpi/usb.asl @@ -0,0 +1,109 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP4) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl b/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl new file mode 100644 index 0000000..d36a122 --- /dev/null +++ b/src/mainboard/google/auron/variants/samus/include/variant/acpi/usb.asl @@ -0,0 +1,176 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // USB-A Port 1 USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // USB-A Port 2 USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // USB-C USB 2.0 Port Left + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // USB-C USB 2.0 Port Right + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT8) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP3) +{ + // USB-C USB 3.0 Port Left + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP4) +{ + // USB-C USB 3.0 Port Right + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP5) +{ + // USB-A Port 1 USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP6) +{ + // USB-A Port 2 USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} -- To view, visit https://review.coreboot.org/19970 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id17f21c23540d2e3d5a902a2174b66c7a5a5f3e0 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: soc/broadwell: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19969 ) Change subject: soc/broadwell: add ACPI method to generate USB port info ...................................................................... soc/broadwell: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/acpi/xhci.asl 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19969/1 diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index bbf9878..53ef127 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -355,6 +355,22 @@ { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 -- To view, visit https://review.coreboot.org/19969 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Id6e6699fe3eaafbe6847479d45c70a1d57bd327a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017