coreboot-gerrit May 2017

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10223/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54504/ : SUCCESS -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: ec/ene_kb3940q: correct ACPI battery data fed into ToString()
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19961 ) Change subject: ec/ene_kb3940q: correct ACPI battery data fed into ToString() ...................................................................... ec/ene_kb3940q: correct ACPI battery data fed into ToString() ToString() requires the input buffer data to be null-terminated, but the data returned by the EC is not, leading Windows to fail to report any battery data at all. Correct this by concatenating a null terminator (0x00) to the end of the buffer data before inputting to ToString() where needed TEST: boot Windows on google/butterfly, observe battery data reported correctly. Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/ec/quanta/ene_kb3940q/acpi/battery.asl 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/19961/1 diff --git a/src/ec/quanta/ene_kb3940q/acpi/battery.asl b/src/ec/quanta/ene_kb3940q/acpi/battery.asl index bcc9a98..dd9ba2f 100644 --- a/src/ec/quanta/ene_kb3940q/acpi/battery.asl +++ b/src/ec/quanta/ene_kb3940q/acpi/battery.asl @@ -90,9 +90,9 @@ Store(Local0, Index(PBIF, 5)) Multiply(Local1, 0x05, Local0) Store (Local0, Index (PBIF, 6)) - Store (ToString(BATD), Index (PBIF, 9)) // Model Number + Store (ToString(Concatenate(BATD, 0x00)), Index (PBIF, 9)) // Model Number Store (ToDecimalString(BSN0), Index (PBIF, 10)) // Serial Number - Store (ToString(BCHM), Index (PBIF, 11)) // Battery Type + Store (ToString(Concatenate(BCHM, 0x00)), Index (PBIF, 11)) // Battery Type Store (\BATV, Index (PBIF, 12)) // OEM information Return (PBIF) -- To view, visit https://review.coreboot.org/19961 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10221/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54502/ : SUCCESS -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/parrot: make chromeos.c compilation conditional on CO...
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19959 ) Change subject: google/parrot: make chromeos.c compilation conditional on CONFIG_CHROMEOS ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10222/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54503/ : SUCCESS -- To view, visit https://review.coreboot.org/19959 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... nb/sandybridge:add CBMEM_MEMINFO table when initing RAM Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older SandyBridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 52 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/19960/1 diff --git a/src/northbridge/intel/sandybridge/raminit.h b/src/northbridge/intel/sandybridge/raminit.h index 4e684ec..9066b7f 100644 --- a/src/northbridge/intel/sandybridge/raminit.h +++ b/src/northbridge/intel/sandybridge/raminit.h @@ -29,5 +29,6 @@ void save_mrc_data(struct pei_data *pei_data); void mainboard_fill_pei_data(struct pei_data *pei_data); int fixup_sandybridge_errata(void); +void setup_sdram_meminfo(struct pei_data *pei_data); #endif /* RAMINIT_H */ diff --git a/src/northbridge/intel/sandybridge/raminit_mrc.c b/src/northbridge/intel/sandybridge/raminit_mrc.c index 09d82d6..77c947b 100644 --- a/src/northbridge/intel/sandybridge/raminit_mrc.c +++ b/src/northbridge/intel/sandybridge/raminit_mrc.c @@ -31,6 +31,7 @@ #include "pei_data.h" #include "sandybridge.h" #include <vboot/vboot_common.h> +#include <memory_info.h> /* Management Engine is in the southbridge */ #include "southbridge/intel/bd82x6x/me.h" @@ -284,4 +285,54 @@ outb(0x6, 0xcf9); halt(); } + setup_sdram_meminfo(&pei_data); +} + +void setup_sdram_meminfo(struct pei_data *pei_data) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + struct memory_info* mem_info; + struct dimm_info *dimm; + int ddr_frequency; + int dimm_size; + int i; + int dimm_cnt = 0; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + memset(mem_info, 0, sizeof(struct memory_info)); + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100; + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + dimm_size = ((ch_conf >> 0) & 0xff) * 256; + + if (dimm_size) { + dimm_cnt++; + dimm = &mem_info->dimm[i]; + dimm->dimm_size = dimm_size; + dimm->ddr_type = 3; // DRAM + dimm->ddr_frequency = ddr_frequency; + dimm->rank_per_dimm = 1; + dimm->channel_num = i; + dimm->dimm_num = 0; + dimm->bank_locator = i * 2; + memcpy(dimm->serial, // bytes 122-125 in SPD + &pei_data->spd_data[i][122], // same for all modules so use first + sizeof(uint8_t) * 4); // since known good + memcpy(dimm->module_part_number, // bytes 128-145 in SPD + &pei_data->spd_data[0][128], // same for all modules so use first + sizeof(uint8_t) * 18); // since known good + dimm->mod_id = + (pei_data->spd_data[0][118] << 8) | // bytes 117/118 (LSB/MSB) + (pei_data->spd_data[0][117] & 0xFF); + dimm->mod_type = 3; //SPD_SODIMM + dimm->bus_width = 0x3; //64-bit + } + } + mem_info->dimm_cnt = dimm_cnt; } -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/lulu: enable SATA device to sleep in S0
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19957 ) Change subject: google/lulu: enable SATA device to sleep in S0 ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10220/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54501/ : SUCCESS -- To view, visit https://review.coreboot.org/19957 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/parrot: make chromeos.c compilation conditional on CO...
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19959 ) Change subject: google/parrot: make chromeos.c compilation conditional on CONFIG_CHROMEOS ...................................................................... google/parrot: make chromeos.c compilation conditional on CONFIG_CHROMEOS No reason to compile/include chromeos.c for non-ChromeOS builds Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/parrot/Makefile.inc 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/19959/1 diff --git a/src/mainboard/google/parrot/Makefile.inc b/src/mainboard/google/parrot/Makefile.inc index 78e5b98..a76bc12 100644 --- a/src/mainboard/google/parrot/Makefile.inc +++ b/src/mainboard/google/parrot/Makefile.inc @@ -15,6 +15,6 @@ ramstage-y += ec.c -romstage-y += chromeos.c -ramstage-y += chromeos.c +romstage-$(CONFIG_CHROMEOS) += chromeos.c +ramstage-$(CONFIG_CHROMEOS) += chromeos.c romstage-y += gpio.c -- To view, visit https://review.coreboot.org/19959 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ie8ef1f4c521b2a7308941299f2501073937bdf4a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/rambi: disable PCI device for unused i2c buses
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19956 ) Change subject: google/rambi: disable PCI device for unused i2c buses ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10219/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54500/ : SUCCESS -- To view, visit https://review.coreboot.org/19956 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ib0e041ae9131615ef1140bad064de5aae91f8ee4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... haswell: add CBMEM_MEMINFO table when initing RAM Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Haswell MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/raminit.h 3 files changed, 53 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19958/1 diff --git a/src/cpu/intel/haswell/romstage.c b/src/cpu/intel/haswell/romstage.c index c6765c7..ac45ee6 100644 --- a/src/cpu/intel/haswell/romstage.c +++ b/src/cpu/intel/haswell/romstage.c @@ -245,6 +245,8 @@ #endif } + setup_sdram_meminfo(params->pei_data); + romstage_handoff_init(wake_from_s3); post_code(0x3f); diff --git a/src/northbridge/intel/haswell/raminit.c b/src/northbridge/intel/haswell/raminit.c index 469c4f2..5e38b59 100644 --- a/src/northbridge/intel/haswell/raminit.c +++ b/src/northbridge/intel/haswell/raminit.c @@ -21,6 +21,7 @@ #include <cbfs.h> #include <halt.h> #include <ip_checksum.h> +#include <memory_info.h> #include <northbridge/intel/common/mrc_cache.h> #include <pc80/mc146818rtc.h> #include <device/pci_def.h> @@ -171,3 +172,52 @@ report_memory_config(); } + +void setup_sdram_meminfo(struct pei_data *pei_data) +{ + u32 addr_decoder_common, addr_decode_ch[2]; + struct memory_info* mem_info; + struct dimm_info *dimm; + int ddr_frequency; + int dimm_size; + int i; + int dimm_cnt = 0; + + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(struct memory_info)); + memset(mem_info, 0, sizeof(struct memory_info)); + + addr_decoder_common = MCHBAR32(0x5000); + addr_decode_ch[0] = MCHBAR32(0x5004); + addr_decode_ch[1] = MCHBAR32(0x5008); + + ddr_frequency = (MCHBAR32(0x5e04) * 13333 * 2 + 50)/100; + + for (i = 0; i < ARRAY_SIZE(addr_decode_ch); i++) { + u32 ch_conf = addr_decode_ch[i]; + dimm_size = ((ch_conf >> 0) & 0xff) * 256; + + if (dimm_size) { + dimm_cnt++; + dimm = &mem_info->dimm[i]; + dimm->dimm_size = dimm_size; + dimm->ddr_type = 3; // DRAM + dimm->ddr_frequency = ddr_frequency; + dimm->rank_per_dimm = 1; + dimm->channel_num = i; + dimm->dimm_num = 0; + dimm->bank_locator = i * 2; + memcpy(dimm->serial, // bytes 122-125 in SPD + &pei_data->spd_data[i][122], // same for all modules so use first + sizeof(uint8_t) * 4); // since known good + memcpy(dimm->module_part_number, // bytes 128-145 in SPD + &pei_data->spd_data[0][128], // same for all modules so use first + sizeof(uint8_t) * 18); // since known good + dimm->mod_id = + (pei_data->spd_data[0][118] << 8) | // bytes 117/118 (LSB/MSB) + (pei_data->spd_data[0][117] & 0xFF); + dimm->mod_type = 3; //SPD_SODIMM + dimm->bus_width = 0x3; //64-bit + } + } + mem_info->dimm_cnt = dimm_cnt; +} diff --git a/src/northbridge/intel/haswell/raminit.h b/src/northbridge/intel/haswell/raminit.h index d02b72d..b42fcf8 100644 --- a/src/northbridge/intel/haswell/raminit.h +++ b/src/northbridge/intel/haswell/raminit.h @@ -19,6 +19,7 @@ #include "pei_data.h" void sdram_initialize(struct pei_data *pei_data); +void setup_sdram_meminfo(struct pei_data *pei_data); int fixup_haswell_errata(void); /* save_mrc_data() must be called after cbmem has been initialized. */ void save_mrc_data(struct pei_data *pei_data); -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/lulu: enable SATA device to sleep in S0
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19957 ) Change subject: google/lulu: enable SATA device to sleep in S0 ...................................................................... google/lulu: enable SATA device to sleep in S0 sata_devslp_disable was set to work around some buggy SSD firmware, but as it's disabled by default in both Linux and Windows, no reason to disable at the firmware level when many properly-functioning SSDs can take advantage of power savings. Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/auron/variants/lulu/devicetree.cb 1 file changed, 0 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/19957/1 diff --git a/src/mainboard/google/auron/variants/lulu/devicetree.cb b/src/mainboard/google/auron/variants/lulu/devicetree.cb index 9f086a6..84fc8c4 100644 --- a/src/mainboard/google/auron/variants/lulu/devicetree.cb +++ b/src/mainboard/google/auron/variants/lulu/devicetree.cb @@ -43,7 +43,6 @@ register "gpe0_en_4" = "0x00000000" register "sata_port_map" = "0x1" - register "sata_devslp_disable" = "1" register "sio_acpi_mode" = "1" -- To view, visit https://review.coreboot.org/19957 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib15f8b51db19b3d9d2e135f85c71a15a45a2ffbd Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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coreboot-gerrit May 2017