coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: soc/broadwell: add missing USB port defs
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19968 ) Change subject: soc/broadwell: add missing USB port defs ...................................................................... soc/broadwell: add missing USB port defs Add device/address stubs for XHCI USB ports 7/8, 10-15. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/soc/intel/broadwell/acpi/xhci.asl 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/19968/1 diff --git a/src/soc/intel/broadwell/acpi/xhci.asl b/src/soc/intel/broadwell/acpi/xhci.asl index a70ded9..bbf9878 100644 --- a/src/soc/intel/broadwell/acpi/xhci.asl +++ b/src/soc/intel/broadwell/acpi/xhci.asl @@ -362,5 +362,13 @@ Device (PRT4) { Name (_ADR, 4) } // USB Port 3 Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + Device (PRT7) { Name (_ADR, 7) } // USB Port 6 + Device (PRT8) { Name (_ADR, 8) } // USB Port 7 + Device (SSP1) { Name (_ADR, 10) } // USB Port 10 + Device (SSP2) { Name (_ADR, 11) } // USB Port 11 + Device (SSP3) { Name (_ADR, 12) } // USB Port 12 + Device (SSP4) { Name (_ADR, 13) } // USB Port 13 + Device (SSP5) { Name (_ADR, 14) } // USB Port 14 + Device (SSP6) { Name (_ADR, 15) } // USB Port 15 } } -- To view, visit https://review.coreboot.org/19968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/slippy: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19967 ) Change subject: google/slippy: add board-specific USB port info ...................................................................... google/slippy: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Each slippy variant has slightly different USB port config; data for falco and leon to be added once available Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/slippy/acpi/mainboard.asl A src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl A src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl 5 files changed, 249 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/19967/1 diff --git a/src/mainboard/google/slippy/acpi/mainboard.asl b/src/mainboard/google/slippy/acpi/mainboard.asl index 7605e9e..f12a440 100644 --- a/src/mainboard/google/slippy/acpi/mainboard.asl +++ b/src/mainboard/google/slippy/acpi/mainboard.asl @@ -23,3 +23,6 @@ } #include <variant/acpi/mainboard.asl> + +/* USB port entries */ +#include <variant/acpi/usb.asl> diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl new file mode 100644 index 0000000..e69de29 --- /dev/null +++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/usb.asl diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl new file mode 100644 index 0000000..9227680 --- /dev/null +++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/usb.asl @@ -0,0 +1,126 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // WWAN M.2 Slot + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // Right USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl new file mode 100644 index 0000000..1799640 --- /dev/null +++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/usb.asl @@ -0,0 +1,120 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT1) +{ + // Left Front USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // Left Rear USB 2.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // Webcam + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT7) +{ + // SD Card + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // Left USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP2) +{ + // Rear USB 3.0 + Name (_UPC, Package (0x04) + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} -- To view, visit https://review.coreboot.org/19967 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Icc3b5b1161f62ac0b840380679acafeff363cf45 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/beltino: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19966 ) Change subject: google/beltino: add board-specific USB port info ...................................................................... google/beltino: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. All beltino variants use the exact same USB port layout. Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/beltino/acpi/mainboard.asl A src/mainboard/google/beltino/acpi/usb.asl 2 files changed, 147 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19966/1 diff --git a/src/mainboard/google/beltino/acpi/mainboard.asl b/src/mainboard/google/beltino/acpi/mainboard.asl index 03dc5e0..e6f931e 100644 --- a/src/mainboard/google/beltino/acpi/mainboard.asl +++ b/src/mainboard/google/beltino/acpi/mainboard.asl @@ -67,3 +67,6 @@ } } } + +/* USB port entries */ +#include "acpi/usb.asl" diff --git a/src/mainboard/google/beltino/acpi/usb.asl b/src/mainboard/google/beltino/acpi/usb.asl new file mode 100644 index 0000000..59c9654 --- /dev/null +++ b/src/mainboard/google/beltino/acpi/usb.asl @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2012 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.XHCI.HUB7.PRT2) +{ + // USB 2.0 Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT3) +{ + // USB 2.0 Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT4) +{ + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT5) +{ + // USB 2.0 Port 3 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.PRT6) +{ + // USB 2.0 Port 4 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP1) +{ + // USB 3.0 Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP2) +{ + // USB 3.0 Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP3) +{ + // USB 3.0 Port 3 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} +Scope (\_SB.PCI0.XHCI.HUB7.SSP4) +{ + // USB 3.0 Port 4 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0x03, // USB 3.0 Port + Zero, // Reserved + Zero // Reserved + }) +} -- To view, visit https://review.coreboot.org/19966 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If5b540949ea071f7165876e12ac1ef50e62d2b22 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: sb/lynxpoint: add missing USB port defs
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19965 ) Change subject: sb/lynxpoint: add missing USB port defs ...................................................................... sb/lynxpoint: add missing USB port defs Add device/address stubs for XHCI USB ports 7, 10-13. Stub data will be supplemented by board-specific info added in subsequent commits. Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/usb.asl 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/19965/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index 85e4390..fdfd843 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -416,5 +416,10 @@ Device (PRT4) { Name (_ADR, 4) } // USB Port 3 Device (PRT5) { Name (_ADR, 5) } // USB Port 4 Device (PRT6) { Name (_ADR, 6) } // USB Port 5 + Device (PRT7) { Name (_ADR, 7) } // USB Port 7 + Device (SSP1) { Name (_ADR, 10) } // USB Port 10 + Device (SSP2) { Name (_ADR, 11) } // USB Port 11 + Device (SSP3) { Name (_ADR, 12) } // USB Port 12 + Device (SSP4) { Name (_ADR, 13) } // USB Port 13 } } -- To view, visit https://review.coreboot.org/19965 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7d2f93351435cccd62e8fe4d95ad3467aa09de69 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: sb/lynxpoint: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19964 ) Change subject: sb/lynxpoint: add ACPI method to generate USB port info ...................................................................... sb/lynxpoint: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/lynxpoint/acpi/usb.asl 1 file changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/64/19964/1 diff --git a/src/southbridge/intel/lynxpoint/acpi/usb.asl b/src/southbridge/intel/lynxpoint/acpi/usb.asl index b02cbfe..85e4390 100644 --- a/src/southbridge/intel/lynxpoint/acpi/usb.asl +++ b/src/southbridge/intel/lynxpoint/acpi/usb.asl @@ -393,6 +393,22 @@ { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) { + Name (PCKG, Package (0x01) { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 -- To view, visit https://review.coreboot.org/19964 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: If63d5637a0469eeace0d935cca961e8d04fdfb1a Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: google/parrot: add board-specific USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19963 ) Change subject: google/parrot: add board-specific USB port info ...................................................................... google/parrot: add board-specific USB port info Add capability and location data for USB ports/devices via _PLD and _UPC ACPI methods, which is utilized by Windows and required by macOS. Move inclusion of mainboard.asl after southbridge asl files so scopes referenced in usb.asl are valid. Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/parrot/acpi/mainboard.asl A src/mainboard/google/parrot/acpi/usb.asl M src/mainboard/google/parrot/dsdt.asl 3 files changed, 155 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/63/19963/1 diff --git a/src/mainboard/google/parrot/acpi/mainboard.asl b/src/mainboard/google/parrot/acpi/mainboard.asl index 6b37e48..98208e0 100644 --- a/src/mainboard/google/parrot/acpi/mainboard.asl +++ b/src/mainboard/google/parrot/acpi/mainboard.asl @@ -101,3 +101,6 @@ } } + +/* USB port entries */ +#include "acpi/usb.asl" diff --git a/src/mainboard/google/parrot/acpi/usb.asl b/src/mainboard/google/parrot/acpi/usb.asl new file mode 100644 index 0000000..fc992db --- /dev/null +++ b/src/mainboard/google/parrot/acpi/usb.asl @@ -0,0 +1,150 @@ +/* + * This file is part of the coreboot project. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +Scope (\_SB.PCI0.EHC1.HUB7.PRT1) +{ + // Hub Port 1 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + + Device (USB2) + { + Name (_ADR, 2) + + // Left USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + + } + + Device (USB3) + { + Name (_ADR, 3) + + // Bottom Right USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + } + + Device (USB4) + { + Name (_ADR, 4) + + // Top Right USB Port + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + Zero, // USB Port + Zero, // Reserved + Zero // Reserved + }) + + // Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (One)) + } + } + +} + +Scope (_SB.PCI0.EHC2.HUB7.PRT1) +{ + // Hub Port 2 + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + + Device (USB1) + { + Name (_ADR, 1) + + // Bluetooth + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + } + + Device (USB3) + { + Name (_ADR, 3) + + // Webcam + Name (_UPC, Package (0x04) // _UPC: USB Port Capabilities + { + 0xFF, // Connectable + 0xFF, // OEM Connector + Zero, // Reserved + Zero // Reserved + }) + + // Not Visible + Method (_PLD, 0, NotSerialized) // _PLD: Physical Location of Device + { + Return (GPLD (Zero)) + } + } +} diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index 3e13a41..d179dea 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -27,7 +27,6 @@ // Some generic macros #include "acpi/platform.asl" - #include "acpi/mainboard.asl" // global NVS and variables #include <southbridge/intel/bd82x6x/acpi/globalnvs.asl> @@ -50,6 +49,8 @@ } } + #include "acpi/mainboard.asl" + #include <vendorcode/google/chromeos/acpi/chromeos.asl> /* Chipset specific sleep states */ -- To view, visit https://review.coreboot.org/19963 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I58ea0b43f7f2c2692630df3bdb06af92566c1202 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: sb/bd82x6x: add ACPI method to generate USB port info
by Matt DeVillier (Code Review) 28 May '17

28 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19962 ) Change subject: sb/bd82x6x: add ACPI method to generate USB port info ...................................................................... sb/bd82x6x: add ACPI method to generate USB port info Add ACPI method GPLD to generate port location data when passed visiblity info. Will be used by _PLD method in board-specific USB .asl files. Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/southbridge/intel/bd82x6x/acpi/usb.asl 1 file changed, 40 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/19962/1 diff --git a/src/southbridge/intel/bd82x6x/acpi/usb.asl b/src/southbridge/intel/bd82x6x/acpi/usb.asl index e76acb8..5f78e3e 100644 --- a/src/southbridge/intel/bd82x6x/acpi/usb.asl +++ b/src/southbridge/intel/bd82x6x/acpi/usb.asl @@ -40,6 +40,27 @@ { Name (_ADR, 0x00000000) + + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) + { + + Name (PCKG, Package (0x01) + { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 @@ -74,6 +95,25 @@ { Name (_ADR, 0x00000000) + // GPLD: Generate Port Location Data (PLD) + Method (GPLD, 1, Serialized) + { + Name (PCKG, Package (0x01) + { + Buffer (0x10) {} + }) + + // REV: Revision 0x02 for ACPI 5.0 + CreateField (DerefOf (Index (PCKG, Zero)), Zero, 0x07, REV) + Store (0x02, REV) + + // VISI: Port visibility to user per port + CreateField (DerefOf (Index (PCKG, Zero)), 0x40, One, VISI) + Store (Arg0, VISI) + + Return (PCKG) + } + // How many are there? Device (PRT1) { Name (_ADR, 1) } // USB Port 0 Device (PRT2) { Name (_ADR, 2) } // USB Port 1 -- To view, visit https://review.coreboot.org/19962 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ib83660d6548112ceb6c75a31e5ce6c4a6041ccfb Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

1 0

Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by Philippe Mathieu-Daudé (Code Review) 28 May '17

28 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Philippe Mathieu-Daudé (Code Review) 28 May '17

28 May '17

Philippe Mathieu-Daudé has posted comments on this change. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: ec/ene_kb3940q: correct ACPI battery data fed into ToString()
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19961 ) Change subject: ec/ene_kb3940q: correct ACPI battery data fed into ToString() ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10224/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54505/ : SUCCESS -- To view, visit https://review.coreboot.org/19961 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I395cc7fbdf26c8cc816e47107e552c0533580fa1 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017