coreboot-gerrit May 2017

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by Barnali Sarkar (Code Review) 29 May '17

29 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19566 to look at the new patch set (#9). Change subject: soc/intel/skylake: Use CPU common code ...................................................................... soc/intel/skylake: Use CPU common code This patch uses common CPU Model library. Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi.c M src/soc/intel/skylake/bootblock/bootblock.c M src/soc/intel/skylake/bootblock/cpu.c M src/soc/intel/skylake/bootblock/report_platform.c M src/soc/intel/skylake/chip.c M src/soc/intel/skylake/chip_fsp20.c M src/soc/intel/skylake/cpu.c D src/soc/intel/skylake/cpu_info.c M src/soc/intel/skylake/include/fsp11/soc/ramstage.h M src/soc/intel/skylake/include/fsp20/soc/ramstage.h M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/cpu.h M src/soc/intel/skylake/include/soc/msr.h M src/soc/intel/skylake/include/soc/smm.h M src/soc/intel/skylake/romstage/romstage_fsp20.c M src/soc/intel/skylake/smi.c D src/soc/intel/skylake/smmrelocate.c M src/soc/intel/skylake/tsc_freq.c 20 files changed, 50 insertions(+), 777 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/19566/9 -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by Barnali Sarkar (Code Review) 29 May '17

29 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19540 to look at the new patch set (#11). Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... soc/intel/common/block: Add Intel common CPU code Create Intel Common CPU Model support code which provides various CPU related APIs which are common over Intel Processor families. Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/common/block/cpu/Kconfig M src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/cpu.c A src/soc/intel/common/block/cpu/cpu_early.c A src/soc/intel/common/block/cpu/smmrelocate.c A src/soc/intel/common/block/include/intelblocks/cpu.h M src/soc/intel/common/block/include/intelblocks/msr.h A src/soc/intel/common/block/include/intelblocks/smm.h 8 files changed, 1,004 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/19540/11 -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Subrata Banik (Code Review) 29 May '17

29 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 15: (3 comments) https://review.coreboot.org/#/c/19759/15/src/soc/intel/common/block/gpio/gp… File src/soc/intel/common/block/gpio/gpio.c: PS15, Line 54: 32 can we use macro PS15, Line 68: GPIO_MAX_NUM_PER_GROUP each GPP may not have same PIN count Line 136: if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) we can't assume PAD configuration may be only 8 byte width, some future soc may have 16 byte. hence we may have pad_conf2, 3 etc. I was wondering if we can get rid of unifying GPIO driver code for all possible socs. It may be bloated and tough to maintain. I have an opinion to use separate GPIO driver for below socs GPIO_V1 = SKL & KBL GPIO_V2 = APL & GLK (if possible) GPIO_V3 = Some future SOC this will help to maintain respective GPIO API neatly. Then we may try to common those GPIO macro definitions as i guess majority of those are same. I don't see much scope to use this code for future socs w/o any modification. testing and maintenance might be tougher. -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/google/poppy:[WIP] Add MIPI camera support.
by Rajmohan Mani (Code Review) 29 May '17

29 May '17

Rajmohan Mani has posted comments on this change. ( https://review.coreboot.org/19621 ) Change subject: mb/google/poppy:[WIP] Add MIPI camera support. ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/19621/1/src/mainboard/google/poppy/acpi/cam… File src/mainboard/google/poppy/acpi/camera.asl: PS1, Line 221: PCTL This is a bug. VALU should be written to the CFG1 register. PS1, Line 358: PCTL This is a bug. VALU should be written to the CFG1 register. -- To view, visit https://review.coreboot.org/19621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: mb/google/poppy:[WIP] Add MIPI camera support.
by Rajmohan Mani (Code Review) 29 May '17

29 May '17

Rajmohan Mani has posted comments on this change. ( https://review.coreboot.org/19621 ) Change subject: mb/google/poppy:[WIP] Add MIPI camera support. ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/19621/1/src/mainboard/google/poppy/acpi/cam… File src/mainboard/google/poppy/acpi/camera.asl: PS1, Line 129: Sleep(3) > @Raj, having delays/sleep in ASL code, is that a good idea? Besides, how is Since this is related to power sequencing of the sensors and vcm (that involve powering up/down voltage rails), which inherently require delays in stabilizing its output, this is needed. These values are arrived based on the specs and the optimal values found during validation. -- To view, visit https://review.coreboot.org/19621 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If32a2a8313488d2f50aad3feaa79e17b1d06c80f Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hyungwoo Yang <hyungwoo.yang(a)intel.com> Gerrit-Reviewer: Rajmohan Mani <rajmohan.mani(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/intel/sandybridge: Remove unecessary reserved resources
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19977 ) Change subject: nb/intel/sandybridge: Remove unecessary reserved resources ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10240/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54521/ : SUCCESS -- To view, visit https://review.coreboot.org/19977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9e14a73dbdb9d62dfd7d942a79659a5997f97971 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge: Remove unecessary reserved resources
by Matt DeVillier (Code Review) 29 May '17

29 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19977 ) Change subject: nb/intel/sandybridge: Remove unecessary reserved resources ...................................................................... nb/intel/sandybridge: Remove unecessary reserved resources The reserved "bad_ram_resources" at 0x20000000 and 0x40000000 were originally implemented to work around an i915 bug on SNB, but that bug has long since been fixed. Commit 593e7de restricted these regions to SNB, but was never tested against SNB which would have likely shown it to no longer being needed. Said commit also failed to guard the corresponding region definitions in ACPI, so remove the reserved regions from both places. TEST: boot Linux w/recent (4.0+) kernel on google/parrot (SNB, IVB) and samsung/stumpy (SNB), observe lack of graphics corruption. Change-Id: I9e14a73dbdb9d62dfd7d942a79659a5997f97971 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/sandybridge/acpi/sandybridge.asl M src/northbridge/intel/sandybridge/northbridge.c 2 files changed, 0 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/19977/1 diff --git a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl index 61537e8..b3ae2ff 100644 --- a/src/northbridge/intel/sandybridge/acpi/sandybridge.asl +++ b/src/northbridge/intel/sandybridge/acpi/sandybridge.asl @@ -37,10 +37,6 @@ Memory32Fixed(ReadWrite, CONFIG_CHROMEOS_RAMOOPS_RAM_START, CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE) #endif - - /* Required for SandyBridge sighting 3715511 */ - Memory32Fixed(ReadWrite, 0x20000000, 0x00200000) - Memory32Fixed(ReadWrite, 0x40000000, 0x00200000) }) // Current Resource Settings diff --git a/src/northbridge/intel/sandybridge/northbridge.c b/src/northbridge/intel/sandybridge/northbridge.c index 5c5f41a..4eeb415 100644 --- a/src/northbridge/intel/sandybridge/northbridge.c +++ b/src/northbridge/intel/sandybridge/northbridge.c @@ -106,12 +106,6 @@ CONFIG_CHROMEOS_RAMOOPS_RAM_SIZE >> 10); #endif - if ((bridge_silicon_revision() & BASE_REV_MASK) == BASE_REV_SNB) { - /* Required for SandyBridge sighting 3715511 */ - bad_ram_resource(dev, index++, 0x20000000 >> 10, 0x00200000 >> 10); - bad_ram_resource(dev, index++, 0x40000000 >> 10, 0x00200000 >> 10); - } - /* Reserve IOMMU BARs */ const u32 capid0_a = pci_read_config32(dev, 0xe4); if (!(capid0_a & (1 << 23))) { -- To view, visit https://review.coreboot.org/19977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I9e14a73dbdb9d62dfd7d942a79659a5997f97971 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: google/chell: add board-specific USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19976 ) Change subject: google/chell: add board-specific USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10239/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54519/ : SUCCESS -- To view, visit https://review.coreboot.org/19976 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ie0b64eadc634049f6b65cf555407337fb7c4363c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/skylake: add ACPI method to generate USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19975 ) Change subject: soc/skylake: add ACPI method to generate USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10238/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54520/ : SUCCESS -- To view, visit https://review.coreboot.org/19975 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I14ba3cea821e103208426e9fcaa0833d84157ff8 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/rambi: add board-specific USB port info
by build bot (Jenkins) (Code Review) 28 May '17

28 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19974 ) Change subject: google/rambi: add board-specific USB port info ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10237/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54518/ : SUCCESS -- To view, visit https://review.coreboot.org/19974 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: If7ce3d135d6ffe53ab1566d5258d01b052ac47f4 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017