coreboot-gerrit May 2017

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Change in coreboot[master]: mc_bdx1: Switch to RTC RX6110SA
by Mario Scheithauer (Code Review) 29 May '17

29 May '17

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/19979 ) Change subject: mc_bdx1: Switch to RTC RX6110SA ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/19979 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by Mario Scheithauer (Code Review) 29 May '17

29 May '17

Mario Scheithauer has posted comments on this change. ( https://review.coreboot.org/19978 ) Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... Patch Set 1: (2 comments) https://review.coreboot.org/#/c/19978/1/src/drivers/i2c/rx6110sa/rx6110sa.c File src/drivers/i2c/rx6110sa/rx6110sa.c: PS1, Line 30: rx611sa_write Why did you not use function name rx6110sa_write and rx6110sa_read? PS1, Line 32: if (!CONFIG_RX6110SA_USE_SMBUS) : i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, reg, val); : else : smbus_write_byte(dev, reg, val); You can leave the negation of CONFIG_RX6110SA_USE_SMBUS if you replace the lines. The same applies for rx611sa_read(...) function. -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19978 ) Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10244/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54525/ : SUCCESS -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mc_bdx1: Switch to RTC RX6110SA
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19979 ) Change subject: mc_bdx1: Switch to RTC RX6110SA ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10245/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54526/ : SUCCESS -- To view, visit https://review.coreboot.org/19979 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: mc_bdx1: Switch to RTC RX6110SA
by Werner Zeh (Code Review) 29 May '17

29 May '17

Werner Zeh has uploaded a new change for review. ( https://review.coreboot.org/19979 ) Change subject: mc_bdx1: Switch to RTC RX6110SA ...................................................................... mc_bdx1: Switch to RTC RX6110SA The prior used RTC PCF8523 is replaced with RX6110SA on this mainboard. Switch to the new RTC in Kconfig and adapt devicetree to the new chip. Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_bdx1/Kconfig M src/mainboard/siemens/mc_bdx1/devicetree.cb 2 files changed, 6 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/19979/1 diff --git a/src/mainboard/siemens/mc_bdx1/Kconfig b/src/mainboard/siemens/mc_bdx1/Kconfig index f64b22b..0200d92 100644 --- a/src/mainboard/siemens/mc_bdx1/Kconfig +++ b/src/mainboard/siemens/mc_bdx1/Kconfig @@ -12,7 +12,8 @@ select USE_SIEMENS_HWILIB select DRIVER_INTEL_I210 select DRIVER_SIEMENS_NC_FPGA - select DRIVERS_I2C_PCF8523 + select DRIVERS_I2C_RX6110SA + select RX6110SA_USE_SMBUS config MAINBOARD_DIR string diff --git a/src/mainboard/siemens/mc_bdx1/devicetree.cb b/src/mainboard/siemens/mc_bdx1/devicetree.cb index 804b781..543786b 100644 --- a/src/mainboard/siemens/mc_bdx1/devicetree.cb +++ b/src/mainboard/siemens/mc_bdx1/devicetree.cb @@ -11,16 +11,14 @@ device pci 1f.2 on end # SATA Controller device pci 1f.3 on # Enable external RTC chip - chip drivers/i2c/pcf8523 - register "cap_sel" = "CAP_SEL_7_PF" - register "power_mode" = "PM_BAT_SW_OFF_LOW_DETECT_OFF" - register "cof_selection" = "COF_OFF" + chip drivers/i2c/rx6110sa + register "cof_selection" = "0" register "set_user_date" = "1" register "user_year" = "04" register "user_month" = "07" register "user_day" = "01" - register "user_weekday" = "0" - device i2c 0x68 on end # RTC PCF8523 + register "user_weekday" = "4" + device i2c 0x32 on end # RTC RX6110 SA end end # SMBus Controller device pci 1f.5 on end # SATA Controller -- To view, visit https://review.coreboot.org/19979 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7c4911191cae254900f9a958da42ecd18497484c Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: rx6110sa: Add possibility to use both I2C and SMBus for the RTC
by Werner Zeh (Code Review) 29 May '17

29 May '17

Werner Zeh has uploaded a new change for review. ( https://review.coreboot.org/19978 ) Change subject: rx6110sa: Add possibility to use both I2C and SMBus for the RTC ...................................................................... rx6110sa: Add possibility to use both I2C and SMBus for the RTC The driver for the RTC RX6110SA is designed to be used with I2C bus. This patch adds the possibility to use SMBus operations to access the RTC. For this purpose the Kconfig switch RX6110SA_USE_SMBUS is added. It is not enabled per default so that I2C will be used. One can set this switch on board level to use SMBus instead. Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/drivers/i2c/rx6110sa/Kconfig M src/drivers/i2c/rx6110sa/rx6110sa.c 2 files changed, 60 insertions(+), 37 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/19978/1 diff --git a/src/drivers/i2c/rx6110sa/Kconfig b/src/drivers/i2c/rx6110sa/Kconfig index a5608f8..48654c6 100644 --- a/src/drivers/i2c/rx6110sa/Kconfig +++ b/src/drivers/i2c/rx6110sa/Kconfig @@ -3,3 +3,10 @@ default n help Enable support for external RTC chip RX6110 SA. + +config RX6110SA_USE_SMBUS + bool + default n + help + Select this option if the RTC RX6110SA is connected to a SMBus controller. + If not selected I2C controller is used instead. diff --git a/src/drivers/i2c/rx6110sa/rx6110sa.c b/src/drivers/i2c/rx6110sa/rx6110sa.c index 743b708..d4a4bb1 100644 --- a/src/drivers/i2c/rx6110sa/rx6110sa.c +++ b/src/drivers/i2c/rx6110sa/rx6110sa.c @@ -13,7 +13,9 @@ * GNU General Public License for more details. */ + #include <device/i2c.h> +#include <device/smbus.h> #include <device/device.h> #include <version.h> #include <console/console.h> @@ -24,17 +26,33 @@ #define I2C_BUS_NUM (dev->bus->secondary - 1) #define I2C_DEV_NUM (dev->path.i2c.device) +/* Function to write a register in the RTC with the given value. */ +static void rx611sa_write(struct device *dev, uint8_t reg, uint8_t val) +{ + if (!CONFIG_RX6110SA_USE_SMBUS) + i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, reg, val); + else + smbus_write_byte(dev, reg, val); +} + +/* Function to read a register in the RTC. */ +static uint8_t rx611sa_read(struct device *dev, uint8_t reg) +{ + uint8_t val; + if (!CONFIG_RX6110SA_USE_SMBUS) + i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, reg, &val); + else + val = smbus_read_byte(dev, reg); + return val; +} + /* Set RTC date from coreboot build date. */ static void rx6110sa_set_build_date(struct device *dev) { - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, YEAR_REG, - coreboot_build_date.year); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, MONTH_REG, - coreboot_build_date.month); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, DAY_REG, - coreboot_build_date.day); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, WEEK_REG, - (1 << coreboot_build_date.weekday)); + rx611sa_write(dev, YEAR_REG, coreboot_build_date.year); + rx611sa_write(dev, MONTH_REG, coreboot_build_date.month); + rx611sa_write(dev, DAY_REG, coreboot_build_date.day); + rx611sa_write(dev, WEEK_REG, (1 << coreboot_build_date.weekday)); } /* Set RTC date from user defined date (available in e.g. device tree). */ @@ -42,14 +60,10 @@ { struct drivers_i2c_rx6110sa_config *config = dev->chip_info; - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, YEAR_REG, - bin2bcd(config->user_year)); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, MONTH_REG, - bin2bcd(config->user_month)); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, DAY_REG, - bin2bcd(config->user_day)); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, WEEK_REG, - (1 << config->user_weekday)); + rx611sa_write(dev, YEAR_REG, bin2bcd(config->user_year)); + rx611sa_write(dev, MONTH_REG, bin2bcd(config->user_month)); + rx611sa_write(dev, DAY_REG, bin2bcd(config->user_day)); + rx611sa_write(dev, WEEK_REG, (1 << config->user_weekday)); } static void rx6110sa_final(struct device *dev) @@ -57,12 +71,12 @@ uint8_t hour, minute, second, year, month, day; /* Read back current RTC date and time and print it to the console. */ - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, HOUR_REG, &hour); - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, MINUTE_REG, &minute); - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, SECOND_REG, &second); - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, YEAR_REG, &year); - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, MONTH_REG, &month); - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, DAY_REG, &day); + hour = rx611sa_read(dev, HOUR_REG); + minute = rx611sa_read(dev, MINUTE_REG); + second = rx611sa_read(dev, SECOND_REG); + year = rx611sa_read(dev, YEAR_REG); + month = rx611sa_read(dev, MONTH_REG); + day = rx611sa_read(dev, DAY_REG); printk(BIOS_INFO, "%s: Current date %02d.%02d.%02d %02d:%02d:%02d\n", dev->chip_ops->name, bcd2bin(month), bcd2bin(day), @@ -75,13 +89,13 @@ uint8_t reg; /* Do a dummy read first. */ - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, SECOND_REG, &reg); + reg = rx611sa_read(dev, SECOND_REG); /* * Check VLF-bit which indicates the RTC data loss, such as due to a * supply voltage drop. */ - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, FLAG_REGISTER, &reg); + reg = rx611sa_read(dev, FLAG_REGISTER); if (!(reg & VLF_BIT)) /* No voltage low detected, everything is well. */ @@ -91,24 +105,26 @@ * Voltage low detected, initialize RX6110 SA again. * Set first some registers to known state. */ - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, BATTERY_BACKUP_REG, 0x00); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, RESERVED_BIT_REG, RTC_INIT_VALUE); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, DIGITAL_REG, 0x00); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, IRQ_CONTROL_REG, 0x00); + rx611sa_write(dev, BATTERY_BACKUP_REG, 0x00); + rx611sa_write(dev, RESERVED_BIT_REG, RTC_INIT_VALUE); + rx611sa_write(dev, DIGITAL_REG, 0x00); + rx611sa_write(dev, IRQ_CONTROL_REG, 0x00); /* Clear timer enable bit and set frequency of clock output. */ - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, EXTENSION_REG, &reg); + + reg = rx611sa_read(dev, EXTENSION_REG); reg &= ~(FSEL_MASK | TE_BIT); reg |= (config->cof_selection << 6); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, EXTENSION_REG, reg); + rx611sa_write(dev, EXTENSION_REG, reg); /* Clear voltage low detect bit. */ - i2c_readb(I2C_BUS_NUM, I2C_DEV_NUM, FLAG_REGISTER, &reg); + reg = rx611sa_read(dev, FLAG_REGISTER); reg &= ~VLF_BIT; - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, FLAG_REGISTER, reg); + rx611sa_write(dev, FLAG_REGISTER, reg); /* Before setting the clock stop oscillator. */ - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, CTRL_REG, STOP_BIT); + rx611sa_write(dev, CTRL_REG, STOP_BIT); + if (config->set_user_date) { /* Set user date defined in device tree. */ printk(BIOS_DEBUG, "%s: Set to user date\n", @@ -120,11 +136,11 @@ dev->chip_ops->name); rx6110sa_set_build_date(dev); } - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, HOUR_REG, 1); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, MINUTE_REG, 0); - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, SECOND_REG, 0); + rx611sa_write(dev, HOUR_REG, 1); + rx611sa_write(dev, MINUTE_REG, 0); + rx611sa_write(dev, SECOND_REG, 0); /* Start oscillator again as the RTC is set up now. */ - i2c_writeb(I2C_BUS_NUM, I2C_DEV_NUM, CTRL_REG, 0x00); + rx611sa_write(dev, CTRL_REG, 0x00); } static struct device_operations rx6110sa_ops = { -- To view, visit https://review.coreboot.org/19978 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I4827ae2c544e8002399d94a1159acacd8176c5e9 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: Use CPU common code ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10243/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54523/ : SUCCESS -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common code
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: Use CPU common code ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10242/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54524/ : SUCCESS -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... Patch Set 11: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10241/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54522/ : SUCCESS -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common code
by Barnali Sarkar (Code Review) 29 May '17

29 May '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19827 to look at the new patch set (#5). Change subject: soc/intel/apollolake: Use CPU common code ...................................................................... soc/intel/apollolake: Use CPU common code This patch uses common CPU Model library. Change-Id: I529c67cf20253cf819d1c13849300788104b083c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi.c M src/soc/intel/apollolake/acpi/pmc_ipc.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c M src/soc/intel/apollolake/cpu.c M src/soc/intel/apollolake/include/soc/cpu.h M src/soc/intel/apollolake/include/soc/iomap.h M src/soc/intel/apollolake/include/soc/pm.h M src/soc/intel/apollolake/pmc.c M src/soc/intel/apollolake/pmutil.c M src/soc/intel/apollolake/romstage.c M src/soc/intel/apollolake/tsc_freq.c M src/soc/intel/common/smihandler.c 14 files changed, 81 insertions(+), 274 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19827/5 -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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coreboot-gerrit May 2017