coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

1 participants
3888 discussions

Change in coreboot[master]: pci_device: add PCI device IDs for Intel platforms
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19541 ) Change subject: pci_device: add PCI device IDs for Intel platforms ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53212/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9034/ : SUCCESS -- To view, visit https://review.coreboot.org/19541 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: common/block/cse: Use CSE PCH ID from device/pci_ids.h
by build bot (Jenkins) (Code Review) 04 May '17

04 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19569 ) Change subject: common/block/cse: Use CSE PCH ID from device/pci_ids.h ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53211/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9033/ : SUCCESS -- To view, visit https://review.coreboot.org/19569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

1 0

Change in coreboot[master]: soc/intel/apollolake: Use XDCI common code
by Subrata Banik (Code Review) 04 May '17

04 May '17

Hello Aaron Durbin, Barnali Sarkar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19429 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Use XDCI common code ...................................................................... soc/intel/apollolake: Use XDCI common code This patch performs apollolake specific XDCI controller initialization. Change-Id: I4649bffe1bb90d7df6a72b5334793bf8f0fdbaeb Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/include/soc/pci_ids.h M src/soc/intel/apollolake/xdci.c 3 files changed, 7 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/19429/4 -- To view, visit https://review.coreboot.org/19429 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4649bffe1bb90d7df6a72b5334793bf8f0fdbaeb Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

1 0

Change in coreboot[master]: common/block/xhci: Get XHCI PCI ID from device/pci_ids.h
by Subrata Banik (Code Review) 04 May '17

04 May '17

Hello Aaron Durbin, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19536 to look at the new patch set (#3). Change subject: common/block/xhci: Get XHCI PCI ID from device/pci_ids.h ...................................................................... common/block/xhci: Get XHCI PCI ID from device/pci_ids.h Change-Id: I33d92a173055ea18b8675c720f01dd5bc77befa3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/xhci/xhci.c 1 file changed, 4 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/19536/3 -- To view, visit https://review.coreboot.org/19536 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I33d92a173055ea18b8675c720f01dd5bc77befa3 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/apollolake: Use intel/common/xhci driver
by Subrata Banik (Code Review) 04 May '17

04 May '17

Hello Aaron Durbin, Barnali Sarkar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19427 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Use intel/common/xhci driver ...................................................................... soc/intel/apollolake: Use intel/common/xhci driver Change-Id: Iccb6b6c8c002701d17444fcf62ec11315e5aeed9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc M src/soc/intel/apollolake/include/soc/pci_ids.h D src/soc/intel/apollolake/xhci.c 4 files changed, 1 insertion(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19427/4 -- To view, visit https://review.coreboot.org/19427 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iccb6b6c8c002701d17444fcf62ec11315e5aeed9 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

1 0

Change in coreboot[master]: soc/intel/common/block: Add Intel XDCI code support
by Subrata Banik (Code Review) 04 May '17

04 May '17

Hello Aaron Durbin, Barnali Sarkar, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19428 to look at the new patch set (#4). Change subject: soc/intel/common/block: Add Intel XDCI code support ...................................................................... soc/intel/common/block: Add Intel XDCI code support XDCI MMIO offsets definitions are not alike between various SoCs hence provided "soc_xdci_init" function to implement SoC specific initialization. Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/xdci.h A src/soc/intel/common/block/xdci/Kconfig A src/soc/intel/common/block/xdci/Makefile.inc A src/soc/intel/common/block/xdci/xdci.c 4 files changed, 69 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/19428/4 -- To view, visit https://review.coreboot.org/19428 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I9cbc686a00c26b92be2847b6bd6c2e5aa5a690f7 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

1 0

Change in coreboot[master]: mb/lenovo/*/romstage: Remove COMA IO port
by Patrick Rudolph (Code Review) 04 May '17

04 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19571 ) Change subject: mb/lenovo/*/romstage: Remove COMA IO port ...................................................................... mb/lenovo/*/romstage: Remove COMA IO port All those boards do not have a serial port, neither do they have working dock support. Don't attempt to decode the COMA IO range. Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 10 files changed, 9 insertions(+), 33 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/19571/1 diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 6c93eed..3669104 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -25,12 +25,11 @@ void pch_enable_lpc(void) { - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0f); + pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x82, 0x3c0e); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x84, 0x007c1611); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x00040069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); } void rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index 610eb89..43a3d52 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -42,7 +42,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x88, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); - pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); /* Memory map KB9012 EC registers */ diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index 766b019..94b8d62 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -24,14 +24,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index e32337a..d7f1c23 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -27,14 +27,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index a17ec52..89ef10c 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -27,14 +27,11 @@ /* EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index fd17f21..09319fc 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -41,8 +41,7 @@ /* T520 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 050e8cf..c454ec7 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -28,14 +28,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 574d02b..a07df70 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -42,14 +42,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 15d2c84..fa52778 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -38,14 +38,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index e68843c..4d8f330 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -41,14 +41,11 @@ /* X230 EC Decode Range Port60/64, Port62/66 */ /* Enable EC, PS/2 Keyboard/Mouse */ pci_write_config16(PCH_LPC_DEV, LPC_EN, - CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN | - COMA_LPC_EN); + CNF2_LPC_EN | CNF1_LPC_EN | MC_LPC_EN | KBC_LPC_EN); pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x7c1601); pci_write_config32(PCH_LPC_DEV, LPC_GEN2_DEC, 0xc15e1); pci_write_config32(PCH_LPC_DEV, LPC_GEN4_DEC, 0x0c06a1); - - pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } -- To view, visit https://review.coreboot.org/19571 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ide7e818f87e70e3f559d0769ccde89c35da961d6 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage
by Patrick Rudolph (Code Review) 04 May '17

04 May '17

Patrick Rudolph has uploaded a new change for review. ( https://review.coreboot.org/19570 ) Change subject: mb/*/romstage: Don't lock ETR3 CF9GR in early romstage ...................................................................... mb/*/romstage: Don't lock ETR3 CF9GR in early romstage Do not lock ETR3 CF9GR in early romstage. As of Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 this is done in bd82x6x's finalize handler. Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- M src/mainboard/gigabyte/ga-b75m-d3h/romstage.c M src/mainboard/gigabyte/ga-b75m-d3v/romstage.c M src/mainboard/lenovo/l520/romstage.c M src/mainboard/lenovo/s230u/romstage.c M src/mainboard/lenovo/t420/romstage.c M src/mainboard/lenovo/t420s/romstage.c M src/mainboard/lenovo/t430s/romstage.c M src/mainboard/lenovo/t520/romstage.c M src/mainboard/lenovo/t530/romstage.c M src/mainboard/lenovo/x1_carbon_gen1/romstage.c M src/mainboard/lenovo/x220/romstage.c M src/mainboard/lenovo/x230/romstage.c 12 files changed, 11 insertions(+), 17 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/19570/1 diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c index bb3b223..cbc5592 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3h/romstage.c @@ -153,7 +153,7 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c index 4a02790..22a10ae 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c +++ b/src/mainboard/gigabyte/ga-b75m-d3v/romstage.c @@ -85,7 +85,7 @@ pci_write_config32(PCH_LPC_DEV, LPC_GEN1_DEC, 0x3c0a01); pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x10000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); /* Initialize SuperIO */ ite_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); diff --git a/src/mainboard/lenovo/l520/romstage.c b/src/mainboard/lenovo/l520/romstage.c index 47b9fd6..6c93eed 100644 --- a/src/mainboard/lenovo/l520/romstage.c +++ b/src/mainboard/lenovo/l520/romstage.c @@ -31,7 +31,6 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0701); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x00000000); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0010); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x80000000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/s230u/romstage.c b/src/mainboard/lenovo/s230u/romstage.c index ad5f021..610eb89 100644 --- a/src/mainboard/lenovo/s230u/romstage.c +++ b/src/mainboard/lenovo/s230u/romstage.c @@ -43,7 +43,7 @@ pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x8c, 0x000c0069); pci_write_config32(PCI_DEV(0, 0x1f, 0), 0x90, 0x000c06a1); pci_write_config16(PCI_DEV(0, 0x1f, 0), 0x80, 0x0000); - pci_write_config32(PCI_DEV(0, 0x1f, 0), 0xac, 0x00010000); + pci_write_config32(PCI_DEV(0, 0x1f, 0), ETR3, 0x10000); /* Memory map KB9012 EC registers */ pci_write_config32( diff --git a/src/mainboard/lenovo/t420/romstage.c b/src/mainboard/lenovo/t420/romstage.c index d25ce45..766b019 100644 --- a/src/mainboard/lenovo/t420/romstage.c +++ b/src/mainboard/lenovo/t420/romstage.c @@ -33,7 +33,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t420s/romstage.c b/src/mainboard/lenovo/t420s/romstage.c index 27b45fd..e32337a 100644 --- a/src/mainboard/lenovo/t420s/romstage.c +++ b/src/mainboard/lenovo/t420s/romstage.c @@ -36,7 +36,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t430s/romstage.c b/src/mainboard/lenovo/t430s/romstage.c index 92f9e62..a17ec52 100644 --- a/src/mainboard/lenovo/t430s/romstage.c +++ b/src/mainboard/lenovo/t430s/romstage.c @@ -36,7 +36,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t520/romstage.c b/src/mainboard/lenovo/t520/romstage.c index 5ba4873..fd17f21 100644 --- a/src/mainboard/lenovo/t520/romstage.c +++ b/src/mainboard/lenovo/t520/romstage.c @@ -50,8 +50,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/t530/romstage.c b/src/mainboard/lenovo/t530/romstage.c index 3d603c5..050e8cf 100644 --- a/src/mainboard/lenovo/t530/romstage.c +++ b/src/mainboard/lenovo/t530/romstage.c @@ -37,8 +37,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c index 3e11324..574d02b 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/romstage.c +++ b/src/mainboard/lenovo/x1_carbon_gen1/romstage.c @@ -51,8 +51,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } const struct southbridge_usb_port mainboard_usb_ports[] = { diff --git a/src/mainboard/lenovo/x220/romstage.c b/src/mainboard/lenovo/x220/romstage.c index 5a1c90a..15d2c84 100644 --- a/src/mainboard/lenovo/x220/romstage.c +++ b/src/mainboard/lenovo/x220/romstage.c @@ -47,8 +47,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) diff --git a/src/mainboard/lenovo/x230/romstage.c b/src/mainboard/lenovo/x230/romstage.c index 53ad9ac..e68843c 100644 --- a/src/mainboard/lenovo/x230/romstage.c +++ b/src/mainboard/lenovo/x230/romstage.c @@ -50,8 +50,7 @@ pci_write_config16(PCH_LPC_DEV, LPC_IO_DEC, 0x10); - pci_write_config32(PCH_LPC_DEV, 0xac, - 0x80010000); + pci_write_config32(PCH_LPC_DEV, ETR3, 0x10000); } void rcba_config(void) -- To view, visit https://review.coreboot.org/19570 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Iea091511f0d2a6128d3a19e9413090c85e4c2e57 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org>

1 0

Change in coreboot[master]: common/block/cse: Use CSE PCH ID from device/pci_ids.h
by Subrata Banik (Code Review) 04 May '17

04 May '17

Subrata Banik has uploaded a new change for review. ( https://review.coreboot.org/19569 ) Change subject: common/block/cse: Use CSE PCH ID from device/pci_ids.h ...................................................................... common/block/cse: Use CSE PCH ID from device/pci_ids.h Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/include/soc/pci_ids.h M src/soc/intel/common/block/cse/cse.c 2 files changed, 1 insertion(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/19569/1 diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 8b548ee..4c2956f 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -26,8 +26,6 @@ #define PCI_DEVICE_ID_APOLLOLAKE_HWSEQ_SPI 0x5a96 /* 00:0d.2 */ #define PCI_DEVICE_ID_APOLLOLAKE_SRAM 0x5aec /* 00:0d.3 */ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ -#define PCI_DEVICE_ID_APOLLOLAKE_CSE0 0x5a9a /* 00:0f.0 */ -#define PCI_DEVICE_ID_HECI1 PCI_DEVICE_ID_APOLLOLAKE_CSE0 #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XDCI 0x5aaa /* 00:15.1 */ diff --git a/src/soc/intel/common/block/cse/cse.c b/src/soc/intel/common/block/cse/cse.c index 64a20d8..272fe7a 100644 --- a/src/soc/intel/common/block/cse/cse.c +++ b/src/soc/intel/common/block/cse/cse.c @@ -471,7 +471,7 @@ .ops = &cse_ops, .vendor = PCI_VENDOR_ID_INTEL, /* SoC/chipset needs to provide PCI device ID */ - .device = PCI_DEVICE_ID_HECI1 + .device = PCI_DEVICE_ID_INTEL_APOLLOLAKE_CSE0 }; #endif -- To view, visit https://review.coreboot.org/19569 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

1 0

Change in coreboot[master]: pci_device: add PCI device IDs for Intel platforms
by Subrata Banik (Code Review) 04 May '17

04 May '17

Hello Rizwan Qureshi, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19541 to look at the new patch set (#5). Change subject: pci_device: add PCI device IDs for Intel platforms ...................................................................... pci_device: add PCI device IDs for Intel platforms Add host of PCI device Ids for IPs in Intel platforms. Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- M src/include/device/pci_ids.h 1 file changed, 107 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/19541/5 -- To view, visit https://review.coreboot.org/19541 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit May 2017