Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19541 )
Change subject: pci_device: add PCI device IDs for Intel platforms
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Patch Set 5:
(1 comment)
https://review.coreboot.org/#/c/19541/5/src/include/device/pci_ids.h
File src/include/device/pci_ids.h:
PS5, Line 2673: PCI_DEVICE_ID_INTEL_KBL_LP_Y_PREMIUM 0x9d56
: #define PCI_DEVICE_ID_APOLLOLAKE_LP
> Can we have a consistent naming scheme:
good catch, we have addressed this in next patch. can you please check, if anything left unattended
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Gerrit-MessageType: comment
Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd
Gerrit-PatchSet: 5
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19569 )
Change subject: common/block/cse: Use CSE PCH ID from device/pci_ids.h
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Patch Set 1:
(1 comment)
https://review.coreboot.org/#/c/19569/1/src/soc/intel/common/block/cse/cse.c
File src/soc/intel/common/block/cse/cse.c:
Line 474: .device = PCI_DEVICE_ID_INTEL_APOLLOLAKE_CSE0
> You might as well put this into a device_ids list so that we can append. Un
yes Aaron, i would like to wait, i could see lots of assumption here, for an example CSE BAR address can't be common for all soc. we will address CSE common code and push SKL use patch right after I2C. That time, we will take care.
/* default window for early boot, must be at least 12 bytes in size */
#define HECI1_BASE_ADDRESS 0xfed1a000
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Gerrit-Change-Id: Ic92d17b2819c39997bbffff8293c937f3f73776b
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