coreboot-gerrit May 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: pci_device: add PCI device IDs for Intel platforms
by Subrata Banik (Code Review) 05 May '17

05 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19541 ) Change subject: pci_device: add PCI device IDs for Intel platforms ...................................................................... Patch Set 3: (2 comments) https://review.coreboot.org/#/c/19541/3/src/include/device/pci_ids.h File src/include/device/pci_ids.h: PS3, Line 2762: #define PCI_DEVICE_ID_INTEL_APOLLOLAKE_HECI1 0x5a9a > i was thinking to modify common cse code to use HECI1 rather using duplicat Done PS3, Line 2762: #define PCI_DEVICE_ID_INTEL_APOLLOLAKE_HECI1 0x5a9a > More concretely, I don't see anyone using CSE0 macro aside from another mac i'm doing that, will push a patch in min. -- To view, visit https://review.coreboot.org/19541 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Remove unused skylake_i2c_config structure
by Furquan Shaikh (Code Review) 05 May '17

05 May '17

Furquan Shaikh has submitted this change and it was merged. ( https://review.coreboot.org/19520 ) Change subject: soc/intel/skylake: Remove unused skylake_i2c_config structure ...................................................................... soc/intel/skylake: Remove unused skylake_i2c_config structure Remove struct skylake_i2c_config from chip.h since it is not used anymore. Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae Signed-off-by: Furquan Shaikh <furquan(a)chromium.org> Reviewed-on: https://review.coreboot.org/19520 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net> Reviewed-by: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> --- M src/soc/intel/skylake/chip.h 1 file changed, 0 insertions(+), 9 deletions(-) Approvals: Aaron Durbin: Looks good to me, approved Sumeet R Pawnikar: Looks good to me, approved Paul Menzel: Looks good to me, but someone else must approve build bot (Jenkins): Verified diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index cd461d4..b474ca2 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -40,15 +40,6 @@ I2C_VOLTAGE_1V8 }; -struct skylake_i2c_config { - /* Bus speed in Hz, default is I2C_SPEED_FAST (400 KHz) */ - enum i2c_speed speed; - /* Bus should be enabled prior to ramstage with temporary base */ - int early_init; - /* Custom bus speed configuration { scl_lcnt, scl_hcnt, sda_hold } */ - struct lpss_i2c_speed_config speed_config[LPSS_I2C_SPEED_CONFIG_COUNT]; -}; - struct soc_intel_skylake_config { /* * Interrupt Routing configuration -- To view, visit https://review.coreboot.org/19520 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: merged Gerrit-Change-Id: Icde4b7af5b9c31020099c1a6372a6867827f61ae Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR
by Patrick Rudolph (Code Review) 05 May '17

05 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/19543 ) Change subject: sb/intel/bd82x6x/finalize: Lock ETR3 CF9GR ...................................................................... Patch Set 1: It's already done on some boards in pch_enable_lpc(). I'll clean the mainboards dir in a seperate commit, as it's to early to lock the reset function in early romstage. -- To view, visit https://review.coreboot.org/19543 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2cb30267a6342db1f3b11715034219ffb18ca678 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: util/intelmetool: Add bootguard information dump support
by Patrick Rudolph (Code Review) 05 May '17

05 May '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/16328 ) Change subject: util/intelmetool: Add bootguard information dump support ...................................................................... Patch Set 19: (3 comments) https://review.coreboot.org/#/c/16328/19/util/intelmetool/intelmetool.c File util/intelmetool/intelmetool.c: Line 458: default: you are changing default behaviour. You need to mention it in the commit message. https://review.coreboot.org/#/c/16328/19/util/intelmetool/msr.c File util/intelmetool/msr.c: Line 50: } else { remove else { } but keep perror(... Line 56: return msr; unreachable -- To view, visit https://review.coreboot.org/16328 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ifeec8e20fa8efc35d7db4c6a84be1f118dccfc4a Gerrit-PatchSet: 19 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Damien Zammit <damien(a)zamaudio.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Mathias Krause <minipli(a)googlemail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: pci_device: add PCI device IDs for Intel platforms
by Subrata Banik (Code Review) 05 May '17

05 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19541 ) Change subject: pci_device: add PCI device IDs for Intel platforms ...................................................................... Patch Set 3: (1 comment) https://review.coreboot.org/#/c/19541/3/src/include/device/pci_ids.h File src/include/device/pci_ids.h: PS3, Line 2762: #define PCI_DEVICE_ID_INTEL_APOLLOLAKE_HECI1 0x5a9a i was thinking to modify common cse code to use HECI1 rather using duplicate macro -- To view, visit https://review.coreboot.org/19541 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0eee9409df3e6dc326b60bc82c2b715c70e7debd Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: google/fizz: Configure SATAXPCIe GPIOs to use native function
by build bot (Jenkins) (Code Review) 05 May '17

05 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19554 ) Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53210/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/9032/ : SUCCESS -- To view, visit https://review.coreboot.org/19554 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Enable SATA ports
by build bot (Jenkins) (Code Review) 05 May '17

05 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19553 ) Change subject: soc/intel/skylake: Enable SATA ports ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53209/ : SUCCESS -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: google/fizz: Configure SATAXPCIe GPIOs to use native function
by Shelley Chen (Code Review) 05 May '17

05 May '17

Hello Aaron Durbin, Paul Menzel, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19554 to look at the new patch set (#4). Change subject: google/fizz: Configure SATAXPCIe GPIOs to use native function ...................................................................... google/fizz: Configure SATAXPCIe GPIOs to use native function BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that device detects SSD Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/gpio.h 1 file changed, 4 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/19554/4 -- To view, visit https://review.coreboot.org/19554 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I4a85b9f3ba1d0a4c0a753420e166d3353417a1d1 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel/skylake: Enable SATA ports
by Shelley Chen (Code Review) 05 May '17

05 May '17

Hello Paul Menzel, build bot (Jenkins), Furquan Shaikh, I'd like you to reexamine a change. Please visit https://review.coreboot.org/19553 to look at the new patch set (#4). Change subject: soc/intel/skylake: Enable SATA ports ...................................................................... soc/intel/skylake: Enable SATA ports The current implementation is incorrect and is actually disabling the ports. Fixes that. BUG=b:37486021, b:35775024 BRANCH=None TEST=reboot and ensure that we can boot from SATA SSD. Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/soc/intel/skylake/sata.c 1 file changed, 6 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/19553/4 -- To view, visit https://review.coreboot.org/19553 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I8525f6f5ddfdf61c564febd86b1ba2e01c22d9e5 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: sb/intel/*: Use common SMBus functions
by build bot (Jenkins) (Code Review) 05 May '17

05 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19258 ) Change subject: sb/intel/*: Use common SMBus functions ...................................................................... Patch Set 10: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/53208/ : SUCCESS -- To view, visit https://review.coreboot.org/19258 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962 Gerrit-PatchSet: 10 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017