Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/19546 )
Change subject: sb/intel/bd82x6x/bootblock: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/19545 )
Change subject: sb/intel/bd82x6x/finalize: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19521 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket
......................................................................
Patch Set 7:
If you revert this commit in your seabios sources everything works fine. I going to investigate it later today
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/19544 )
Change subject: nb/intel/sandybridge/romstage: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Sumeet R Pawnikar has posted comments on this change. ( https://review.coreboot.org/19547 )
Change subject: nb/intel/sandybridge/early_init: Use register name
......................................................................
Patch Set 1: Code-Review+2
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Philipp Deppenwiese has posted comments on this change. ( https://review.coreboot.org/19521 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket
......................................................................
Patch Set 7:
Yes because there is another bug in coreboot or seabios interoperability and SeaBIOS thinks something goes wrong and executes the behaviour introduced with 7fce1d9661b29e3dab05b862e95c6cd35d822536
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Bill XIE has posted comments on this change. ( https://review.coreboot.org/19521 )
Change subject: mb/gigabyte/ga-b75m-d3h: Add tpm support for its onboard tpm socket
......................................................................
Patch Set 7:
(1 comment)
https://review.coreboot.org/#/c/19521/5/src/mainboard/gigabyte/ga-b75m-d3h/…
File src/mainboard/gigabyte/ga-b75m-d3h/Kconfig:
Line 21: select MAINBOARD_HAS_LPC_TPM
> add select TPM because we have two implementation using the same driver tpm
Below is a SeaBIOS log about TCGBIOS fetched from my Thinkpad x230 after apply Change 19535:
TCGBIOS: Detected a TPM 1.2.
TCGBIOS: Starting with TPM_Startup(ST_CLEAR)
Return from build_and_send_cmd(99, 0 1) = 26
Return from build_and_send_cmd(4000000a, 0 8) = 0
TCGBIOS: Return code from TPM_GetCapability(5, 277) = 0
TCGBIOS: Return code from TPM_GetCapability(5, 288) = 0
TCGBIOS: timeouts: 750000 750000 750000 750000
TCGBIOS: durations: 6000000 6000000 180000000
Return from build_and_send_cmd(50, 0 0) = 0
WARNING - Timeout at tis_wait_sts:160!
Return from build_and_send_cmd(4000000b, 0 0) = ffffffff
TCGBIOS: TPM malfunctioning (line 864).
WARNING - Timeout at tis_wait_sts:160!
There will be no 't' menu item within SeaBIOS' menu, and then TPM becomes deactivated in the OS. If there is no SeaBIOS in the bootloader payload chain, TPM would not get deactivated, but it seems SeaBIOS is needed to revived a cleared TPM. Note that on sandybridge platforms like t420 and x220, SeaBIOS works fine.
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Hello Patrick Rudolph, Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19258
to look at the new patch set (#10).
Change subject: sb/intel/*: Use common SMBus functions
......................................................................
sb/intel/*: Use common SMBus functions
All Intel southbridges implement the same SMBus functions.
This patch replaces all these similar and mostly identical
implementations with a common file.
This also makes i2c block read available to all those southbridges.
If the northbridge has to read a lot of SPD bytes sequentially, using
this function can reduce the time being spent to read SPD five-fold.
Change-Id: I93bb186e04e8c32dff04fc1abe4b5ecbc4c9c962
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/northbridge/intel/sandybridge/raminit.c
M src/southbridge/intel/bd82x6x/Kconfig
M src/southbridge/intel/bd82x6x/early_smbus.c
M src/southbridge/intel/bd82x6x/smbus.c
D src/southbridge/intel/bd82x6x/smbus.h
M src/southbridge/intel/common/Kconfig
M src/southbridge/intel/common/Makefile.inc
R src/southbridge/intel/common/smbus.c
A src/southbridge/intel/common/smbus.h
M src/southbridge/intel/fsp_bd82x6x/Kconfig
M src/southbridge/intel/fsp_i89xx/Kconfig
M src/southbridge/intel/fsp_i89xx/early_smbus.c
D src/southbridge/intel/fsp_i89xx/smbus.h
M src/southbridge/intel/fsp_rangeley/Kconfig
M src/southbridge/intel/fsp_rangeley/early_smbus.c
M src/southbridge/intel/fsp_rangeley/smbus.c
D src/southbridge/intel/fsp_rangeley/smbus.h
M src/southbridge/intel/i3100/Kconfig
M src/southbridge/intel/i3100/early_smbus.c
M src/southbridge/intel/i3100/smbus.c
D src/southbridge/intel/i3100/smbus.h
M src/southbridge/intel/i82371eb/Kconfig
M src/southbridge/intel/i82371eb/early_smbus.c
M src/southbridge/intel/i82371eb/smbus.c
D src/southbridge/intel/i82371eb/smbus.h
M src/southbridge/intel/i82801ax/Kconfig
M src/southbridge/intel/i82801ax/early_smbus.c
M src/southbridge/intel/i82801ax/smbus.c
D src/southbridge/intel/i82801ax/smbus.h
M src/southbridge/intel/i82801bx/Kconfig
M src/southbridge/intel/i82801bx/early_smbus.c
M src/southbridge/intel/i82801bx/smbus.c
D src/southbridge/intel/i82801bx/smbus.h
M src/southbridge/intel/i82801ex/Kconfig
M src/southbridge/intel/i82801ex/early_smbus.c
M src/southbridge/intel/i82801ex/smbus.c
D src/southbridge/intel/i82801ex/smbus.h
M src/southbridge/intel/i82801gx/Kconfig
M src/southbridge/intel/i82801gx/early_smbus.c
M src/southbridge/intel/i82801gx/smbus.c
D src/southbridge/intel/i82801gx/smbus.h
M src/southbridge/intel/i82801ix/Kconfig
M src/southbridge/intel/i82801ix/early_smbus.c
M src/southbridge/intel/i82801ix/smbus.c
D src/southbridge/intel/i82801ix/smbus.h
M src/southbridge/intel/ibexpeak/Kconfig
M src/southbridge/intel/ibexpeak/early_smbus.c
M src/southbridge/intel/ibexpeak/smbus.c
M src/southbridge/intel/lynxpoint/Kconfig
M src/southbridge/intel/lynxpoint/early_smbus.c
M src/southbridge/intel/lynxpoint/smbus.c
D src/southbridge/intel/lynxpoint/smbus.h
52 files changed, 183 insertions(+), 1,512 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19258/10
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