Hello Kyösti Mälkki, Philippe Mathieu-Daudé, Paul Menzel, build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19386
to look at the new patch set (#4).
Change subject: drivers/spi: Re-factor spi_crop_chunk
......................................................................
drivers/spi: Re-factor spi_crop_chunk
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi-generic.c
M src/drivers/spi/spiconsole.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/include/spi-generic.h
M src/soc/broadcom/cygnus/spi.c
M src/soc/imgtec/pistachio/spi.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/spi.c
M src/soc/marvell/armada38x/spi.c
M src/soc/marvell/bg4cd/spi.c
M src/soc/mediatek/mt8173/flash_controller.c
M src/soc/mediatek/mt8173/spi.c
M src/soc/nvidia/tegra124/spi.c
M src/soc/nvidia/tegra210/spi.c
M src/soc/qualcomm/ipq40xx/spi.c
M src/soc/qualcomm/ipq806x/spi.c
M src/soc/rockchip/common/spi.c
M src/soc/samsung/exynos5420/spi.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/sb700/spi.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/fsp_rangeley/spi.c
37 files changed, 92 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19386/4
--
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Gerrit-PatchSet: 4
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>
Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/19575 )
Change subject: soc/intel/common: Provide common block fast_spi_flash_ctrlr
......................................................................
soc/intel/common: Provide common block fast_spi_flash_ctrlr
Now that we have a common block driver for fast spi flash controller,
provide spi_ctrlr structure that can be used by different platforms
for defining the bus-ctrlr mapping. Currently, the ctrlr structure is
empty, but with follow-on changes, new members will be added to this
structure as required.
BUG=None
Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/soc/intel/apollolake/spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
M src/soc/intel/common/block/include/intelblocks/fast_spi.h
M src/soc/intel/skylake/spi.c
4 files changed, 13 insertions(+), 36 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/19575/2
--
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I7228ae885018d1e23e6e80dd8ce227b0d99d84a6
Gerrit-PatchSet: 2
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Hello Kyösti Mälkki, Philippe Mathieu-Daudé, Paul Menzel, build bot (Jenkins), coreboot org,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/19386
to look at the new patch set (#3).
Change subject: drivers/spi: Re-factor spi_crop_chunk
......................................................................
drivers/spi: Re-factor spi_crop_chunk
spi_crop_chunk is a property of the SPI controller since it depends
upon the maximum transfer size that is supported by the
controller. Also, it is possible to implement this within spi-generic
layer by obtaining following parameters from the controller:
1. max_xfer_size: Maximum transfer size supported by the controller
(Size of 0 indicates invalid size, and unlimited transfer size is
indicated by UINT32_MAX.)
2. deduct_cmd_len: Whether cmd_len needs to be deducted from the
max_xfer_size to determine max data size that can be
transferred. (This is used by the amd boards.)
Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
M src/drivers/spi/adesto.c
M src/drivers/spi/amic.c
M src/drivers/spi/atmel.c
M src/drivers/spi/eon.c
M src/drivers/spi/gigadevice.c
M src/drivers/spi/macronix.c
M src/drivers/spi/spansion.c
M src/drivers/spi/spi-generic.c
M src/drivers/spi/spiconsole.c
M src/drivers/spi/sst.c
M src/drivers/spi/stmicro.c
M src/drivers/spi/winbond.c
M src/include/spi-generic.h
M src/soc/broadcom/cygnus/spi.c
M src/soc/imgtec/pistachio/spi.c
M src/soc/intel/baytrail/spi.c
M src/soc/intel/braswell/spi.c
M src/soc/intel/broadwell/spi.c
M src/soc/intel/common/block/fast_spi/fast_spi_flash.c
M src/soc/intel/common/block/gspi/gspi.c
M src/soc/intel/fsp_baytrail/spi.c
M src/soc/intel/fsp_broadwell_de/spi.c
M src/soc/marvell/armada38x/spi.c
M src/soc/marvell/bg4cd/spi.c
M src/soc/mediatek/mt8173/flash_controller.c
M src/soc/mediatek/mt8173/spi.c
M src/soc/nvidia/tegra124/spi.c
M src/soc/nvidia/tegra210/spi.c
M src/soc/qualcomm/ipq40xx/spi.c
M src/soc/qualcomm/ipq806x/spi.c
M src/soc/rockchip/common/spi.c
M src/soc/samsung/exynos5420/spi.c
M src/southbridge/amd/agesa/hudson/spi.c
M src/southbridge/amd/cimx/sb800/spi.c
M src/southbridge/amd/sb700/spi.c
M src/southbridge/intel/common/spi.c
M src/southbridge/intel/fsp_rangeley/spi.c
37 files changed, 92 insertions(+), 119 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/19386/3
--
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To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I81c199413f879c664682088e93bfa3f91c6a46e5
Gerrit-PatchSet: 3
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com>
Hello Kyösti Mälkki, Aaron Durbin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18433
to look at the new patch set (#20).
Change subject: amd/pi/00670F00: Change to early cbmem init
......................................................................
amd/pi/00670F00: Change to early cbmem init
Add cbmem initialization to romstage and force Stoney to early by
selecting the Kconfig option. Add cbmem_top() function to memmap.c.
Remove the LATE_CBMEM_INIT-only set_top_of_ram().
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 4c1b4615516dfbd46a768968c2be017cdeb51ee4)
Change-Id: Id1c22a15752a07eebf39530ba8549ef1f74265ec
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
M src/cpu/amd/pi/00670F00/romstage.c
M src/northbridge/amd/pi/00670F00/Kconfig
M src/northbridge/amd/pi/00670F00/memmap.c
M src/northbridge/amd/pi/00670F00/northbridge.c
4 files changed, 19 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/18433/20
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: Id1c22a15752a07eebf39530ba8549ef1f74265ec
Gerrit-PatchSet: 20
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de>
Gerrit-Reviewer: Patrick Georgi <pgeorgi(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Ronald Minnich <rminnich(a)google.com>
Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Kyösti Mälkki, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18428
to look at the new patch set (#19).
Change subject: amd/pi/00670F00: Add memmap file
......................................................................
amd/pi/00670F00: Add memmap file
In preparation for supporting EARLY_CBMEM_INIT, move the UMA
base and size calculation code into a new memmap.c file.
Original-Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Original-Reviewed-by: Marc Jones <marcj303(a)gmail.com>
(cherry picked from commit 4fec9f6754675bbe0c8fbfc031c5c5665dace34b)
Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
M src/northbridge/amd/pi/00670F00/Makefile.inc
A src/northbridge/amd/pi/00670F00/memmap.c
A src/northbridge/amd/pi/00670F00/memmap.h
M src/northbridge/amd/pi/00670F00/northbridge.c
4 files changed, 102 insertions(+), 38 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/18428/19
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I8ddaa8359536081752fb8e47e49f4d5958416620
Gerrit-PatchSet: 19
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Kyösti Mälkki, Aaron Durbin, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18495
to look at the new patch set (#17).
Change subject: amd/pi/00670F00: Add generic romstage
......................................................................
amd/pi/00670F00: Add generic romstage
Move the generic romstage code to the Stoney Ridge cpu.
Change-Id: If66ac0e4b3c088f138b9282546ed1ec2d861dd74
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
---
M src/cpu/amd/pi/00670F00/Makefile.inc
A src/cpu/amd/pi/00670F00/romstage.c
A src/cpu/amd/pi/00670F00/romstage.h
M src/mainboard/amd/gardenia/romstage.c
4 files changed, 91 insertions(+), 34 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/18495/17
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If66ac0e4b3c088f138b9282546ed1ec2d861dd74
Gerrit-PatchSet: 17
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Hello Kyösti Mälkki, Aaron Durbin, build bot (Jenkins), Martin Roth,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/18492
to look at the new patch set (#16).
Change subject: vendorcode/amd/pi/00670F00: Clarify CAR disable
......................................................................
vendorcode/amd/pi/00670F00: Clarify CAR disable
Clean up the AMD_DISABLE_STACK_FAMILY_HOOK_F15 to be clear that
it does a wbinvd to preserve the coreboot stack and CAR globals.
The Stoney Ridge uses a different S3 architecture, so this is not
an issue of reserving or relocating the stack on a resume. Remove
the Gardenia cache_disable TODO comment as this clarifies how it
works for Stoney.
Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328
Signed-off-by: Marc Jones <marcj303(a)gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
---
M src/cpu/amd/pi/cache_as_ram.inc
M src/mainboard/amd/bettong/romstage.c
M src/mainboard/amd/db-ft3b-lc/romstage.c
M src/mainboard/amd/gardenia/romstage.c
M src/mainboard/amd/lamar/romstage.c
M src/mainboard/amd/olivehillplus/romstage.c
M src/mainboard/bap/ode_e21XX/romstage.c
M src/mainboard/pcengines/apu2/romstage.c
M src/vendorcode/amd/pi/00630F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00660F01/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00670F00/binaryPI/gcccar.inc
M src/vendorcode/amd/pi/00730F01/binaryPI/gcccar.inc
12 files changed, 116 insertions(+), 39 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/18492/16
--
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Gerrit-MessageType: newpatchset
Gerrit-Change-Id: I77e53262212e00bce9145b0bc3909ad8651f2328
Gerrit-PatchSet: 16
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-Owner: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org>
Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com>
Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Gerrit-Reviewer: Martin Roth <martinroth(a)google.com>
Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net>
Gerrit-Reviewer: Zheng Bao <fishbaozi(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>