coreboot-gerrit May 2017

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Change in coreboot[master]: google/slippy: populate PEI SPD data for all channels
by Matt DeVillier (Code Review) 30 May '17

30 May '17

Matt DeVillier has uploaded a new change for review. ( https://review.coreboot.org/19981 ) Change subject: google/slippy: populate PEI SPD data for all channels ...................................................................... google/slippy: populate PEI SPD data for all channels Since dual-channel setups use same RAM/SPD for both channels, populate spd_data[1] with same SPD data as spd_data[0], allowing info for both channels to propogate into the SBMIOS tables. Clean up calculations using SPD length to avoid repetition. Changes modeled after google/auron variants. Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/mainboard/google/slippy/variants/falco/romstage.c M src/mainboard/google/slippy/variants/leon/romstage.c M src/mainboard/google/slippy/variants/peppy/romstage.c M src/mainboard/google/slippy/variants/wolf/romstage.c 4 files changed, 49 insertions(+), 44 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/19981/1 diff --git a/src/mainboard/google/slippy/variants/falco/romstage.c b/src/mainboard/google/slippy/variants/falco/romstage.c index 8254bc2..81174db 100644 --- a/src/mainboard/google/slippy/variants/falco/romstage.c +++ b/src/mainboard/google/slippy/variants/falco/romstage.c @@ -74,6 +74,7 @@ int spd_index = get_gpios(gpio_vector); char *spd_file; size_t spd_file_len; + size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -81,27 +82,27 @@ if (!spd_file) die("SPD data not found."); - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + if (spd_file_len < ((spd_index + 1) * spd_len)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file_len < sizeof(peid->spd_data[0])) + if (spd_file_len < spd_len) die("Missing SPD data."); + + memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); /* Index 0-2,6 are 4GB config with both CH0 and CH1 * Index 3-5,7 are 2GB config with CH0 only */ switch (spd_index) { + case 0: case 1: case 2: case 6: + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); + break; case 3: case 4: case 5: case 7: peid->dimm_channel1_disabled = 3; } - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); } void variant_romstage_entry(unsigned long bist) diff --git a/src/mainboard/google/slippy/variants/leon/romstage.c b/src/mainboard/google/slippy/variants/leon/romstage.c index c9cf07b..132f586 100644 --- a/src/mainboard/google/slippy/variants/leon/romstage.c +++ b/src/mainboard/google/slippy/variants/leon/romstage.c @@ -74,6 +74,7 @@ int spd_index = get_gpios(gpio_vector); char *spd_file; size_t spd_file_len; + size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -81,25 +82,24 @@ if (!spd_file) die("SPD data not found."); + if (spd_file_len < ((spd_index + 1) * spd_len)) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < spd_len) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + /* Limiting to a single dimm for 2GB configuration * Identified by bit 3 */ if (spd_index & 0x4) peid->dimm_channel1_disabled = 3; - - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < sizeof(peid->spd_data[0])) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); + else + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); } void variant_romstage_entry(unsigned long bist) diff --git a/src/mainboard/google/slippy/variants/peppy/romstage.c b/src/mainboard/google/slippy/variants/peppy/romstage.c index 4a39101..bf21cbc 100644 --- a/src/mainboard/google/slippy/variants/peppy/romstage.c +++ b/src/mainboard/google/slippy/variants/peppy/romstage.c @@ -77,6 +77,7 @@ int spd_index = get_gpios(gpio_vector); char *spd_file; size_t spd_file_len; + size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -84,11 +85,24 @@ if (!spd_file) die("SPD data not found."); + if (spd_file_len < ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); + spd_index = 0; + } + + if (spd_file_len < spd_len) + die("Missing SPD data."); + + memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); + switch (google_chromeec_get_board_version()) { case PEPPY_BOARD_VERSION_PROTO: /* Index 0 is 2GB config with CH0 only. */ if (spd_index == 0) peid->dimm_channel1_disabled = 3; + else + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); break; case PEPPY_BOARD_VERSION_EVT: @@ -97,22 +111,11 @@ * Index 4-6 are 2GB config with CH0 only. */ if (spd_index > 3) peid->dimm_channel1_disabled = 3; + else + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); break; } - - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { - printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); - spd_index = 0; - } - - if (spd_file_len < sizeof(peid->spd_data[0])) - die("Missing SPD data."); - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); } void variant_romstage_entry(unsigned long bist) diff --git a/src/mainboard/google/slippy/variants/wolf/romstage.c b/src/mainboard/google/slippy/variants/wolf/romstage.c index 4bdde31..5b6b254 100644 --- a/src/mainboard/google/slippy/variants/wolf/romstage.c +++ b/src/mainboard/google/slippy/variants/wolf/romstage.c @@ -76,6 +76,7 @@ int spd_index = get_gpios(gpio_vector); char *spd_file; size_t spd_file_len; + size_t spd_len = sizeof(peid->spd_data[0]); printk(BIOS_DEBUG, "SPD index %d\n", spd_index); spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, @@ -83,27 +84,27 @@ if (!spd_file) die("SPD data not found."); - if (spd_file_len < - ((spd_index + 1) * sizeof(peid->spd_data[0]))) { + if (spd_file_len < ((spd_index + 1) * spd_len)) { printk(BIOS_ERR, "SPD index override to 0 - old hardware?\n"); spd_index = 0; } - if (spd_file_len < sizeof(peid->spd_data[0])) + if (spd_file_len < spd_len) die("Missing SPD data."); + + memcpy(peid->spd_data[0], spd_file + (spd_index * spd_len), spd_len); /* Index 0-2, are 4GB config with both CH0 and CH1 * Index 3-5, are 2GB config with CH0 only */ switch (spd_index) { + case 0: case 1: case 2: + memcpy(peid->spd_data[1], + spd_file + (spd_index * spd_len), spd_len); + break; case 3: case 4: case 5: peid->dimm_channel1_disabled = 3; } - - memcpy(peid->spd_data[0], - spd_file + - spd_index * sizeof(peid->spd_data[0]), - sizeof(peid->spd_data[0])); } void variant_romstage_entry(unsigned long bist) -- To view, visit https://review.coreboot.org/19981 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10257/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54540/ : SUCCESS -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Matt DeVillier (Code Review) 30 May '17

30 May '17

Matt DeVillier has posted comments on this change. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/19960/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_mrc.c: PS1, Line 308: 0x5e04 > MC_BIOS_DATA in northbridge/intel/sandybridge/raminit_common.h? these 3 MCHBAR values (5000,5004,5008) are used for getting DRAM info for SNB thru SKL and repeated each time. I agree defining them once would be ideal but not sure where PS1, Line 310: addr_decode_ch > This looks like channels, but we can have two dimms per channel, so should added DIMM-B PS1, Line 325: 122 > Hrm - looks like we need an spd_ddr3.h file. agreed, where to put it? PS1, Line 328: same for all modules so use first > what if not all modules are populated? addressed in patch 2 -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Matt DeVillier (Code Review) 30 May '17

30 May '17

Hello Philippe Mathieu-Daudé, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19960 to look at the new patch set (#2). Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... nb/sandybridge:add CBMEM_MEMINFO table when initing RAM Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older SandyBridge MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/northbridge/intel/sandybridge/raminit.h M src/northbridge/intel/sandybridge/raminit_mrc.c 2 files changed, 77 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/19960/2 -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM
by Martin Roth (Code Review) 29 May '17

29 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19960 ) Change subject: nb/sandybridge:add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/19960/1/src/northbridge/intel/sandybridge/r… File src/northbridge/intel/sandybridge/raminit_mrc.c: PS1, Line 308: 0x5e04 MC_BIOS_DATA in northbridge/intel/sandybridge/raminit_common.h? I guess none of the other MCHBAR values are defined anywhere, so maybe that doesn't make sense. PS1, Line 310: addr_decode_ch This looks like channels, but we can have two dimms per channel, so should this be multiplied by 2, or should we have a j loop? PS1, Line 325: 122 Hrm - looks like we need an spd_ddr3.h file. PS1, Line 328: same for all modules so use first what if not all modules are populated? -- To view, visit https://review.coreboot.org/19960 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I13d784a17eda01ccc9569c4562bba6d14af5157d Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/baytrail: add ACPI method to generate USB port info
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19973 ) Change subject: soc/baytrail: add ACPI method to generate USB port info ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10256/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54539/ : SUCCESS -- To view, visit https://review.coreboot.org/19973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/broadwell: add missing USB port defs
by build bot (Jenkins) (Code Review) 29 May '17

29 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19968 ) Change subject: soc/broadwell: add missing USB port defs ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10255/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54538/ : SUCCESS -- To view, visit https://review.coreboot.org/19968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: nb/intel/sandybridge: Remove unecessary reserved resources
by Matt DeVillier (Code Review) 29 May '17

29 May '17

Matt DeVillier has abandoned this change. ( https://review.coreboot.org/19977 ) Change subject: nb/intel/sandybridge: Remove unecessary reserved resources ...................................................................... Abandoned will rework guarding ACPI regions in new patch -- To view, visit https://review.coreboot.org/19977 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: abandon Gerrit-Change-Id: I9e14a73dbdb9d62dfd7d942a79659a5997f97971 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/broadwell: add missing USB port defs
by Martin Roth (Code Review) 29 May '17

29 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19968 ) Change subject: soc/broadwell: add missing USB port defs ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19968 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ice86bd226a70bd5996430e7a68a026cc825ba187 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/baytrail: add ACPI method to generate USB port info
by Martin Roth (Code Review) 29 May '17

29 May '17

Martin Roth has posted comments on this change. ( https://review.coreboot.org/19973 ) Change subject: soc/baytrail: add ACPI method to generate USB port info ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/19973 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iad947ae2cd541d3407455b218c2b352b9a373718 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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