coreboot-gerrit May 2017

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Change in coreboot[master]: mc_tcu3: Remove all hwinfo files from mainboard directory
by Werner Zeh (Code Review) 30 May '17

30 May '17

Werner Zeh has uploaded a new change for review. ( https://review.coreboot.org/19982 ) Change subject: mc_tcu3: Remove all hwinfo files from mainboard directory ...................................................................... mc_tcu3: Remove all hwinfo files from mainboard directory To unify the hwinfo handling along all Siemens MC boards the hwinfo files have to be removed from the mainboard directory. They will be added to cbfs in site-local/Makefile.inc. Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef Signed-off-by: Werner Zeh <werner.zeh(a)siemens.com> --- M src/mainboard/siemens/mc_tcu3/Makefile.inc D src/mainboard/siemens/mc_tcu3/hwinfo.hex D src/mainboard/siemens/mc_tcu3/hwinfo10.hex D src/mainboard/siemens/mc_tcu3/hwinfo12.hex D src/mainboard/siemens/mc_tcu3/hwinfo15.hex D src/mainboard/siemens/mc_tcu3/hwinfo19.hex 6 files changed, 0 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/19982/1 diff --git a/src/mainboard/siemens/mc_tcu3/Makefile.inc b/src/mainboard/siemens/mc_tcu3/Makefile.inc index 2922eef..edcb85e 100644 --- a/src/mainboard/siemens/mc_tcu3/Makefile.inc +++ b/src/mainboard/siemens/mc_tcu3/Makefile.inc @@ -17,24 +17,3 @@ ramstage-y += irqroute.c ramstage-y += lcd_panel.c ramstage-y += ptn3460.c - -cbfs-files-y += hwinfo.hex -hwinfo.hex-file := hwinfo.hex -hwinfo.hex-type := raw -hwinfo.hex-align := 0x1000 - -cbfs-files-y += hwinfo10.hex -hwinfo10.hex-file := hwinfo10.hex -hwinfo10.hex-type := raw - -cbfs-files-y += hwinfo12.hex -hwinfo12.hex-file := hwinfo12.hex -hwinfo12.hex-type := raw - -cbfs-files-y += hwinfo15.hex -hwinfo15.hex-file := hwinfo15.hex -hwinfo15.hex-type := raw - -cbfs-files-y += hwinfo19.hex -hwinfo19.hex-file := hwinfo19.hex -hwinfo19.hex-type := raw diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo.hex b/src/mainboard/siemens/mc_tcu3/hwinfo.hex deleted file mode 100644 index bbf6783..0000000 --- a/src/mainboard/siemens/mc_tcu3/hwinfo.hex +++ /dev/null Binary files differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo10.hex b/src/mainboard/siemens/mc_tcu3/hwinfo10.hex deleted file mode 100644 index 390c6b4..0000000 --- a/src/mainboard/siemens/mc_tcu3/hwinfo10.hex +++ /dev/null Binary files differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo12.hex b/src/mainboard/siemens/mc_tcu3/hwinfo12.hex deleted file mode 100644 index 471af4f..0000000 --- a/src/mainboard/siemens/mc_tcu3/hwinfo12.hex +++ /dev/null Binary files differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo15.hex b/src/mainboard/siemens/mc_tcu3/hwinfo15.hex deleted file mode 100644 index 4cbbe5b..0000000 --- a/src/mainboard/siemens/mc_tcu3/hwinfo15.hex +++ /dev/null Binary files differ diff --git a/src/mainboard/siemens/mc_tcu3/hwinfo19.hex b/src/mainboard/siemens/mc_tcu3/hwinfo19.hex deleted file mode 100644 index f8510fc..0000000 --- a/src/mainboard/siemens/mc_tcu3/hwinfo19.hex +++ /dev/null Binary files differ -- To view, visit https://review.coreboot.org/19982 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: Ia3dcb2e0118527b37aed872740273c4fa7004aef Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Werner Zeh <werner.zeh(a)siemens.com>

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Change in coreboot[master]: soc/intel/apollolake: Use CPU common code
by Subrata Banik (Code Review) 30 May '17

30 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19827 ) Change subject: soc/intel/apollolake: Use CPU common code ...................................................................... Patch Set 5: (2 comments) https://review.coreboot.org/#/c/19827/5/src/soc/intel/apollolake/chip.c File src/soc/intel/apollolake/chip.c: PS5, Line 28: #include <intelblocks/cpu.h> order https://review.coreboot.org/#/c/19827/5/src/soc/intel/apollolake/include/so… File src/soc/intel/apollolake/include/soc/iomap.h: PS5, Line 34: align? -- To view, visit https://review.coreboot.org/19827 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I529c67cf20253cf819d1c13849300788104b083c Gerrit-PatchSet: 5 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/skylake: Use CPU common code
by Subrata Banik (Code Review) 30 May '17

30 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19566 ) Change subject: soc/intel/skylake: Use CPU common code ...................................................................... Patch Set 9: (3 comments) https://review.coreboot.org/#/c/19566/9/src/soc/intel/skylake/bootblock/cpu… File src/soc/intel/skylake/bootblock/cpu.c: PS9, Line 19: #include <intelblocks/cpu.h> order PS9, Line 22: set_strap_msg_dat is this the function supposed to get called from common cpu code to soc, then name has to start with soc_ https://review.coreboot.org/#/c/19566/9/src/soc/intel/skylake/cpu.c File src/soc/intel/skylake/cpu.c: PS9, Line 30: #include <cpu/intel/microcode.h> need this? -- To view, visit https://review.coreboot.org/19566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6af56564c6f488f58173ba0beda6912763706f9f Gerrit-PatchSet: 9 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: soc/intel/common/block: Add Intel common CPU code
by Subrata Banik (Code Review) 30 May '17

30 May '17

Subrata Banik has posted comments on this change. ( https://review.coreboot.org/19540 ) Change subject: soc/intel/common/block: Add Intel common CPU code ...................................................................... Patch Set 11: (4 comments) https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/cpu/cpu… File src/soc/intel/common/block/cpu/cpu.c: PS11, Line 124: #if IS_ENABLED(CONFIG_HAVE_SMI_HANDLER) avoid #if use if (IS_ENABLED()) anyway you are having soft link https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/cpu/cpu… File src/soc/intel/common/block/cpu/cpu_early.c: PS11, Line 106: set_pch_cpu_strap(nominal_ratio); i guess this implementation differs between different socs.? PS11, Line 316: ADDRESS + PM1_TMR); > 80 https://review.coreboot.org/#/c/19540/11/src/soc/intel/common/block/include… File src/soc/intel/common/block/include/intelblocks/msr.h: PS11, Line 65: #define PRMRR_PHYS_BASE_MSR 0x1f4 don't keep this into common, it may be different between socs in future. -- To view, visit https://review.coreboot.org/19540 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f80c42132d9ea738be4051d2395e9e51ac153f8 Gerrit-PatchSet: 11 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Cole Nelson <colex.nelson(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GL...
by Shaunak Saha (Code Review) 30 May '17

30 May '17

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/19739 ) Change subject: [WIP]mainboard/intel/glkrvp: Add GPE routing settings for GLKRVP. ...................................................................... Patch Set 7: (1 comment) https://review.coreboot.org/#/c/19739/7/src/mainboard/intel/glkrvp/variants… File src/mainboard/intel/glkrvp/variants/baseboard/devicetree.cb: Line 77: #PMC_GPE_NW_31_0 - 02 > Are you specifying the bits within each register you are using? I don't und No. This is actually the numbers in GPE_CFG register representing GPIO community portID mapping. I will remove this comment and merge this pacth with glkrvp mainboard patch. -- To view, visit https://review.coreboot.org/19739 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I56a99bbb70ac9edda8448fabf05e3ea90d18d93c Gerrit-PatchSet: 7 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: [WIP]soc/intel/GLK: Fix GPE routing path
by Shaunak Saha (Code Review) 30 May '17

30 May '17

Shaunak Saha has posted comments on this change. ( https://review.coreboot.org/19697 ) Change subject: [WIP]soc/intel/GLK: Fix GPE routing path ...................................................................... Patch Set 13: I will incorporate all the changes and comments in one glkrvp patch that Hannah is working on. -- To view, visit https://review.coreboot.org/19697 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I484764ef4f6f815735cfc6615d10d87495d30186 Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block/gpio: Port gpio code from Apollolake ...
by Hannah Williams (Code Review) 30 May '17

30 May '17

Hannah Williams has posted comments on this change. ( https://review.coreboot.org/19759 ) Change subject: soc/intel/common/block/gpio: Port gpio code from Apollolake to common ...................................................................... Patch Set 15: (1 comment) https://review.coreboot.org/#/c/19759/15/src/soc/intel/common/block/gpio/gp… File src/soc/intel/common/block/gpio/gpio.c: Line 136: if (IS_ENABLED(CONFIG_DEBUG_SOC_COMMON_BLOCK_GPIO)) > we can't assume PAD configuration may be only 8 byte width, some future soc Today for SKL, KBL, APL and GLK we only have pad_conf0 and pad_conf1 - some bits are defined in one and not in the other where they are reserved - so it is not a issue to combine these. GLK has pad_conf 2 and 3 but we aren't using them. When we start using pad_conf_2 and pad_conf 3, we should be able to extend this base code using CONFIG flags -- To view, visit https://review.coreboot.org/19759 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Ic48401e92103ff0ec278fb69a3d304148a2d79aa Gerrit-PatchSet: 15 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Divya Chellappa <divya.chella(a)gmail.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: V Sowmya <v.sowmya(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: Yes

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19958 ) Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10259/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54542/ : SUCCESS -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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Change in coreboot[master]: haswell: add CBMEM_MEMINFO table when initing RAM
by Matt DeVillier (Code Review) 30 May '17

30 May '17

Hello Philippe Mathieu-Daudé, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19958 to look at the new patch set (#2). Change subject: haswell: add CBMEM_MEMINFO table when initing RAM ...................................................................... haswell: add CBMEM_MEMINFO table when initing RAM Populate a memory_info struct with PEI and SPD data, in order to inject the CBMEM_INFO table necessary to populate a type17 SMBIOS table. On Broadwell, this is done by the MRC binary, but the older Haswell MRC binary doesn't populate the pei_data struct with all the info needed, so we have to pull it from the SPD. Some values are hardcoded based on platform specifications. Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com> --- M src/cpu/intel/haswell/romstage.c M src/northbridge/intel/haswell/raminit.c M src/northbridge/intel/haswell/raminit.h 3 files changed, 78 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/19958/2 -- To view, visit https://review.coreboot.org/19958 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iea837d23f2c9c1c943e0db28cf81b265f054e9d1 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Philippe Mathieu-Daudé <philippe.mathieu.daude(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/slippy: populate PEI SPD data for all channels
by build bot (Jenkins) (Code Review) 30 May '17

30 May '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19981 ) Change subject: google/slippy: populate PEI SPD data for all channels ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/10258/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/54541/ : SUCCESS -- To view, visit https://review.coreboot.org/19981 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I7e14b35642a3fbaecaeb7d1d33b5a7c1405bac45 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-HasComments: No

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coreboot-gerrit May 2017