coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common System A...
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18567 ) Change subject: soc/intel/apollolake: Clean up code by using common System Agent module ...................................................................... Patch Set 23: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50855/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6831/ : SUCCESS -- To view, visit https://review.coreboot.org/18567 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Gerrit-PatchSet: 23 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18565 ) Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... Patch Set 18: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50853/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6830/ : SUCCESS -- To view, visit https://review.coreboot.org/18565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c Gerrit-PatchSet: 18 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Clean up code by using common System Agen...
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18566 ) Change subject: soc/intel/skylake: Clean up code by using common System Agent module ...................................................................... Patch Set 19: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50854/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6829/ : SUCCESS -- To view, visit https://review.coreboot.org/18566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Gerrit-PatchSet: 19 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18381 ) Change subject: soc/intel/common/block: Add cache as ram init and teardown code ...................................................................... Patch Set 38: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50852/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6828/ : SUCCESS -- To view, visit https://review.coreboot.org/18381 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Gerrit-PatchSet: 38 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/pci_devs.h: Use consistent naming in soc/pci_devs.h
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18576 ) Change subject: soc/pci_devs.h: Use consistent naming in soc/pci_devs.h ...................................................................... Patch Set 20: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50851/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6827/ : SUCCESS -- To view, visit https://review.coreboot.org/18576 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I5e4c7502e9678c0a367e9c7a96cf848d5b24f68e Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common CAR init
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18555 ) Change subject: soc/intel/apollolake: Clean up code by using common CAR init ...................................................................... Patch Set 25: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50850/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6826/ : SUCCESS -- To view, visit https://review.coreboot.org/18555 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Gerrit-PatchSet: 25 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] Move global variable declaration from header to romsta...
by Arthur Heymans (Code Review) 28 Mar '17

28 Mar '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19029 ) Change subject: [WIP] Move global variable declaration from header to romstage.c ...................................................................... [WIP] Move global variable declaration from header to romstage.c This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g1/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/f.h M src/northbridge/amd/amdk8/pre_f.h M src/northbridge/amd/amdk8/raminit_f.c 37 files changed, 136 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/19029/1 diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 26275b6..03b72f3 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -35,6 +35,10 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index bbbe869..95fddfe 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -35,6 +35,10 @@ #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + unsigned get_sbdn(unsigned bus); #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index 549ad0c..f341888 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -33,6 +33,10 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */ +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index ae89b05..cc0f0c5 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -32,6 +32,10 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index 3645c9f..a9fde30 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -36,6 +36,10 @@ #include <southbridge/amd/sb700/smbus.h> #include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627DHG_SP1) #define GPIO2345_DEV PNP_DEV(0x2e, W83627DHG_GPIO2345_V) diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 4965c4f..4478738 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -45,6 +45,11 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index b8f631b..46e2e77 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -43,6 +43,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 4c74d0f..408bc02 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -43,6 +43,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 0f98062..99dac5e 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -43,6 +43,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 03a095d..8ea2815 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -41,6 +41,10 @@ #include <superio/winbond/w83627thg/w83627thg.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset(int controllers, const struct mem_controller *ctrl) { } diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 91fded1..4820912 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -39,6 +39,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index daf0b50..e2ba679 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -42,6 +42,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index c61557b..00b07ff 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -42,6 +42,9 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) #define CLKIN_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 158e612..8ec62bd 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -18,6 +18,10 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 337423f..6f95abd 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -41,6 +41,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index da96ed7..cff283f 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -37,6 +37,9 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index 4ec6a87..acab760 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -21,6 +21,11 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index e7a3b2f..27fc82b 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -42,6 +42,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, PILOT_SP1) #define RTC_DEV PNP_DEV(0x4e, PC87417_RTC) diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 9fbc808..713401f 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -17,6 +17,10 @@ #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index d25799f..6ffa53a 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -37,6 +37,10 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + static void memreset(int controllers, const struct mem_controller *ctrl) { } static void activate_spd_rom(const struct mem_controller *ctrl) { } diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 620bc64..5c85d7b 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -42,6 +42,10 @@ #include "cpu/amd/dualcore/dualcore.c" #include <spd.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #if CONFIG_HAVE_OPTION_TABLE #include "option_table.h" #endif diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index d1c50df..c4cd330 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -39,6 +39,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x4e, W83627EHG_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index db52429..cec5e2e 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -40,6 +40,10 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, PC87417_SP1) #define RTC_DEV PNP_DEV(0x2e, PC87417_RTC) diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 463a767..054457c 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -40,6 +40,10 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <device/pci_ids.h> +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index ac070e9..2332f54 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -38,6 +38,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627EHG_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index a7f2c96..ae7c2fc 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -42,6 +42,10 @@ #include "southbridge/amd/sb600/early_setup.c" #include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, CONFIG_UART_FOR_CONSOLE == 1 ? IT8712F_SP2 : IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 397acfe..0a3e0c2 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -21,6 +21,10 @@ #include "superio/smsc/lpc47b397/early_gpio.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/pre_f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, LPC47B397_SP1) #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 6c3fdbd..756cd47 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -37,6 +37,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, DME1737_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index fdfb124..436efd7 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -35,6 +35,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 89cea08..9339fa4 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -38,6 +38,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) #define DUMMY_DEV PNP_DEV(0x2e, 0) diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index e534617..98b4100 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -35,6 +35,10 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index b1805a9..a1cc6d2 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -35,6 +35,10 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 02b4680..027de72 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -38,6 +38,10 @@ #include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1) unsigned get_sbdn(unsigned bus); diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index 3372f32..dd9e30e 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -21,6 +21,10 @@ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" +#include <northbridge/amd/amdk8/f.h> +#include <arch/early_variables.h> +struct sys_info sysinfo_car CAR_GLOBAL; + #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) static void memreset_setup(void) { } diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index 359a1d6..373eeee 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -518,11 +518,6 @@ uint32_t sbbusn; } __attribute__((packed)); -#ifdef __PRE_RAM__ -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; -#endif - #include <reset.h> #if ((CONFIG_MEM_TRAIN_SEQ != 1) && defined(__PRE_RAM__)) || \ diff --git a/src/northbridge/amd/amdk8/pre_f.h b/src/northbridge/amd/amdk8/pre_f.h index 9c1eeb6..6b32d6c 100644 --- a/src/northbridge/amd/amdk8/pre_f.h +++ b/src/northbridge/amd/amdk8/pre_f.h @@ -262,9 +262,4 @@ uint32_t sbbusn; } __attribute__((packed)); -#ifdef __PRE_RAM__ -#include <arch/early_variables.h> -struct sys_info sysinfo_car CAR_GLOBAL; -#endif - #endif /* AMDK8_PRE_F_H */ diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index aa2349d..abf2b3f 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -40,7 +40,6 @@ #include "f_pci.c" - /* for PCI_ADDR(0, 0x18, 2, 0x98) index, and PCI_ADDR(0x, 0x18, 2, 0x9c) data */ /* -- To view, visit https://review.coreboot.org/19029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/amd/amdk8/exit_from_self.c: Use linker instead of include
by Arthur Heymans (Code Review) 28 Mar '17

28 Mar '17

Hello Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19027 to look at the new patch set (#3). Change subject: nb/amd/amdk8/exit_from_self.c: Use linker instead of include ...................................................................... nb/amd/amdk8/exit_from_self.c: Use linker instead of include Don't #include *. but use linker. Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asus/m2v/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/exit_from_self.c M src/northbridge/amd/amdk8/f.h M src/northbridge/amd/amdk8/raminit.c M src/northbridge/amd/amdk8/raminit.h M src/northbridge/amd/amdk8/raminit_f.c M src/northbridge/amd/amdk8/raminit_f_dqs.c 8 files changed, 22 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/19027/3 -- To view, visit https://review.coreboot.org/19027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Barnali Sarkar (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Subrata Banik, Balaji Manigandan, Aamir Bohra, Paul Menzel, Hannah Williams, build bot (Jenkins), Furquan Shaikh, Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18557 to look at the new patch set (#13). Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... soc/intel/common/block: [WIP]Add Intel common FAST_SPI code Create Intel Common FAST_SPI Controller code. This code currently only contains the code for SPI initialization required in Bootblock phase, which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h More code will get added up in the subsequent phases. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- A src/soc/intel/common/block/fast_spi/Kconfig A src/soc/intel/common/block/fast_spi/Makefile.inc A src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/include/intelblocks/fast_spi.h 4 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18557/13 -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

1 0

Change in coreboot[master]: nb/amd/amdk8/exit_from_self.c: Use linker instead of include
by Arthur Heymans (Code Review) 28 Mar '17

28 Mar '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/19027 ) Change subject: nb/amd/amdk8/exit_from_self.c: Use linker instead of include ...................................................................... Patch Set 2: Putting it in a header does not work since its declared multiple times (if header is used more than once). So is putting this global variable in romstage.c ok? -- To view, visit https://review.coreboot.org/19027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit March 2017