coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/amd/amdk8/exit_from_self.c: Use linker instead of include
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19027 ) Change subject: nb/amd/amdk8/exit_from_self.c: Use linker instead of include ...................................................................... Patch Set 4: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50861/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6838/ : SUCCESS -- To view, visit https://review.coreboot.org/19027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] nb/amd/amdk8: Link raminit_f.c
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19030 ) Change subject: [WIP] nb/amd/amdk8: Link raminit_f.c ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50862/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6836/ : SUCCESS -- To view, visit https://review.coreboot.org/19030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] Move global variable declaration from header to romsta...
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19029 ) Change subject: [WIP] Move global variable declaration from header to romstage.c ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50860/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6837/ : SUCCESS -- To view, visit https://review.coreboot.org/19029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: [WIP] Move global variable declaration from header to romsta...
by Arthur Heymans (Code Review) 28 Mar '17

28 Mar '17

Hello Kyösti Mälkki, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/19029 to look at the new patch set (#2). Change subject: [WIP] Move global variable declaration from header to romstage.c ...................................................................... [WIP] Move global variable declaration from header to romstage.c This is needed if one wants to use the header more than once. Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g1/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/f.h M src/northbridge/amd/amdk8/pre_f.h M src/northbridge/amd/amdk8/raminit_f.c 37 files changed, 124 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/19029/2 -- To view, visit https://review.coreboot.org/19029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: [WIP] nb/amd/amdk8: Link raminit_f.c
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19030 ) Change subject: [WIP] nb/amd/amdk8: Link raminit_f.c ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50859/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6835/ : SUCCESS -- To view, visit https://review.coreboot.org/19030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

1 0

Change in coreboot[master]: [WIP] nb/amd/amdk8: Link raminit_f.c
by Arthur Heymans (Code Review) 28 Mar '17

28 Mar '17

Arthur Heymans has uploaded a new change for review. ( https://review.coreboot.org/19030 ) Change subject: [WIP] nb/amd/amdk8: Link raminit_f.c ...................................................................... [WIP] nb/amd/amdk8: Link raminit_f.c For this debug.c needed to be linked too. Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/cpu/amd/model_fxx/init_cpus.c M src/mainboard/amd/dbm690t/romstage.c M src/mainboard/amd/mahogany/romstage.c M src/mainboard/amd/pistachio/romstage.c M src/mainboard/amd/serengeti_cheetah/romstage.c M src/mainboard/asrock/939a785gmh/romstage.c M src/mainboard/asus/a8n_e/romstage.c M src/mainboard/asus/a8v-e_deluxe/romstage.c M src/mainboard/asus/a8v-e_se/romstage.c M src/mainboard/asus/k8v-x/romstage.c M src/mainboard/asus/kfsn4-dre_k8/romstage.c M src/mainboard/asus/m2n-e/romstage.c M src/mainboard/asus/m2v-mx_se/romstage.c M src/mainboard/asus/m2v/romstage.c M src/mainboard/broadcom/blast/romstage.c M src/mainboard/gigabyte/ga_2761gxdk/romstage.c M src/mainboard/gigabyte/m57sli/romstage.c M src/mainboard/hp/dl145_g1/romstage.c M src/mainboard/hp/dl145_g3/romstage.c M src/mainboard/iwill/dk8_htx/romstage.c M src/mainboard/kontron/kt690/romstage.c M src/mainboard/msi/ms7135/romstage.c M src/mainboard/msi/ms7260/romstage.c M src/mainboard/msi/ms9185/romstage.c M src/mainboard/msi/ms9282/romstage.c M src/mainboard/nvidia/l1_2pvv/romstage.c M src/mainboard/siemens/sitemp_g1p1/romstage.c M src/mainboard/sunw/ultra40/romstage.c M src/mainboard/sunw/ultra40m2/romstage.c M src/mainboard/supermicro/h8dme/romstage.c M src/mainboard/supermicro/h8dmr/romstage.c M src/mainboard/technexion/tim5690/romstage.c M src/mainboard/technexion/tim8690/romstage.c M src/mainboard/tyan/s2912/romstage.c M src/mainboard/winent/mb6047/romstage.c M src/northbridge/amd/amdk8/Makefile.inc M src/northbridge/amd/amdk8/debug.c M src/northbridge/amd/amdk8/f.h M src/northbridge/amd/amdk8/f_pci.c M src/northbridge/amd/amdk8/raminit.h M src/northbridge/amd/amdk8/raminit_f.c M src/northbridge/amd/amdk8/raminit_f_dqs.c M src/northbridge/amd/amdk8/reset_test.c 43 files changed, 177 insertions(+), 170 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/19030/1 diff --git a/src/cpu/amd/model_fxx/init_cpus.c b/src/cpu/amd/model_fxx/init_cpus.c index d38c552..518b84f 100644 --- a/src/cpu/amd/model_fxx/init_cpus.c +++ b/src/cpu/amd/model_fxx/init_cpus.c @@ -329,6 +329,7 @@ set_var_mtrr(0, 0x00000000, CACHE_TMP_RAMTOP, MTRR_TYPE_WRBACK); #if CONFIG_K8_REV_F_SUPPORT #if CONFIG_MEM_TRAIN_SEQ == 1 + #include <northbridge/amd/amdk8/f.h> train_ram_on_node(id.nodeid, id.coreid, sysinfo, (unsigned)STOP_CAR_AND_CPU); #endif diff --git a/src/mainboard/amd/dbm690t/romstage.c b/src/mainboard/amd/dbm690t/romstage.c index 03b72f3..b37d650 100644 --- a/src/mainboard/amd/dbm690t/romstage.c +++ b/src/mainboard/amd/dbm690t/romstage.c @@ -33,7 +33,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ + /* After sb600_early_setup.c! */ #include <northbridge/amd/amdk8/f.h> #include <arch/early_variables.h> @@ -41,17 +41,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/mahogany/romstage.c b/src/mainboard/amd/mahogany/romstage.c index 95fddfe..21c4555 100644 --- a/src/mainboard/amd/mahogany/romstage.c +++ b/src/mainboard/amd/mahogany/romstage.c @@ -33,7 +33,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ + /* After sb700/early_setup.c! */ #include <northbridge/amd/amdk8/f.h> #include <arch/early_variables.h> @@ -43,10 +43,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8718F_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } @@ -54,7 +54,6 @@ #include "southbridge/amd/rs780/early_setup.c" #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/pistachio/romstage.c b/src/mainboard/amd/pistachio/romstage.c index f341888..e880724 100644 --- a/src/mainboard/amd/pistachio/romstage.c +++ b/src/mainboard/amd/pistachio/romstage.c @@ -31,23 +31,22 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600/early_setup.c! */ + /* After sb600/early_setup.c! */ #include <northbridge/amd/amdk8/f.h> #include <arch/early_variables.h> struct sys_info sysinfo_car CAR_GLOBAL; -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/amd/serengeti_cheetah/romstage.c b/src/mainboard/amd/serengeti_cheetah/romstage.c index cc0f0c5..3df81c4 100644 --- a/src/mainboard/amd/serengeti_cheetah/romstage.c +++ b/src/mainboard/amd/serengeti_cheetah/romstage.c @@ -26,7 +26,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> @@ -47,7 +47,7 @@ outb((1 << 2)|(0 << 0), SMBUS_IO_BASE + 0xc0 + 17); } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -63,7 +63,7 @@ smbus_write_byte(SMBUS_HUB, 0x03, 0); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -72,7 +72,6 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asrock/939a785gmh/romstage.c b/src/mainboard/asrock/939a785gmh/romstage.c index a9fde30..3b2f117 100644 --- a/src/mainboard/asrock/939a785gmh/romstage.c +++ b/src/mainboard/asrock/939a785gmh/romstage.c @@ -34,7 +34,7 @@ #include "northbridge/amd/amdk8/setup_resource_map.c" #include <southbridge/amd/sb700/sb700.h> #include <southbridge/amd/sb700/smbus.h> -#include "northbridge/amd/amdk8/debug.c" /* After sb700/early_setup.c! */ + /* After sb700/early_setup.c! */ #include <northbridge/amd/amdk8/pre_f.h> #include <arch/early_variables.h> @@ -45,10 +45,10 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return do_smbus_read_byte(SMBUS_IO_BASE, device, address); } diff --git a/src/mainboard/asus/a8n_e/romstage.c b/src/mainboard/asus/a8n_e/romstage.c index 4478738..2a4c37e 100644 --- a/src/mainboard/asus/a8n_e/romstage.c +++ b/src/mainboard/asus/a8n_e/romstage.c @@ -38,7 +38,7 @@ #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -50,10 +50,10 @@ struct sys_info sysinfo_car CAR_GLOBAL; -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_deluxe/romstage.c b/src/mainboard/asus/a8v-e_deluxe/romstage.c index 46e2e77..665dde9 100644 --- a/src/mainboard/asus/a8v-e_deluxe/romstage.c +++ b/src/mainboard/asus/a8v-e_deluxe/romstage.c @@ -38,7 +38,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ + /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -51,10 +51,10 @@ #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/a8v-e_se/romstage.c b/src/mainboard/asus/a8v-e_se/romstage.c index 408bc02..9d226a6 100644 --- a/src/mainboard/asus/a8v-e_se/romstage.c +++ b/src/mainboard/asus/a8v-e_se/romstage.c @@ -38,7 +38,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ + /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -51,10 +51,10 @@ #define GPIO_DEV PNP_DEV(0x2e, W83627EHG_GPIO_SUSLED_V) #define ACPI_DEV PNP_DEV(0x2e, W83627EHG_ACPI) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/k8v-x/romstage.c b/src/mainboard/asus/k8v-x/romstage.c index 99dac5e..b77eb27 100644 --- a/src/mainboard/asus/k8v-x/romstage.c +++ b/src/mainboard/asus/k8v-x/romstage.c @@ -38,7 +38,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83697hf/w83697hf.h> #include "southbridge/via/vt8237r/early_smbus.c" -#include "northbridge/amd/amdk8/debug.c" /* After vt8237r/early_smbus.c! */ + /* After vt8237r/early_smbus.c! */ #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include <spd.h> @@ -49,10 +49,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83697HF_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/asus/kfsn4-dre_k8/romstage.c b/src/mainboard/asus/kfsn4-dre_k8/romstage.c index 8ea2815..9364ac6 100644 --- a/src/mainboard/asus/kfsn4-dre_k8/romstage.c +++ b/src/mainboard/asus/kfsn4-dre_k8/romstage.c @@ -35,7 +35,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/amd/mtrr.h> #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> @@ -47,11 +47,9 @@ #define SERIAL_DEV PNP_DEV(0x2e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl); - -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -59,7 +57,6 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" @@ -184,7 +181,8 @@ RC01 | DIMM0, RC01 | DIMM2, RC01 | DIMM4, RC01 | DIMM6, RC01 | DIMM1, RC01 | DIMM3, RC01 | DIMM5, RC01 | DIMM7, }; -static void activate_spd_rom(const struct mem_controller *ctrl) { +void activate_spd_rom(const struct mem_controller *ctrl) +{ printk(BIOS_DEBUG, "activate_spd_rom() for node %02x\n", ctrl->node_id); if (ctrl->node_id == 0) { printk(BIOS_DEBUG, "enable_spd_node0()\n"); diff --git a/src/mainboard/asus/m2n-e/romstage.c b/src/mainboard/asus/m2n-e/romstage.c index 4820912..0bc9b9e 100644 --- a/src/mainboard/asus/m2n-e/romstage.c +++ b/src/mainboard/asus/m2n-e/romstage.c @@ -36,7 +36,7 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -59,10 +59,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -71,7 +71,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/asus/m2v-mx_se/romstage.c b/src/mainboard/asus/m2v-mx_se/romstage.c index e2ba679..cfbd620 100644 --- a/src/mainboard/asus/m2v-mx_se/romstage.c +++ b/src/mainboard/asus/m2v-mx_se/romstage.c @@ -34,7 +34,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" @@ -49,10 +49,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -61,7 +61,6 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/asus/m2v/romstage.c b/src/mainboard/asus/m2v/romstage.c index 4225631..1de013c 100644 --- a/src/mainboard/asus/m2v/romstage.c +++ b/src/mainboard/asus/m2v/romstage.c @@ -34,7 +34,7 @@ #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include "southbridge/via/vt8237r/early_smbus.c" @@ -53,10 +53,10 @@ extern struct sys_info sysinfo_car; -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -65,7 +65,6 @@ #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "cpu/amd/dualcore/dualcore.c" #include "cpu/amd/model_fxx/init_cpus.c" diff --git a/src/mainboard/broadcom/blast/romstage.c b/src/mainboard/broadcom/blast/romstage.c index 8ec62bd..4d26201 100644 --- a/src/mainboard/broadcom/blast/romstage.c +++ b/src/mainboard/broadcom/blast/romstage.c @@ -13,7 +13,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -27,7 +27,7 @@ unsigned get_sbdn(unsigned bus); static void memreset_setup(void) { } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -36,7 +36,7 @@ smbus_send_byte(SMBUS_HUB, device); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c index 6f95abd..68f95b2 100644 --- a/src/mainboard/gigabyte/ga_2761gxdk/romstage.c +++ b/src/mainboard/gigabyte/ga_2761gxdk/romstage.c @@ -37,7 +37,7 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include "southbridge/sis/sis966/early_ctrl.c" @@ -48,10 +48,10 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8716F_SP1) #define CLKIN_DEV PNP_DEV(0x2e, IT8716F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -59,7 +59,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/gigabyte/m57sli/romstage.c b/src/mainboard/gigabyte/m57sli/romstage.c index cff283f..640a694 100644 --- a/src/mainboard/gigabyte/m57sli/romstage.c +++ b/src/mainboard/gigabyte/m57sli/romstage.c @@ -34,7 +34,6 @@ #include <superio/ite/common/ite.h> #include <superio/ite/it8716f/it8716f.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" #include "northbridge/amd/amdk8/setup_resource_map.c" #include <arch/early_variables.h> @@ -56,10 +55,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -78,7 +77,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/hp/dl145_g1/romstage.c b/src/mainboard/hp/dl145_g1/romstage.c index acab760..df6ce3f 100644 --- a/src/mainboard/hp/dl145_g1/romstage.c +++ b/src/mainboard/hp/dl145_g1/romstage.c @@ -16,7 +16,7 @@ #include "southbridge/amd/amd8111/early_smbus.c" #include <northbridge/amd/amdk8/raminit.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> @@ -43,7 +43,7 @@ } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -80,7 +80,7 @@ printk(BIOS_DEBUG, "change_i2c_mux 2 ret=%08x\n", ret); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/hp/dl145_g3/romstage.c b/src/mainboard/hp/dl145_g3/romstage.c index 27fc82b..6d6e616 100644 --- a/src/mainboard/hp/dl145_g3/romstage.c +++ b/src/mainboard/hp/dl145_g3/romstage.c @@ -39,7 +39,7 @@ #include <superio/serverengines/pilot/pilot.h> #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -51,7 +51,7 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -62,7 +62,7 @@ smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -71,7 +71,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include <spd.h> #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/iwill/dk8_htx/romstage.c b/src/mainboard/iwill/dk8_htx/romstage.c index 713401f..fe66610 100644 --- a/src/mainboard/iwill/dk8_htx/romstage.c +++ b/src/mainboard/iwill/dk8_htx/romstage.c @@ -12,7 +12,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <cpu/x86/bist.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -42,7 +42,7 @@ } } -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { if (is_cpu_pre_c0()) { udelay(800); @@ -52,9 +52,9 @@ } } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/kontron/kt690/romstage.c b/src/mainboard/kontron/kt690/romstage.c index 6ffa53a..b769caa 100644 --- a/src/mainboard/kontron/kt690/romstage.c +++ b/src/mainboard/kontron/kt690/romstage.c @@ -28,7 +28,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627dhg/w83627dhg.h> #include <cpu/amd/mtrr.h> @@ -41,17 +41,16 @@ #include <arch/early_variables.h> struct sys_info sysinfo_car CAR_GLOBAL; -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/msi/ms7135/romstage.c b/src/mainboard/msi/ms7135/romstage.c index 5c85d7b..9d8ac82 100644 --- a/src/mainboard/msi/ms7135/romstage.c +++ b/src/mainboard/msi/ms7135/romstage.c @@ -35,7 +35,7 @@ #include <southbridge/nvidia/ck804/early_smbus.h> #include <northbridge/amd/amdk8/raminit.h> #include <delay.h> -#include "northbridge/amd/amdk8/debug.c" + #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" #include "northbridge/amd/amdk8/coherent_ht.c" @@ -52,10 +52,10 @@ #define SERIAL_DEV PNP_DEV(0x4e, W83627THG_SP1) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/msi/ms7260/romstage.c b/src/mainboard/msi/ms7260/romstage.c index c4cd330..e886740 100644 --- a/src/mainboard/msi/ms7260/romstage.c +++ b/src/mainboard/msi/ms7260/romstage.c @@ -36,7 +36,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -58,10 +58,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) {} +void memreset(int controllers, const struct mem_controller *ctrl) {} static inline void activate_spd_rom(const struct mem_controller *ctrl) {} -static inline int spd_read_byte(unsigned int device, unsigned int address) +int spd_read_byte(unsigned int device, unsigned int address) { return smbus_read_byte(device, address); } @@ -70,7 +70,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9185/romstage.c b/src/mainboard/msi/ms9185/romstage.c index cec5e2e..d3a3cda 100644 --- a/src/mainboard/msi/ms9185/romstage.c +++ b/src/mainboard/msi/ms9185/romstage.c @@ -35,7 +35,7 @@ #include <reset.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/nsc/pc87417/pc87417.h> #include <cpu/x86/bist.h> #include "northbridge/amd/amdk8/setup_resource_map.c" @@ -49,7 +49,7 @@ unsigned get_sbdn(unsigned bus); -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -60,7 +60,7 @@ smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f ); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -69,7 +69,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/msi/ms9282/romstage.c b/src/mainboard/msi/ms9282/romstage.c index 054457c..582abea 100644 --- a/src/mainboard/msi/ms9282/romstage.c +++ b/src/mainboard/msi/ms9282/romstage.c @@ -32,7 +32,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> @@ -59,7 +59,7 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -70,7 +70,7 @@ smbus_send_byte(SMBUS_SWITCH2, (device >> 4) & 0x0f); } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -79,7 +79,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/nvidia/l1_2pvv/romstage.c b/src/mainboard/nvidia/l1_2pvv/romstage.c index 2332f54..3092290 100644 --- a/src/mainboard/nvidia/l1_2pvv/romstage.c +++ b/src/mainboard/nvidia/l1_2pvv/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627ehg/w83627ehg.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -57,10 +57,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -69,7 +69,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/siemens/sitemp_g1p1/romstage.c b/src/mainboard/siemens/sitemp_g1p1/romstage.c index ae7c2fc..93f8fd4 100644 --- a/src/mainboard/siemens/sitemp_g1p1/romstage.c +++ b/src/mainboard/siemens/sitemp_g1p1/romstage.c @@ -40,7 +40,7 @@ #include "southbridge/amd/rs690/early_setup.c" #include "southbridge/amd/sb600/early_setup.c" -#include "northbridge/amd/amdk8/debug.c" /* After sb600_early_setup.c! */ + /* After sb600_early_setup.c! */ #include <northbridge/amd/amdk8/pre_f.h> #include <arch/early_variables.h> @@ -50,7 +50,7 @@ #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) /* CAN'T BE REMOVED! crt0.S will use it. I don't know WHY!*/ -static void memreset(int controllers, const struct mem_controller *ctrl) +void memreset(int controllers, const struct mem_controller *ctrl) { } @@ -60,14 +60,13 @@ } /*called in raminit_f.c */ -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/sunw/ultra40/romstage.c b/src/mainboard/sunw/ultra40/romstage.c index 0a3e0c2..d1b90fa 100644 --- a/src/mainboard/sunw/ultra40/romstage.c +++ b/src/mainboard/sunw/ultra40/romstage.c @@ -15,7 +15,7 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/smsc/lpc47b397/lpc47b397.h> #include <cpu/x86/bist.h> #include "superio/smsc/lpc47b397/early_gpio.c" @@ -29,7 +29,7 @@ #define SUPERIO_GPIO_DEV PNP_DEV(0x2e, LPC47B397_RT) #define SUPERIO_GPIO_IO_BASE 0x400 -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } #ifdef ENABLE_ONBOARD_SCSI static void sio_gpio_setup(void) @@ -45,7 +45,7 @@ static inline void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/mainboard/sunw/ultra40m2/romstage.c b/src/mainboard/sunw/ultra40m2/romstage.c index 756cd47..3a34a92 100644 --- a/src/mainboard/sunw/ultra40m2/romstage.c +++ b/src/mainboard/sunw/ultra40m2/romstage.c @@ -34,7 +34,7 @@ #include "northbridge/amd/amdk8/reset_test.c" #include <superio/smsc/dme1737/dme1737.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -56,10 +56,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -68,7 +68,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dme/romstage.c b/src/mainboard/supermicro/h8dme/romstage.c index 436efd7..4db3068 100644 --- a/src/mainboard/supermicro/h8dme/romstage.c +++ b/src/mainboard/supermicro/h8dme/romstage.c @@ -32,7 +32,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -55,7 +55,7 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } static inline void activate_spd_rom(const struct mem_controller *ctrl) { @@ -69,7 +69,7 @@ #endif } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -78,7 +78,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/supermicro/h8dmr/romstage.c b/src/mainboard/supermicro/h8dmr/romstage.c index 9339fa4..ba44ca8 100644 --- a/src/mainboard/supermicro/h8dmr/romstage.c +++ b/src/mainboard/supermicro/h8dmr/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -58,10 +58,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -70,7 +70,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/technexion/tim5690/romstage.c b/src/mainboard/technexion/tim5690/romstage.c index 98b4100..7a790bd 100644 --- a/src/mainboard/technexion/tim5690/romstage.c +++ b/src/mainboard/technexion/tim5690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -42,17 +42,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/technexion/tim8690/romstage.c b/src/mainboard/technexion/tim8690/romstage.c index a1cc6d2..35933e2 100644 --- a/src/mainboard/technexion/tim8690/romstage.c +++ b/src/mainboard/technexion/tim8690/romstage.c @@ -27,7 +27,7 @@ #include <spd.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" + #include <superio/ite/common/ite.h> #include <superio/ite/it8712f/it8712f.h> #include <cpu/x86/bist.h> @@ -42,17 +42,16 @@ #define SERIAL_DEV PNP_DEV(0x2e, IT8712F_SP1) #define GPIO_DEV PNP_DEV(0x2e, IT8712F_GPIO) -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(u32 device, u32 address) +int spd_read_byte(u32 device, u32 address) { return smbus_read_byte(device, address); } #include <northbridge/amd/amdk8/amdk8.h> #include "northbridge/amd/amdk8/incoherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "northbridge/amd/amdk8/coherent_ht.c" #include "lib/generic_sdram.c" #include "resourcemap.c" diff --git a/src/mainboard/tyan/s2912/romstage.c b/src/mainboard/tyan/s2912/romstage.c index 027de72..03c42d6 100644 --- a/src/mainboard/tyan/s2912/romstage.c +++ b/src/mainboard/tyan/s2912/romstage.c @@ -35,7 +35,7 @@ #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627hf/w83627hf.h> #include <cpu/x86/bist.h> -#include "northbridge/amd/amdk8/debug.c" + #include "northbridge/amd/amdk8/setup_resource_map.c" #include <northbridge/amd/amdk8/f.h> @@ -57,10 +57,10 @@ return (dev >> 15) & 0x1f; } -static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void memreset(int controllers, const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } @@ -69,7 +69,6 @@ #include <northbridge/amd/amdk8/f.h> #include "northbridge/amd/amdk8/incoherent_ht.c" #include "northbridge/amd/amdk8/coherent_ht.c" -#include "northbridge/amd/amdk8/raminit_f.c" #include "lib/generic_sdram.c" #include "resourcemap.c" #include "cpu/amd/dualcore/dualcore.c" diff --git a/src/mainboard/winent/mb6047/romstage.c b/src/mainboard/winent/mb6047/romstage.c index dd9e30e..7243228 100644 --- a/src/mainboard/winent/mb6047/romstage.c +++ b/src/mainboard/winent/mb6047/romstage.c @@ -15,7 +15,6 @@ #include <delay.h> #include <cpu/x86/lapic.h> #include "northbridge/amd/amdk8/reset_test.c" -#include "northbridge/amd/amdk8/debug.c" #include <superio/winbond/common/winbond.h> #include <superio/winbond/w83627thg/w83627thg.h> #include <cpu/x86/bist.h> @@ -29,9 +28,9 @@ static void memreset_setup(void) { } static void memreset(int controllers, const struct mem_controller *ctrl) { } -static void activate_spd_rom(const struct mem_controller *ctrl) { } +void activate_spd_rom(const struct mem_controller *ctrl) { } -static inline int spd_read_byte(unsigned device, unsigned address) +int spd_read_byte(unsigned device, unsigned address) { return smbus_read_byte(device, address); } diff --git a/src/northbridge/amd/amdk8/Makefile.inc b/src/northbridge/amd/amdk8/Makefile.inc index 7497a07..fb2aca5 100644 --- a/src/northbridge/amd/amdk8/Makefile.inc +++ b/src/northbridge/amd/amdk8/Makefile.inc @@ -4,8 +4,11 @@ ramstage-y += misc_control.c ramstage-y += get_sblk_pci1234.c ramstage-$(CONFIG_HAVE_ACPI_TABLES) += acpi.c + +romstage-y += debug.c ifeq ($(CONFIG_K8_REV_F_SUPPORT),y) romstage-$(CONFIG_HAVE_ACPI_RESUME) += exit_from_self.c +romstage-y += raminit_f.c endif # Enable this if you want to check the values of the PCI routing registers. diff --git a/src/northbridge/amd/amdk8/debug.c b/src/northbridge/amd/amdk8/debug.c index a8431f4..e1eade4 100644 --- a/src/northbridge/amd/amdk8/debug.c +++ b/src/northbridge/amd/amdk8/debug.c @@ -3,7 +3,13 @@ * */ -static inline void print_debug_addr(const char *str, void *val) +#include "debug.h" +#include <console/console.h> +#include <arch/io.h> +#include <device/pci_def.h> +#include <delay.h> + +void print_debug_addr(const char *str, void *val) { #if CONFIG_DEBUG_CAR printk(BIOS_DEBUG, "------Address debug: %s%p------\n", str, val); @@ -11,12 +17,12 @@ } #if 1 -static void print_debug_pci_dev(unsigned dev) +void print_debug_pci_dev(unsigned dev) { printk(BIOS_DEBUG, "PCI: %02x:%02x.%02x", (dev>>20) & 0xff, (dev>>15) & 0x1f, (dev>>12) & 0x7); } -static inline void print_pci_devices(void) +void print_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -41,7 +47,7 @@ } } -static void dump_pci_device(unsigned dev) +void dump_pci_device(unsigned dev) { int i; print_debug_pci_dev(dev); @@ -58,9 +64,7 @@ } #if CONFIG_K8_REV_F_SUPPORT -static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, - uint32_t index_reg, uint32_t index); -static inline void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) +void dump_pci_device_index_wait(unsigned dev, uint32_t index_reg) { int i; print_debug_pci_dev(dev); @@ -81,7 +85,7 @@ } #endif -static inline void dump_pci_devices(void) +void dump_pci_devices(void) { pci_devfn_t dev; for (dev = PCI_DEV(0, 0, 0); @@ -106,7 +110,7 @@ } } -static inline void dump_pci_devices_on_bus(unsigned busn) +void dump_pci_devices_on_bus(unsigned busn) { pci_devfn_t dev; for (dev = PCI_DEV(busn, 0, 0); @@ -133,7 +137,7 @@ #if CONFIG_DEBUG_SMBUS -static void dump_spd_registers(const struct mem_controller *ctrl) +void dump_spd_registers(const struct mem_controller *ctrl) { int i; printk(BIOS_DEBUG, "\n"); @@ -179,7 +183,7 @@ } } } -static void dump_smbus_registers(void) +void dump_smbus_registers(void) { unsigned device; printk(BIOS_DEBUG, "\n"); @@ -205,7 +209,7 @@ } #endif -static inline void dump_io_resources(unsigned port) +void dump_io_resources(unsigned port) { int i; @@ -225,7 +229,7 @@ } } -static inline void dump_mem(unsigned start, unsigned end) +void dump_mem(unsigned start, unsigned end) { unsigned i; printk(BIOS_DEBUG, "dump_mem:"); diff --git a/src/northbridge/amd/amdk8/f.h b/src/northbridge/amd/amdk8/f.h index b5e89ad..4f10257 100644 --- a/src/northbridge/amd/amdk8/f.h +++ b/src/northbridge/amd/amdk8/f.h @@ -579,6 +579,10 @@ } #endif +extern struct sys_info sysinfo_car; + void dqs_restore_MC_NVRAM(unsigned int dev); +void train_ram_on_node(unsigned nodeid, unsigned coreid, + struct sys_info *sysinfo, unsigned retcall); #endif /* AMDK8_F_H */ diff --git a/src/northbridge/amd/amdk8/f_pci.c b/src/northbridge/amd/amdk8/f_pci.c index 3ea4003..230333a 100644 --- a/src/northbridge/amd/amdk8/f_pci.c +++ b/src/northbridge/amd/amdk8/f_pci.c @@ -1,6 +1,8 @@ #ifndef AMDK8_F_PCI_C #define AMDK8_F_PCI_C +#include "debug.h" + #ifdef UNUSED_CODE /* bit [10,8] are dev func, bit[1,0] are dev index */ static uint32_t pci_read_config32_index(pci_devfn_t dev, uint32_t index_reg, @@ -24,7 +26,7 @@ } #endif -static uint32_t pci_read_config32_index_wait(pci_devfn_t dev, +uint32_t pci_read_config32_index_wait(pci_devfn_t dev, uint32_t index_reg, uint32_t index) { uint32_t dword; diff --git a/src/northbridge/amd/amdk8/raminit.h b/src/northbridge/amd/amdk8/raminit.h index 95a99b0..9b5921d 100644 --- a/src/northbridge/amd/amdk8/raminit.h +++ b/src/northbridge/amd/amdk8/raminit.h @@ -1,6 +1,9 @@ #ifndef RAMINIT_H #define RAMINIT_H +#define NODE_ID 0x60 +#define HT_INIT_CONTROL 0x6c + #define NODE_NUMS 8 #define DIMM_SOCKETS 4 @@ -12,14 +15,24 @@ }; struct sys_info; + void exit_from_self(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo); void setup_resource_map(const unsigned int *register_values, int max); void set_hw_mem_hole(int controllers, const struct mem_controller *ctrl); +int spd_read_byte(unsigned device, unsigned address); +void activate_spd_rom(const struct mem_controller *ctrl); +void memreset(int controllers, const struct mem_controller *ctrl); +void set_sysinfo_in_ram(unsigned int val); #define TIMEOUT_LOOPS 300000 #if defined(__PRE_RAM__) && CONFIG_RAMINIT_SYSINFO void sdram_initialize(int controllers, const struct mem_controller *ctrl, void *sysinfo); +void sdram_enable(int controllers, const struct mem_controller *ctrl, + struct sys_info *sysinfo); +void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo); +void sdram_set_spd_registers(const struct mem_controller *ctrl, + struct sys_info *sysinfo); #else void sdram_initialize(int controllers, const struct mem_controller *ctrl); #endif diff --git a/src/northbridge/amd/amdk8/raminit_f.c b/src/northbridge/amd/amdk8/raminit_f.c index 06c93a9..c736c37 100644 --- a/src/northbridge/amd/amdk8/raminit_f.c +++ b/src/northbridge/amd/amdk8/raminit_f.c @@ -16,14 +16,20 @@ * GNU General Public License for more details. */ +#include <arch/io.h> +#include <console/console.h> #include <cpu/x86/cache.h> +#include <cpu/x86/msr.h> #include <cpu/x86/mtrr.h> #include <cpu/x86/tsc.h> #include <cpu/amd/mtrr.h> +#include <pc80/mc146818rtc.h> #include <lib.h> #include <stdlib.h> +#include <string.h> #include <arch/acpi.h> +#include "amdk8.h" #include "raminit.h" #include "f.h" #include <spd_ddr2.h> @@ -88,7 +94,7 @@ return pci_read_config32(ctrl->f0, 0) == 0x11001022; } -static void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) +void sdram_set_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) { static const unsigned int register_values[] = { @@ -2789,7 +2795,7 @@ return meminfo->dimm_mask; } -static void sdram_set_spd_registers(const struct mem_controller *ctrl, +void sdram_set_spd_registers(const struct mem_controller *ctrl, struct sys_info *sysinfo) { struct spd_set_memclk_result result; @@ -2969,7 +2975,7 @@ } #endif -static void sdram_enable(int controllers, const struct mem_controller *ctrl, +void sdram_enable(int controllers, const struct mem_controller *ctrl, struct sys_info *sysinfo) { int i; diff --git a/src/northbridge/amd/amdk8/raminit_f_dqs.c b/src/northbridge/amd/amdk8/raminit_f_dqs.c index 1e99f33..8943cbe 100644 --- a/src/northbridge/amd/amdk8/raminit_f_dqs.c +++ b/src/northbridge/amd/amdk8/raminit_f_dqs.c @@ -17,6 +17,7 @@ #include <arch/stages.h> #include <cpu/x86/cr.h> #include <cpu/x86/mtrr.h> +#include <arch/early_variables.h> //0: mean no debug info #define DQS_TRAIN_DEBUG 0 @@ -1769,7 +1770,7 @@ } #endif -static void set_sysinfo_in_ram(unsigned val) +void set_sysinfo_in_ram(unsigned val) { #if CONFIG_MEM_TRAIN_SEQ == 1 set_htic_bit(0, val, 9); @@ -2034,7 +2035,7 @@ } -static inline void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) +void train_ram_on_node(unsigned nodeid, unsigned coreid, struct sys_info *sysinfo, unsigned retcall) { if (coreid) return; // only do it on core0 struct sys_info *sysinfox; diff --git a/src/northbridge/amd/amdk8/reset_test.c b/src/northbridge/amd/amdk8/reset_test.c index d8734a9..f998c48 100644 --- a/src/northbridge/amd/amdk8/reset_test.c +++ b/src/northbridge/amd/amdk8/reset_test.c @@ -1,7 +1,6 @@ #include <stdint.h> #include <cpu/x86/lapic.h> -#define NODE_ID 0x60 -#define HT_INIT_CONTROL 0x6c +#include "raminit.h" #define HTIC_ColdR_Detect (1<<4) #define HTIC_BIOSR_Detect (1<<5) -- To view, visit https://review.coreboot.org/19030 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newchange Gerrit-Change-Id: I9cd1ffff2c39021693fe1d5d3f90ec5f70891f57 Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: [WIP] Move global variable declaration from header to romsta...
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19029 ) Change subject: [WIP] Move global variable declaration from header to romstage.c ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50858/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6834/ : SUCCESS -- To view, visit https://review.coreboot.org/19029 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I375d08465b6c64cd91e7563e3917764507d779ba Gerrit-PatchSet: 1 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: KBL: Update FSP headers - upgrade to FSP.2.0.0
by Barnali Sarkar (Code Review) 28 Mar '17

28 Mar '17

Barnali Sarkar has posted comments on this change. ( https://review.coreboot.org/19023 ) Change subject: KBL: Update FSP headers - upgrade to FSP.2.0.0 ...................................................................... Patch Set 2: (2 comments) https://review.coreboot.org/#/c/19023/2/src/vendorcode/intel/fsp/fsp2_0/sky… File src/vendorcode/intel/fsp/fsp2_0/skykabylake/ConfigBlock/CpuConfigFspData.h: Line 69: There is no change here actually. https://review.coreboot.org/#/c/19023/2/src/vendorcode/intel/fsp/fsp2_0/sky… File src/vendorcode/intel/fsp/fsp2_0/skykabylake/MemInfoHob.h: PS2, Line 206: EFI_HOB_GUID_TYPE EfiHobGuidType This parameter should be skipped. FSP should only publish the Raw data of the HOB, it should not include the HOB Header. -- To view, visit https://review.coreboot.org/19023 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: Id8ecea6fa5f4e7a72410f8da535ab9c4808b3482 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-HasComments: Yes

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Change in coreboot[master]: nb/amd/amdk8/exit_from_self.c: Use linker instead of include
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/19027 ) Change subject: nb/amd/amdk8/exit_from_self.c: Use linker instead of include ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/50857/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/6833/ : SUCCESS -- To view, visit https://review.coreboot.org/19027 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I716b37e71ab3a4409709357f50f79e3149ede2b6 Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by build bot (Jenkins) (Code Review) 28 Mar '17

28 Mar '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/18557 ) Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... Patch Set 13: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/50856/ : SUCCESS https://qa.coreboot.org/job/coreboot-checkpatch/6832/ : SUCCESS -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 13 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit March 2017