coreboot-gerrit March 2017

coreboot-gerrit@coreboot.org

1 participants
2925 discussions

Change in coreboot[master]: soc/intel/common/block: Add Intel common systemagent support
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Barnali Sarkar, dhaval v sharma, Balaji Manigandan, Paul Menzel, build bot (Jenkins), Hannah Williams, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18565 to look at the new patch set (#19). Change subject: soc/intel/common/block: Add Intel common systemagent support ...................................................................... soc/intel/common/block: Add Intel common systemagent support Create common Intel systemagent code. This code currently contains the SA initialization required in Bootblock phase, which has the following programming- * Set PCIEXBAR * Clear TSEG register More code will get added up in the subsequent phases. Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/common/block/include/intelblocks/systemagent.h A src/soc/intel/common/block/systemagent/Kconfig A src/soc/intel/common/block/systemagent/Makefile.inc A src/soc/intel/common/block/systemagent/systemagent.c 4 files changed, 123 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/65/18565/19 -- To view, visit https://review.coreboot.org/18565 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I6f0c515278f7fd04d407463a1eeb25ba13639f5c Gerrit-PatchSet: 19 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Code clean up by using common PCR module
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Barnali Sarkar, Ravishankar Sarawadi, Bora Guvendik, Hannah Williams, Shaunak Saha, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18674 to look at the new patch set (#4). Change subject: soc/intel/skylake: Code clean up by using common PCR module ...................................................................... soc/intel/skylake: Code clean up by using common PCR module This patch creates PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pci_ids.h Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc M src/soc/intel/skylake/acpi/irqlinks.asl M src/soc/intel/skylake/acpi/pch.asl M src/soc/intel/skylake/acpi/pcr.asl M src/soc/intel/skylake/bootblock/pch.c M src/soc/intel/skylake/bootblock/uart.c M src/soc/intel/skylake/finalize.c M src/soc/intel/skylake/gpio.c M src/soc/intel/skylake/include/soc/iomap.h D src/soc/intel/skylake/include/soc/pcr.h M src/soc/intel/skylake/lpc.c D src/soc/intel/skylake/pcr.c M src/soc/intel/skylake/pmc.c M src/soc/intel/skylake/smihandler.c 15 files changed, 32 insertions(+), 338 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/18674/4 -- To view, visit https://review.coreboot.org/18674 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id9336883514298e7f93fbc95aef8228202aa6fb9 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Code clean up by using common PCR module
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Barnali Sarkar, Ravishankar Sarawadi, Bora Guvendik, Hannah Williams, Shaunak Saha, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18673 to look at the new patch set (#4). Change subject: soc/intel/apollolake: Code clean up by using common PCR module ...................................................................... soc/intel/apollolake: Code clean up by using common PCR module This patch creates PCR library to perform CRRd and CRWr operation using Port Ids, define inside soc/pci_ids.h Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/acpi/gpio.asl M src/soc/intel/apollolake/acpi/scs.asl M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/gpio.c M src/soc/intel/apollolake/include/soc/gpio_defs.h M src/soc/intel/apollolake/include/soc/iomap.h D src/soc/intel/apollolake/include/soc/iosf.h M src/soc/intel/apollolake/itss.c 9 files changed, 77 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/73/18673/4 -- To view, visit https://review.coreboot.org/18673 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iacbf58dbd55bf3915676d875fcb484362d357a44 Gerrit-PatchSet: 4 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Ravishankar Sarawadi <ravishankar.sarawadi(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Barnali Sarkar, Balaji Manigandan, Aamir Bohra, Paul Menzel, Hannah Williams, build bot (Jenkins), Furquan Shaikh, Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18557 to look at the new patch set (#14). Change subject: soc/intel/common/block: [WIP]Add Intel common FAST_SPI code ...................................................................... soc/intel/common/block: [WIP]Add Intel common FAST_SPI code Create Intel Common FAST_SPI Controller code. This code currently only contains the code for SPI initialization required in Bootblock phase, which has the following programming - * Get BIOS Rom Region Size * Enable SPIBAR * Disable the BIOS write protect so write commands are allowed * Enable SPI Prefetching and Caching. * SPI Controller register offsets in the common header fast_spi.h More code will get added up in the subsequent phases. Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> --- A src/soc/intel/common/block/fast_spi/Kconfig A src/soc/intel/common/block/fast_spi/Makefile.inc A src/soc/intel/common/block/fast_spi/fast_spi.c A src/soc/intel/common/block/include/intelblocks/fast_spi.h 4 files changed, 266 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/18557/14 -- To view, visit https://review.coreboot.org/18557 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I046e3b30c8efb172851dd17f49565c9ec4cb38cb Gerrit-PatchSet: 14 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common System A...
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Barnali Sarkar, dhaval v sharma, Balaji Manigandan, Paul Menzel, build bot (Jenkins), Hannah Williams, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18567 to look at the new patch set (#24). Change subject: soc/intel/apollolake: Clean up code by using common System Agent module ...................................................................... soc/intel/apollolake: Clean up code by using common System Agent module This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/bootblock/bootblock.c M src/soc/intel/apollolake/chip.c R src/soc/intel/apollolake/include/soc/systemagent.h M src/soc/intel/apollolake/memmap.c M src/soc/intel/apollolake/northbridge.c M src/soc/intel/apollolake/romstage.c 7 files changed, 15 insertions(+), 31 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/18567/24 -- To view, visit https://review.coreboot.org/18567 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I01a24e2d4f1c8c9ca113c128bb6b3eac23dc79ad Gerrit-PatchSet: 24 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Clean up code by using common System Agen...
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Pratikkumar V Prajapati, Barnali Sarkar, dhaval v sharma, Balaji Manigandan, Paul Menzel, build bot (Jenkins), Hannah Williams, Pratikkumar Prajapati, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18566 to look at the new patch set (#20). Change subject: soc/intel/skylake: Clean up code by using common System Agent module ...................................................................... soc/intel/skylake: Clean up code by using common System Agent module This patch currently contains the SA initialization required for bootblock phase - 1. Use SOC_INTEL_COMMON_BLOCK_SA kconfig for common SA code. 2. Perform PCIEXBAR programming based on soc configurable PCIEX_LENGTH_xxxMB 3. Use common systemagent header file. Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Signed-off-by: Barnali Sarkar <barnali.sarkar(a)intel.com> Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/bootblock/systemagent.c M src/soc/intel/skylake/include/soc/bootblock.h M src/soc/intel/skylake/include/soc/iomap.h M src/soc/intel/skylake/include/soc/systemagent.h 6 files changed, 10 insertions(+), 60 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/18566/20 -- To view, visit https://review.coreboot.org/18566 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I0fa0a60f680b9b00b7f26f1875c553612b123a8e Gerrit-PatchSet: 20 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: soc/intel/common/block: Add Intel common PCR support
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Barnali Sarkar, Bora Guvendik, Hannah Williams, Shaunak Saha, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18669 to look at the new patch set (#2). Change subject: soc/intel/common/block: Add Intel common PCR support ...................................................................... soc/intel/common/block: Add Intel common PCR support IOSF_SB message space is used to access registers mapped on IOSF-SB. These registers include uncore CRs (configuration registers) and chipset specific registers. The Private Configuration Register (PCR) space is accessed on IOSF-SB using destination ID also known as Port ID. Access to IOSF-SB by the Host or System Agent is possible over PSF via the Primary to Sideband Bridge (P2SB). P2SB will forward properly formatted register access requests as CRRd and CRWr request via IOSF-SB. Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- A src/soc/intel/apollolake/include/soc/pcr_ids.h A src/soc/intel/common/block/include/intelblocks/pcr.h A src/soc/intel/common/block/pcr/Kconfig A src/soc/intel/common/block/pcr/Makefile.inc A src/soc/intel/common/block/pcr/pcr.c A src/soc/intel/skylake/include/soc/pcr_ids.h 6 files changed, 367 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/69/18669/2 -- To view, visit https://review.coreboot.org/18669 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I78526a86b6d10f226570c08050327557e0bb2c78 Gerrit-PatchSet: 2 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Shaunak Saha <shaunak.saha(a)intel.com>

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Change in coreboot[master]: soc/intel/apollolake: Clean up code by using common CAR init
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Barnali Sarkar, Paul Menzel, build bot (Jenkins), Furquan Shaikh, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18555 to look at the new patch set (#26). Change subject: soc/intel/apollolake: Clean up code by using common CAR init ...................................................................... soc/intel/apollolake: Clean up code by using common CAR init This patch currently contains common CAR initialization required in bootblock phase along with common MSR header - 1. Use SOC_INTEL_COMMON_BLOCK_CAR to have common CAR initialization and CAR teardown. 2. Use common MSR header "intelblocks/msr.h" inside soc/cpu.h Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/apollolake/Kconfig M src/soc/intel/apollolake/Makefile.inc D src/soc/intel/apollolake/bootblock/cache_as_ram.S D src/soc/intel/apollolake/exit_car.S M src/soc/intel/apollolake/include/soc/cpu.h 5 files changed, 17 insertions(+), 385 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/18555/26 -- To view, visit https://review.coreboot.org/18555 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: I67f909f50a24f009b3e35388665251be1dde40f7 Gerrit-PatchSet: 26 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins)

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Change in coreboot[master]: soc/intel/common/block: Add cache as ram init and teardown code
by Subrata Banik (Code Review) 28 Mar '17

28 Mar '17

Hello Aaron Durbin, Barnali Sarkar, dhaval v sharma, Balaji Manigandan, Paul Menzel, Rizwan Qureshi, build bot (Jenkins), Hannah Williams, Martin Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/18381 to look at the new patch set (#39). Change subject: soc/intel/common/block: Add cache as ram init and teardown code ...................................................................... soc/intel/common/block: Add cache as ram init and teardown code Create sample model for common car init and teardown programming. TEST=Booted Reef, KCRD/EVE, GLKRVP with CAR_CQOS, CAR_NEM_ENHANCED and CAR_NEM configs till post code 0x2a. Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/drivers/intel/fsp1_1/after_raminit.S A src/soc/intel/common/block/cpu/Kconfig A src/soc/intel/common/block/cpu/Makefile.inc A src/soc/intel/common/block/cpu/car/cache_as_ram.S A src/soc/intel/common/block/cpu/car/exit_car.S M src/soc/intel/skylake/Kconfig M src/soc/intel/skylake/Makefile.inc D src/soc/intel/skylake/bootblock/cache_as_ram.S D src/soc/intel/skylake/include/soc/car_teardown.S M src/soc/intel/skylake/romstage/car_stage_fsp20.S 10 files changed, 601 insertions(+), 341 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/18381/39 -- To view, visit https://review.coreboot.org/18381 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: newpatchset Gerrit-Change-Id: Iffd0c3e3ca81a3d283d5f1da115222a222e6b157 Gerrit-PatchSet: 39 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Aamir Bohra <aamir.bohra(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com>

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Change in coreboot[master]: siemens/mc_apl1: Adjust gpio settings
by Werner Zeh (Code Review) 28 Mar '17

28 Mar '17

Werner Zeh has posted comments on this change. ( https://review.coreboot.org/18995 ) Change subject: siemens/mc_apl1: Adjust gpio settings ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/18995 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-MessageType: comment Gerrit-Change-Id: I2f440e863c2e6f59298c500ac5aefa3b7386bcdf Gerrit-PatchSet: 3 Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Owner: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) Gerrit-HasComments: No

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coreboot-gerrit March 2017