coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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New patch to review for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit e66f2169f8cc2f8f977ed2265abde5fb3d615baf Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function has CAS and Frequency masks as inputs to support northbridges that have different limits on those. The CAS mask is used as defined in SPD and frequency mask is bitwise mask for supported frequency so e.g. : DDR2_200MH is (1 << 0), DDR2_266MHZ is (1 << 1), etc. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 86 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 15 +++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index b712192..f520904 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,6 +111,21 @@ static u8 spd_get_msbs(u8 c) } /** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_lsbs(u8 c) +{ + int i; + for (i = 0; i > 7; i++) + if (c & (1 << i)) + return i; + + return 0; +} + +/** * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -593,3 +609,73 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +int get_common_freq_cas(u8 freq_mask, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas) +{ + int i, found, high_supp_cas, low_supp_cas; + u8 curr_freq, curr_cas; + + const int ddr2_speeds_table[] = { + TCK_200MHZ, + TCK_266MHZ, + TCK_333MHZ, + TCK_400MHZ, + TCK_533MHZ, + TCK_666MHZ, + TCK_700MHZ, + TCK_800MHZ, + }; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i]->cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 1; + } + + high_supp_cas = spd_get_msbs(cas_mask); + low_supp_cas = spd_get_lsbs(cas_mask); + + /* Loop from fast to slow frequency, from low to high CAS latency */ + for (curr_freq = spd_get_msbs(freq_mask); + curr_freq >= spd_get_lsbs(freq_mask); curr_freq--) { + printram("Trying speed: %d\n", curr_freq); + for (curr_cas = low_supp_cas; + curr_cas <= low_supp_cas; curr_cas++) { + printram(" Trying CAS: %d\n"; curr_freq); + found = 1; + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == + SPD_DIMM_TYPE_UNDEFINED) + continue; + + printram(" Testing DIMM: %d\n", i); + if (dimm[i]->cycle_time[curr_cas] == 0) { + printram(" CAS not supported"); + found = 0; + break; + } + + if (dimm[i]->cycle_time[curr_cas] > + ddr2_speeds_table[curr_freq]) { + printram(" Timing too fast\n"); + found = 0; + break; + } + } + if (found) { + *selected_freq = curr_freq; + *selected_cas = curr_cas; + return 0; + } + } + } + + printk(BIOS_DEBUG, "No common CAS Frequency combination possible!\n"); + return 1; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 236be49..24d3379 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -46,6 +46,18 @@ #define TCK_333MHZ 768 #define TCK_266MHZ 960 #define TCK_200MHZ 1280 + +enum dram_freq { + DDR2_200MHZ, + DDR2_266MHZ, + DDR2_333MHZ, + DDR2_400MHZ, + DDR2_533MHZ, + DDR2_666MHZ, + DDR2_700MHZ, + DDR2_800MHZ, +}; + /** @} */ /** @@ -198,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +int get_common_freq_cas(u8 freq_mask, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

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Patch set updated for coreboot: soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18288 -gerrit commit 8295c60a15eb88b50035e243d6e072c8c66fc942 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Feb 3 19:05:27 2017 +0530 soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during coreboot MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/cpu.c | 24 ++++++++++++++++++++---- src/soc/intel/skylake/include/soc/msr.h | 5 +++++ 2 files changed, 25 insertions(+), 4 deletions(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 684680d..a3c4539 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -37,6 +37,7 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/smm.h> #include <soc/systemagent.h> @@ -351,6 +352,20 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } +/* + * The emulated ACPI timer allows disabling of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void configure_emulation_timer(void) +{ + msr_t msr; + + msr.hi = uCODE_TMR_EMULATION; + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + /* All CPUs including BSP will run the following function. */ static void cpu_core_init(device_t cpu) { @@ -367,6 +382,9 @@ static void cpu_core_init(device_t cpu) /* Configure Intel Speed Shift */ configure_isst(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ + configure_emulation_timer(); + /* Enable Direct Cache Access */ configure_dca_cap(); @@ -506,8 +524,6 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } -/* - * Do CPU MP Init before FSP Silicon Init - */ +/* Do CPU MP Init before FSP Silicon Init */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); \ No newline at end of file +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..405b13f 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -26,6 +26,11 @@ #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_EMULATE_PM_TIMER 0x121 +#define EMULATE_PM_TMR_EN (1 << 16) +#define uCODE_TMR_EMULATION 0x262E8B51 +#define EMULATE_DELAY_OFFSET_VALUE 20 +#define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57

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Patch set updated for coreboot: soc/intel/skylake: Perform CPU MP Init before FSP-S Init
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18287 -gerrit commit 72258324998c72b8562c8d007446ceecc1a9718c Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Feb 3 18:57:49 2017 +0530 soc/intel/skylake: Perform CPU MP Init before FSP-S Init As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Boot to OS with all threads enabled. Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/chip.c | 4 +-- src/soc/intel/skylake/chip_fsp20.c | 4 +-- src/soc/intel/skylake/cpu.c | 33 +++++++++++++++------- src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 3 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- 5 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c64a8df..060c4ee 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +49,7 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .init = &soc_init_cpus, + .init = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ebd3134..f1a32c4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,7 +59,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = &soc_init_cpus, + .init = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e8616f0..684680d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -397,13 +398,6 @@ static const struct cpu_driver driver __cpu_driver = { static const void *microcode_patch; static int ht_disabled; -static void pre_mp_init(void) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - static int get_cpu_count(void) { msr_t msr; @@ -463,7 +457,12 @@ static void post_mp_init(void) } static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = NULL, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, @@ -474,8 +473,9 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void soc_init_cpus(device_t dev) +static void soc_init_cpus(void *unused) { + device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct bus *cpu_bus = dev->link_list; if (mp_init_with_smm(cpu_bus, &mp_ops)) { @@ -486,6 +486,13 @@ void soc_init_cpus(device_t dev) configure_thermal_target(); } +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void soc_post_cpus_init(void *unused) +{ + if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); +} + int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) { msr_t msr; @@ -498,3 +505,9 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) msr = rdmsr(MTRR_CAP_MSR); return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } + +/* + * Do CPU MP Init before FSP Silicon Init + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); \ No newline at end of file diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index 8df7796..f1a9e53 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +29,6 @@ void soc_irq_settings(FSP_SIL_UPD *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); -void soc_init_cpus(device_t dev); const char *soc_acpi_name(struct device *dev); int init_igd_opregion(igd_opregion_t *igd_opregion); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 0ae87f4..136c4f2 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +29,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); -void soc_init_cpus(device_t dev); void soc_irq_settings(FSP_SIL_UPD *params); const char *soc_acpi_name(struct device *dev);

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Patch set updated for coreboot: soc/intel/skylake:[WIP] Add option to disable host reads to PMC XRAM
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18319 -gerrit commit fdf5429fadb1d975b729d468a9aa4f82f25d34db Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Feb 10 15:58:24 2017 +0530 soc/intel/skylake:[WIP] Add option to disable host reads to PMC XRAM FSP exposes a UPD to enable/disable host reads to PMC XRAM, mirror the same in skylake static.c to make it configurable from devicetree. Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 3 +++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 38d58c7..f4e4fe3 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -52,6 +52,9 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + #When set to true, this disallows host reads to PMC XRAM + register "PchPmPmcReadDisable" = "0" + register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1b69952..c69133b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -376,6 +376,9 @@ struct soc_intel_skylake_config { /* Enable/Disable VMX feature */ u8 VmxEnable; + /* When set to true, this disallows host reads to PMC XRAM */ + u8 PchPmPmcReadDisable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ebd3134..64db164 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -239,7 +239,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * 100b - VR specific command sent for MPS VR decay issue */ params->SendVrMbxCmd1 = config->SendVrMbxCmd; - + tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; soc_irq_settings(params); }

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New patch to review for coreboot: soc/intel/skylake: Add option to disable host reads to PMC XRAM
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18319 -gerrit commit b2f5e7b376a48ff2bfb04f9414595664cc616af9 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Feb 10 15:58:24 2017 +0530 soc/intel/skylake: Add option to disable host reads to PMC XRAM FSP exposes a UPD to enable/disable host reads to PMC XRAM, mirror the same in skylake static.c to make it configurable from devicetree. Change-Id: Iaa33aa3233bda4f050da37d1d8af0556311c9496 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 3 +++ src/soc/intel/skylake/chip.h | 3 +++ src/soc/intel/skylake/chip_fsp20.c | 2 +- 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 38d58c7..f4e4fe3 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -52,6 +52,9 @@ chip soc/intel/skylake register "PmConfigSlpAMinAssert" = "3" # 2s register "PmTimerDisabled" = "1" register "SendVrMbxCmd" = "1" # IMVP8 workaround + #When set to true, this disallows host reads to PMC XRAM + register "PchPmPmcReadDisable" = "0" + register "pirqa_routing" = "PCH_IRQ11" register "pirqb_routing" = "PCH_IRQ10" diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 1b69952..c69133b 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -376,6 +376,9 @@ struct soc_intel_skylake_config { /* Enable/Disable VMX feature */ u8 VmxEnable; + /* When set to true, this disallows host reads to PMC XRAM */ + u8 PchPmPmcReadDisable; + /* Statically clock gate 8254 PIT. */ u8 clock_gate_8254; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ebd3134..64db164 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -239,7 +239,7 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd) * 100b - VR specific command sent for MPS VR decay issue */ params->SendVrMbxCmd1 = config->SendVrMbxCmd; - + tconfig->PchPmPmcReadDisable = config->PchPmPmcReadDisable; soc_irq_settings(params); }

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Patch set updated for coreboot: mainboard/google/poppy: Enable Realtek 5663 support
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18216 -gerrit commit 87e9db7f8bb83a616cc19f9f0fd7eed23ad5fe31 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Tue Feb 7 21:11:45 2017 +0530 mainboard/google/poppy: Enable Realtek 5663 support Enable Realtek RT5663 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=With required driver support in kernel verify audio on headset Change-Id: I9b9eb1e7edca56870f5be0e4fd603c9b0dc7f9de Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/devicetree.cb | 8 ++++++++ 1 file changed, 8 insertions(+) diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index 88ee84f..38d58c7 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -231,6 +231,14 @@ chip soc/intel/skylake register "name" = ""MAXL"" device i2c 3A on end end + chip drivers/i2c/generic + register "hid" = ""10EC5663"" + register "name" = ""RT53"" + register "desc" = ""Realtek RT5663"" + register "irq" = "IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "probed" = "1" + device i2c 13 on end + end end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on

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Patch set updated for coreboot: mainboard/google/poppy: Enable Maxim 98927 codec
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18215 -gerrit commit b1ab81fa894ea2c0b66cd57fb9eac7d579102f6f Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:22:42 2017 +0530 mainboard/google/poppy: Enable Maxim 98927 codec Enable Maxim 98927 codec i2c device and add required SSDT parameters. BUG=None BRANCH=None TEST=with required driver support in kernel verfy audio on poppy on-board speakers. Change-Id: Id731de42d77204d59f32ac4c33a245837d6e2107 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/mainboard/google/poppy/Kconfig | 3 +++ src/mainboard/google/poppy/devicetree.cb | 17 ++++++++++++++++- 2 files changed, 19 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 7893482..13d61bd 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -20,6 +20,9 @@ config CHROMEOS config DRIVERS_I2C_GENERIC def_bool y +config DRIVERS_I2C_MAX98927 + def_bool y + config GBB_HWID string depends on CHROMEOS diff --git a/src/mainboard/google/poppy/devicetree.cb b/src/mainboard/google/poppy/devicetree.cb index a9e0cef..88ee84f 100644 --- a/src/mainboard/google/poppy/devicetree.cb +++ b/src/mainboard/google/poppy/devicetree.cb @@ -216,7 +216,22 @@ chip soc/intel/skylake device pci 16.4 off end # Management Engine Interface 3 device pci 17.0 off end # SATA device pci 19.0 on end # UART #2 - device pci 19.1 on end # I2C #5 + device pci 19.1 on + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "0" + register "desc" = ""SSM4567 Right Speaker Amp"" + register "name" = ""MAXR"" + device i2c 39 on end + end + chip drivers/i2c/max98927 + register "interleave_mode" = "1" + register "uid" = "1" + register "desc" = ""SSM4567 Left Speaker Amp"" + register "name" = ""MAXL"" + device i2c 3A on end + end + end # I2C #5 device pci 19.2 on end # I2C #4 device pci 1c.0 on chip drivers/intel/wifi

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Patch set updated for coreboot: mainboard/google/poppy: Generate required nhlt table
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18214 -gerrit commit 1badb306a25e0d88d06026e86f899da0ecf18ee6 Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:30:01 2017 +0530 mainboard/google/poppy: Generate required nhlt table poppy board uses Maxim 98927 speaker codec and Realtek RT5663 for heaset. Select the apropriate NHLT blobs to be packaged in CBFS. Also, generate the required ACPI NHLT table for codec and the supported topology in poppy. BUG=None BRANCH=None TEST=With the required driver support in kernel verify that the Audio plays on on-board speakers and headset, recording works from on-boards mics and headset mics. Change-Id: I98c65038b35fe99a661807de0766e6eac2c80eed Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 6 ++++ src/mainboard/google/poppy/mainboard.c | 53 ++++++++++++++++++++++++++++++++++ 2 files changed, 59 insertions(+) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index f1749e3..7893482 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -41,4 +41,10 @@ config MAX_CPUS int default 8 +config INCLUDE_NHLT_BLOBS + bool "Include blobs for audio." + select NHLT_DMIC_2CH + select NHLT_DMIC_4CH + select NHLT_RT5663 + select NHLT_MAX98927 endif diff --git a/src/mainboard/google/poppy/mainboard.c b/src/mainboard/google/poppy/mainboard.c index 29559b3..6931a30 100644 --- a/src/mainboard/google/poppy/mainboard.c +++ b/src/mainboard/google/poppy/mainboard.c @@ -14,19 +14,72 @@ */ #include <arch/acpi.h> +#include <console/console.h> #include <device/device.h> #include <ec/ec.h> #include <vendorcode/google/chromeos/chromeos.h> +#include <soc/nhlt.h> + +static const char *oem_id_maxim = "GOOGLE"; +static const char *oem_table_id_maxim = "POPPYMAX"; static void mainboard_init(device_t dev) { mainboard_ec_init(); } + +static unsigned long mainboard_write_acpi_tables(device_t device, + unsigned long current, acpi_rsdp_t *rsdp) +{ + uintptr_t start_addr; + uintptr_t end_addr; + struct nhlt *nhlt; + const char *oem_id = NULL; + const char *oem_table_id = NULL; + uint32_t oem_revision = 0; + + start_addr = current; + + nhlt = nhlt_init(); + + if (nhlt == NULL) + return start_addr; + + /* 2 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 2)) + printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n"); + + + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC arrays.\n"); + + /* MAXIM98927 Smart Amps for left and right channel */ + if (nhlt_soc_add_max98927(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add max98927\n"); + + /* RT5663 Headset codec. */ + if (nhlt_soc_add_rt5663(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add headset codec.\n"); + + oem_id = oem_id_maxim; + oem_table_id = oem_table_id_maxim; + + end_addr = nhlt_soc_serialize_oem_overrides(nhlt, start_addr, + oem_id, oem_table_id, oem_revision); + + if (end_addr != start_addr) + acpi_add_table(rsdp, (void *)start_addr); + + return end_addr; +} + static void mainboard_enable(device_t dev) { dev->ops->init = mainboard_init; dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator; + dev->ops->write_acpi_tables = mainboard_write_acpi_tables; } struct chip_operations mainboard_ops = {

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Patch set updated for coreboot: soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18213 -gerrit commit 718cc4ac48b97cac38765439e91479ffd120c74f Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Sat Jan 14 06:08:21 2017 +0530 soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support Add APIs and required parameters for creating Maxim 98927 and Realtek 5336 SSP endpoints in NHLT table. Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> --- src/soc/intel/skylake/Kconfig | 13 ++++++ src/soc/intel/skylake/include/soc/nhlt.h | 12 ++++++ src/soc/intel/skylake/nhlt/Makefile.inc | 19 ++++++++- src/soc/intel/skylake/nhlt/max98927.c | 47 +++++++++++++++++++++ src/soc/intel/skylake/nhlt/rt5663.c | 71 ++++++++++++++++++++++++++++++++ 5 files changed, 161 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 11953a6..489d976 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -59,6 +59,7 @@ config CPU_SPECIFIC_OPTIONS select TSC_CONSTANT_RATE select TSC_SYNC_MFENCE select UDELAY_TSC + select ACPI_NHLT config MAINBOARD_USES_FSP2_0 bool @@ -234,6 +235,18 @@ config NHLT_SSM4567 help Include DSP firmware settings for ssm4567 smart amplifier. +config NHLT_RT5663 + bool + default n + help + Include DSP firmware settings for rt5663 headset codec. + +config NHLT_MAX98927 + bool + default n + help + Include DSP firmware settings for max98927 amplifier. + config SKIP_FSP_CAR bool "Skip cache as RAM setup in FSP" default y diff --git a/src/soc/intel/skylake/include/soc/nhlt.h b/src/soc/intel/skylake/include/soc/nhlt.h index 008dd0d..3993003 100644 --- a/src/soc/intel/skylake/include/soc/nhlt.h +++ b/src/soc/intel/skylake/include/soc/nhlt.h @@ -60,4 +60,16 @@ int nhlt_soc_add_ssm4567(struct nhlt *nhlt, int hwlink); */ int nhlt_soc_add_max98357(struct nhlt *nhlt, int hwlink); +/* + * Add rt5663 headset codec on provided SSP link. Return 0 on success, < 0 + * on error. + */ +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink); + +/* + * Add max98927 amplifier in stereo configuration on provided SSP link. + * Return 0 on success, < 0 on error. + */ +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink); + #endif diff --git a/src/soc/intel/skylake/nhlt/Makefile.inc b/src/soc/intel/skylake/nhlt/Makefile.inc index e022482..743a931 100644 --- a/src/soc/intel/skylake/nhlt/Makefile.inc +++ b/src/soc/intel/skylake/nhlt/Makefile.inc @@ -2,9 +2,16 @@ ramstage-y += dmic.c ramstage-y += nau88l25.c ramstage-y += max98357.c ramstage-y += ssm4567.c +ramstage-y += rt5663.c +ramstage-y += max98927.c # DSP firmware settings files. -NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake +ifeq ($(CONFIG_SOC_INTEL_KABYLAKE),y) +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/kabylake/nhlt-blobs +else +NHLT_BLOB_PATH = 3rdparty/blobs/soc/intel/skylake/nhlt-blobs +endif + DMIC_2CH_48KHZ_16B = dmic-2ch-48khz-16b.bin DMIC_2CH_48KHZ_32B = dmic-2ch-48khz-32b.bin DMIC_4CH_48KHZ_16B = dmic-4ch-48khz-16b.bin @@ -13,6 +20,8 @@ NAU88L25 = nau88l25-2ch-48khz-24b.bin MAX98357_RENDER = max98357-render-2ch-48khz-24b.bin SSM4567_RENDER = ssm4567-render-2ch-48khz-24b.bin SSM4567_CAPTURE = ssm4567-capture-4ch-48khz-32b.bin +RT5663 = rt5663-2ch-48khz-24b.bin +MAX98927_RENDER = max98927-render-2ch-48khz-24b.bin cbfs-files-$(CONFIG_NHLT_DMIC_2CH) += $(DMIC_2CH_48KHZ_16B) $(DMIC_2CH_48KHZ_16B)-file := $(NHLT_BLOB_PATH)/$(DMIC_2CH_48KHZ_16B) @@ -45,3 +54,11 @@ $(SSM4567_RENDER)-type := raw cbfs-files-$(CONFIG_NHLT_SSM4567) += $(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-file := $(NHLT_BLOB_PATH)/$(SSM4567_CAPTURE) $(SSM4567_CAPTURE)-type := raw + +cbfs-files-$(CONFIG_NHLT_RT5663) += $(RT5663) +$(RT5663)-file := $(NHLT_BLOB_PATH)/$(RT5663) +$(RT5663)-type := raw + +cbfs-files-$(CONFIG_NHLT_MAX98927) += $(MAX98927_RENDER) +$(MAX98927_RENDER)-file := $(NHLT_BLOB_PATH)/$(MAX98927_RENDER) +$(MAX98927_RENDER)-type := raw diff --git a/src/soc/intel/skylake/nhlt/max98927.c b/src/soc/intel/skylake/nhlt/max98927.c new file mode 100644 index 0000000..77b72aa --- /dev/null +++ b/src/soc/intel/skylake/nhlt/max98927.c @@ -0,0 +1,47 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +static const struct nhlt_format_config max98927_render_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "max98927-render-2ch-48khz-24b.bin", + }, +}; + +static const struct nhlt_endp_descriptor max98927_descriptors[] = { + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .formats = max98927_render_formats, + .num_formats = ARRAY_SIZE(max98927_render_formats), + }, +}; + +int nhlt_soc_add_max98927(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, max98927_descriptors, + ARRAY_SIZE(max98927_descriptors)); +} diff --git a/src/soc/intel/skylake/nhlt/rt5663.c b/src/soc/intel/skylake/nhlt/rt5663.c new file mode 100644 index 0000000..ab361de --- /dev/null +++ b/src/soc/intel/skylake/nhlt/rt5663.c @@ -0,0 +1,71 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/nhlt.h> + +/* The same DSP firmware settings are used for both the capture and + * render endpoints. */ +static const struct nhlt_format_config rt5663_formats[] = { + /* 48 KHz 24-bits per sample. */ + { + .num_channels = 2, + .sample_freq_khz = 48, + .container_bits_per_sample = 32, + .valid_bits_per_sample = 24, + .speaker_mask = SPEAKER_FRONT_LEFT | SPEAKER_FRONT_RIGHT, + .settings_file = "rt5663-2ch-48khz-24b.bin", + }, +}; + +/* The rt5663 just has headphones and a mic. Both the capture and render + * endpoints occupy the same virtual slot. */ +static const struct nhlt_tdm_config tdm_config = { + .virtual_slot = 0, + .config_type = NHLT_TDM_BASIC, +}; + +static const struct nhlt_endp_descriptor rt5663_descriptors[] = { + /* Render Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_RENDER, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, + /* Capture Endpoint */ + { + .link = NHLT_LINK_SSP, + .device = NHLT_SSP_DEV_I2S, + .direction = NHLT_DIR_CAPTURE, + .vid = NHLT_VID, + .did = NHLT_DID_SSP, + .cfg = &tdm_config, + .cfg_size = sizeof(tdm_config), + .formats = rt5663_formats, + .num_formats = ARRAY_SIZE(rt5663_formats), + }, +}; + +int nhlt_soc_add_rt5663(struct nhlt *nhlt, int hwlink) +{ + /* Virtual bus id of SSP links are the hardware port ids proper. */ + return nhlt_add_ssp_endpoints(nhlt, hwlink, rt5663_descriptors, + ARRAY_SIZE(rt5663_descriptors)); +}

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Patch set updated for coreboot: driver/i2c/max98927: add i2c driver for Maxim 98927 codec
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18211 -gerrit commit fea57bfe71bffb02c79590a943e6319dd606436a Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Fri Jan 13 22:17:01 2017 +0530 driver/i2c/max98927: add i2c driver for Maxim 98927 codec Maxim 98927 kernel driver requires entries in the ACPI SSDT table, add a SSDT generator as part of this driver. BUG=None BRANCH=None TEST=After boot, dump and verify that the generated SSDT ACPI table has the required entries. Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com> Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Signed-off-by: M Naveen <naveen.m(a)intel.com> Signed-off-by: Dylan Reid <dgreid(a)chromium.org> --- src/drivers/i2c/max98927/Kconfig | 2 + src/drivers/i2c/max98927/Makefile.inc | 1 + src/drivers/i2c/max98927/chip.h | 30 ++++++++++ src/drivers/i2c/max98927/max98927.c | 108 ++++++++++++++++++++++++++++++++++ 4 files changed, 141 insertions(+) diff --git a/src/drivers/i2c/max98927/Kconfig b/src/drivers/i2c/max98927/Kconfig new file mode 100644 index 0000000..1007442 --- /dev/null +++ b/src/drivers/i2c/max98927/Kconfig @@ -0,0 +1,2 @@ +config DRIVERS_I2C_MAX98927 + bool diff --git a/src/drivers/i2c/max98927/Makefile.inc b/src/drivers/i2c/max98927/Makefile.inc new file mode 100644 index 0000000..3bafee1 --- /dev/null +++ b/src/drivers/i2c/max98927/Makefile.inc @@ -0,0 +1 @@ +ramstage-$(CONFIG_DRIVERS_I2C_MAX98927) += max98927.c diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h new file mode 100644 index 0000000..d63244f --- /dev/null +++ b/src/drivers/i2c/max98927/chip.h @@ -0,0 +1,30 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corp. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * Maxim MAX98927 audio codec devicetree bindings + */ +struct drivers_i2c_max98927_config { + /* I2C Bus Frequency in Hertz (default 400kHz) */ + unsigned int bus_speed; + /* Set ‘1’ if I2S channel size is not 32bit. */ + unsigned int interleave_mode; + /*Identifier for chips*/ + unsigned int uid; + /* Device Description */ + const char *desc; + /* ACPI Device Name */ + const char *name; +}; diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c new file mode 100644 index 0000000..1f5fabf --- /dev/null +++ b/src/drivers/i2c/max98927/max98927.c @@ -0,0 +1,108 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/acpi.h> +#include <arch/acpi_device.h> +#include <arch/acpigen.h> +#include <console/console.h> +#include <device/i2c.h> +#include <device/device.h> +#include <device/path.h> +#include <stdint.h> +#include <string.h> +#include "chip.h" + +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + +#define MAX98927_ACPI_NAME "MAXI" +#define MAX98927_ACPI_HID "MX98927" + +#define MAX98927_DP_INT(key, val) \ + acpi_dp_add_integer(dp, "maxim," key, (val)) + +static void max98927_fill_ssdt(struct device *dev) +{ + struct drivers_i2c_max98927_config *config = dev->chip_info; + const char *scope = acpi_device_scope(dev); + struct acpi_i2c i2c = { + .address = dev->path.i2c.device, + .mode_10bit = dev->path.i2c.mode_10bit, + .speed = config->bus_speed ? : I2C_SPEED_FAST, + .resource = scope, + }; + struct acpi_dp *dp = NULL; + + if (!dev->enabled || !scope) + return; + + /* Device */ + acpigen_write_scope(scope); + acpigen_write_device(acpi_device_name(dev)); + acpigen_write_name_string("_HID", MAX98927_ACPI_HID); + acpigen_write_name_integer("_UID", config->uid); + acpigen_write_name_string("_DDN", config->desc); + acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON); + + /* Resources */ + acpigen_write_name("_CRS"); + acpigen_write_resourcetemplate_header(); + acpi_device_write_i2c(&i2c); + acpigen_write_resourcetemplate_footer(); + + /* Device Properties */ + dp = acpi_dp_new_table("_DSD"); + + acpi_dp_add_integer(dp, "interleave_mode", config->interleave_mode); + + acpi_dp_write(dp); + + acpigen_pop_len(); /* Device */ + acpigen_pop_len(); /* Scope */ + + printk(BIOS_INFO, "%s: %s address 0%xh\n", + acpi_device_path(dev), dev->chip_ops->name, + dev->path.i2c.device); +} + +static const char *max98927_acpi_name(struct device *dev) +{ + struct drivers_i2c_max98927_config *config = dev->chip_info; + + if (config->name) + return config->name; + + return MAX98927_ACPI_NAME; +} +#endif + +static struct device_operations max98927_ops = { + .read_resources = DEVICE_NOOP, + .set_resources = DEVICE_NOOP, + .enable_resources = DEVICE_NOOP, +#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) + .acpi_name = &max98927_acpi_name, + .acpi_fill_ssdt_generator = &max98927_fill_ssdt, +#endif +}; + +static void max98927_enable(struct device *dev) +{ + dev->ops = &max98927_ops; +} + +struct chip_operations drivers_i2c_max98927_ops = { + CHIP_NAME("Maxim MAX98927 Codec") + .enable_dev = &max98927_enable +};

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coreboot-gerrit February 2017