coreboot-gerrit February 2017

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Patch set updated for coreboot: device/dram/ddr2: Add common ddr2 spd decoder
by Patrick Rudolph 10 Feb '17

10 Feb '17

Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18273 -gerrit commit 704a23101461d4ef6203b54160b18b5cdafff8b9 Author: Patrick Rudolph <siro(a)das-labor.org> Date: Tue Jan 31 19:43:17 2017 +0100 device/dram/ddr2: Add common ddr2 spd decoder Decode DDR2 SPD similar to DDR3 SPD decoder to ease readability, reduce code complexity and reduce size of maintainable code. Change-Id: I741f0e61ab23e3999ae9e31f57228ba034c2509e Signed-off-by: Patrick Rudolph <siro(a)das-labor.org> --- src/device/Kconfig | 4 + src/device/dram/Makefile.inc | 1 + src/device/dram/ddr2.c | 599 +++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 205 ++++++++++++++ 4 files changed, 809 insertions(+) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..7e8e50f 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -214,6 +214,10 @@ config SPD_CACHE bool default n +config SPD_DDR2 + bool + default n + config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..9b0016a 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1,2 @@ romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-$(CONFIG_SPD_DDR2) += ddr2.c diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c new file mode 100644 index 0000000..4224d6e --- /dev/null +++ b/src/device/dram/ddr2.c @@ -0,0 +1,599 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/** + * @file ddr2.c + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/dram/ddr2.h> +#include <string.h> + +/*============================================================================== + * = DDR2 SPD decoding helpers + *----------------------------------------------------------------------------*/ + +/** + * \brief Checks if the DIMM is Registered based on byte[20] of the SPD + * + * Tells if the DIMM type is registered or not. + * + * @param type DIMM type. This is byte[20] of the SPD. + */ +int dimm_is_registered(enum spd_dimm_type type) +{ + if ((type == SPD_DIMM_TYPE_RDIMM) + | (type == SPD_DIMM_TYPE_72B_SO_RDIMM)) + return 1; + + return 0; +} + +/** + * \brief Calculate the checksum of a DDR2 SPD unique identifier + * + * @param spd pointer to raw SPD data + * @param len length of data in SPD + * + * @return the checksum of SPD data bytes 63, or 0 when spd data is truncated. + */ +u8 spd_ddr2_calc_checksum(u8 *spd, int len) +{ + int i; + u8 c = 0; + + if (len < 63) + /* Not enough bytes available to get the checksum */ + return 0; + + for (i = 0; i < 63; i++) + c += spd[i]; + + return c; +} + +/** + * \brief Return size of SPD. + * + * Returns size of SPD. Usually 128 Byte. + */ +u32 spd_decode_spd_size_ddr2(u8 byte0) +{ + return byte0; +} + +/** + * \brief Return size of eeprom. + * + * Returns size of eeprom. Usually 256 Byte. + */ +u32 spd_decode_eeprom_size_ddr2(u8 byte1) +{ + if (!byte1) + return 0; + + if (byte1 > 0x0e) + return 0x3fff; + + return 1 << byte1; +} + +/** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_msbs(u8 c) +{ + int i; + for (i = 7; i >= 0; i--) + if (c & (1 << i)) + return i; + + return 0; +} + +/** + * \brief Decode SPD tck cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_tck_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + + switch (c & 0xf) { + case 0xa: + low = 25; + break; + case 0xb: + low = 33; + break; + case 0xc: + low = 66; + break; + case 0xd: + low = 75; + break; + default: + low = (c & 0xf) * 10; + } + + return ((high * 100 + low) << 8) / 100; +} + +/** + * \brief Decode SPD bcd style timings + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_bcd_time(u8 c) +{ + u8 high, low; + + high = c >> 4; + low = c & 0xf; + + return ((high * 10 + low) << 8) / 100; +} + +/** + * \brief Decode SPD tRP, tRRP cycle time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th ns. + */ +static u32 spd_decode_quarter_time(u8 c) +{ + u8 high, low; + + high = c >> 2; + low = 25 * (c & 0x3); + + return ((high * 100 + low) << 8) / 100; +} + +/** + * \brief Decode SPD tRR time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static u32 spd_decode_tRR_time(u8 c) +{ + switch (c) { + default: + case 0: + return 15625 << 8; + case 1: + return 15625 << 6; + case 2: + return 15625 << 7; + case 3: + return 15625 << 9; + case 4: + return 15625 << 10; + case 5: + return 15625 << 11; + } +} + +/** + * \brief Decode SPD tRC,tRFC time + * + * Decodes a raw SPD data from a DDR2 DIMM. + * Returns cycle time in 1/256th us. + */ +static void spd_decode_tRCtRFC_time(u8 *spd_40_41_42, u32 *tRC, u32 *tRFC) +{ + u8 b40, b41, b42; + + b40 = spd_40_41_42[0]; + b41 = spd_40_41_42[1]; + b42 = spd_40_41_42[2]; + + *tRC = b41 * 100; + *tRFC = b42 * 100; + + if (b40 & 0x01) + *tRFC += 256 * 100; + + switch ((b40 >> 1) & 0x07) { + case 1: + *tRFC += 25; + break; + case 2: + *tRFC += 33; + break; + case 3: + *tRFC += 50; + break; + case 4: + *tRFC += 66; + break; + case 5: + *tRFC += 75; + break; + default: + break; + } + + switch ((b40 >> 4) & 0x07) { + case 1: + *tRC += 25; + break; + case 2: + *tRC += 33; + break; + case 3: + *tRC += 50; + break; + case 4: + *tRC += 66; + break; + case 5: + *tRC += 75; + break; + default: + break; + } + + /* Convert to 1/256th us */ + *tRC = (*tRC << 8) / 100; + *tRFC = (*tRFC << 8) / 100; +} + +/** + * \brief Decode the raw SPD data + * + * Decodes a raw SPD data from a DDR2 DIMM, and organizes it into a + * @ref dimm_attr structure. The SPD data must first be read in a contiguous + * array, and passed to this function. + * + * @param dimm pointer to @ref dimm_attr structure where the decoded data is to + * be stored + * @param spd array of raw data previously read from the SPD. + * + * @return @ref spd_status enumerator + * SPD_STATUS_OK -- decoding was successful + * SPD_STATUS_INVALID -- invalid SPD or not a DDR2 SPD + * SPD_STATUS_CRC_ERROR -- CRC did not verify + * SPD_STATUS_INVALID_FIELD -- A field with an invalid value was + * detected. + */ +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd) +{ + int ret; + u16 eeprom_size; + u8 spd_size; + u8 cl; + u8 reg8; + + memset(dimm, 0, sizeof(*dimm)); + + spd_size = spd_decode_spd_size_ddr2(spd[0]); + eeprom_size = spd_decode_eeprom_size_ddr2(spd[1]); + + printram("EEPROM with 0x%04x bytes\n", eeprom_size); + printram("SPD contains 0x%02x bytes\n", spd_size); + + if (spd_size < 64 || eeprom_size < 64) { + printram("ERROR: SPD to small\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + if (spd_ddr2_calc_checksum(spd, spd_size) != spd[63]) { + printram("ERROR: SPD checksum error\n"); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + + reg8 = spd[62]; + if ((reg8 & 0xf0) != 0x10) { + printram("ERROR: Unsupported SPD revision %01x.%01x\n", + reg8 >> 4, reg8 & 0xf); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Revision : %01x.%01x\n", reg8 >> 4, reg8 & 0xf); + + reg8 = spd[2]; + if (reg8 != 0x08) { + printram("ERROR: Unsupported SPD type %x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_UNDEFINED; + return SPD_STATUS_INVALID; + } + printram(" Type : 0x%02x\n", reg8); + dimm->dram_type = SPD_MEMORY_TYPE_SDRAM_DDR2; + + dimm->row_bits = spd[3]; + if (dimm->row_bits > 31) { + printram(" Invalid number of memory rows\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Rows : %u\n", dimm->row_bits); + + dimm->col_bits = spd[4]; + if (dimm->col_bits > 16) { + printram(" Invalid number of memory columns\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Columns : %u\n", dimm->col_bits); + + dimm->ranks = (spd[5] & 0x7) + 1; + printram(" Ranks : %u\n", dimm->ranks); + + dimm->mod_width = spd[6]; + printram(" Module width : x%u\n", dimm->mod_width); + + dimm->width = spd[13]; + printram(" Width : x%u\n", dimm->width); + + dimm->banks = spd[17]; + printram(" Banks : %u\n", dimm->banks); + + switch (spd[8]) { + case 0: + dimm->flags.operable_5_00V = 1; + printram(" Voltage : 5.0V\n"); + break; + case 1: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 2: + dimm->flags.operable_1_50V = 1; + printram(" Voltage : 1.5V\n"); + break; + case 3: + dimm->flags.operable_3_33V = 1; + printram(" Voltage : 3.3V\n"); + break; + case 4: + dimm->flags.operable_2_50V = 1; + printram(" Voltage : 2.5V\n"); + break; + case 5: + dimm->flags.operable_1_80V = 1; + printram(" Voltage : 1.8V\n"); + break; + default: + printram(" Unknown voltage level.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + + dimm->cas_supported = spd[18]; + if (dimm->cas_supported & 0x3) { + printram(" Invalid CAS support advertised.\n"); + ret = SPD_STATUS_INVALID_FIELD; + } + printram(" Supported CAS mask : 0x%x\n", dimm->cas_supported); + + /* CL=X */ + cl = spd_get_msbs(dimm->cas_supported); + + /* SDRAM Cycle time at Maximum Supported CAS Latency (CL), CL=X */ + dimm->cycle_time[cl] = spd_decode_tck_time(spd[9]); + /* SDRAM Access from Clock */ + dimm->access_time[cl] = spd_decode_bcd_time(spd[10]); + + if (dimm->cas_supported & (1 << (cl - 1))) { + /* Minimum Clock Cycle at CLX-1 */ + dimm->cycle_time[cl - 1] = spd_decode_tck_time(spd[23]); + /* Maximum Data Access Time (tAC) from Clock at CLX-1 */ + dimm->access_time[cl - 1] = spd_decode_bcd_time(spd[24]); + } + if (dimm->cas_supported & (1 << (cl - 2))) { + /* Minimum Clock Cycle at CLX-2 */ + dimm->cycle_time[cl - 2] = spd_decode_tck_time(spd[25]); + /* Maximum Data Access Time (tAC) from Clock at CLX-2 */ + dimm->access_time[cl - 2] = spd_decode_bcd_time(spd[26]); + } + + /* Module Rank Density */ + reg8 = (spd[31] >> 5) | (spd[31] << 3); + /* Module density */ + dimm->size_mb = 128 * reg8 * dimm->ranks; + if (dimm->size_mb < 1024) + printram(" Capacity : %u MB\n", dimm->size_mb); + else + printram(" Capacity : %u GB\n", dimm->size_mb >> 10); + + /* SDRAM Maximum Cycle Time (tCKmax) */ + dimm->tCK = spd_decode_tck_time(spd[43]); + /* Minimum Write Recovery Time (tWRmin) */ + dimm->tWR = spd_decode_quarter_time(spd[36]); + /* Minimum RAS# to CAS# Delay Time (tRCDmin) */ + dimm->tRCD = spd_decode_quarter_time(spd[29]); + /* Minimum Row Active to Row Active Delay Time (tRRDmin) */ + dimm->tRRD = spd_decode_quarter_time(spd[28]); + /* Minimum Row Precharge Delay Time (tRPmin) */ + dimm->tRP = spd_decode_quarter_time(spd[27]); + /* Minimum Active to Precharge Delay Time (tRASmin) */ + dimm->tRAS = spd[30] << 8; + /* Minimum Active to Active/Refresh Delay Time (tRCmin) */ + /* Minimum Refresh Recovery Delay Time (tRFCmin) */ + spd_decode_tRCtRFC_time(&spd[40], &dimm->tRC, &dimm->tRFC); + /* Minimum Internal Write to Read Command Delay Time (tWTRmin) */ + dimm->tWTR = spd_decode_quarter_time(spd[37]); + /* Minimum Internal Read to Precharge Command Delay Time (tRTPmin) */ + dimm->tRTP = spd_decode_quarter_time(spd[38]); + /* Data Input Setup Time Before Strobe */ + dimm->tDS = spd_decode_bcd_time(spd[34]); + /* Data Input Hold Time After Strobe */ + dimm->tDH = spd_decode_bcd_time(spd[35]); + /* SDRAM Device DQS-DQ Skew for DQS and associated DQ signals */ + dimm->tDQSQ = (spd[44] << 8) / 100; + /* SDRAM Device Maximum Read Data Hold Skew Factor */ + dimm->tQHS = (spd[45] << 8) / 100; + /* PLL Relock Time in us */ + dimm->tPLL = spd[46] << 8; + /* Refresh rate in us */ + dimm->tRR = spd_decode_tRR_time(spd[12]); + + /* Number of PLLs on DIMM */ + dimm->plls = (spd[21] >> 2) & 0x3; + + /* SDRAM Thermal and Refresh Options */ + printram(" General features :"); + if (spd[22] & 0x04) { + dimm->flags.pasr = 1; + printram(" PASR"); + } + if (spd[22] & 0x02) { + dimm->flags.terminate_50ohms = 1; + printram(" 50Ohm"); + } + if (spd[22] & 0x01) { + dimm->flags.weak_driver = 1; + printram(" WEAK_DRIVER"); + } + printram("\n"); + + /* SDRAM Supported Burst length */ + printram(" Burst length :"); + if (spd[16] & 0x06) { + dimm->flags.bl8 = 1; + printram(" BL8"); + } + if (spd[22] & 0x04) { + dimm->flags.bl4 = 1; + printram(" BL4"); + } + printram("\n"); + + dimm->dimm_type = spd[20] & SPD_DIMM_TYPE_MASK; + printram(" Dimm type : %x\n", dimm->dimm_type); + + dimm->flags.is_ecc = !!(spd[11] & 0x3); + printram(" ECC support : %x\n", dimm->flags.is_ecc); + + dimm->flags.stacked = !!(spd[5] & 0x10); + printram(" Package : %s\n", + dimm->flags.stacked ? "stack" : "planar"); + + if (spd_size > 71) { + memcpy(&dimm->manufacturer_id, &spd[64], 4); + printram(" Manufacturer ID : %x\n", dimm->manufacturer_id); + } + + if (spd_size > 90) { + dimm->part_number[16] = 0; + memcpy(dimm->part_number, &spd[73], 16); + printram(" Part number : %s\n", dimm->part_number); + } + + return ret; +} + +/* + * The information printed below has a more informational character, and is not + * necessarily tied in to RAM init debugging. Hence, we stop using printram(), + * and use the standard printk()'s below. + */ + +static void print_ns(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u ns\n", msg, mant, fp); +} + +static void print_us(const char *msg, u32 val) +{ + u32 mant, fp; + mant = val / 256; + fp = (val % 256) * 1000 / 256; + + printk(BIOS_INFO, "%s%3u.%.3u us\n", msg, mant, fp); +} + +/** +* \brief Print the info in DIMM +* +* Print info about the DIMM. Useful to use when CONFIG_DEBUG_RAM_SETUP is +* selected, or for a purely informative output. +* +* @param dimm pointer to already decoded @ref dimm_attr structure +*/ +void dram_print_spd_ddr2(const dimm_attr *dimm) +{ + u8 val8, cl; + char buf[32]; + int i; + + printk(BIOS_INFO, " Row addr bits : %u\n", dimm->row_bits); + printk(BIOS_INFO, " Column addr bits : %u\n", dimm->col_bits); + printk(BIOS_INFO, " Number of ranks : %u\n", dimm->ranks); + printk(BIOS_INFO, " DIMM Capacity : %u MB\n", dimm->size_mb); + printk(BIOS_INFO, " Width : x%u\n", dimm->width); + printk(BIOS_INFO, " Banks : %u\n", dimm->banks); + + /* CAS Latencies Supported */ + val8 = dimm->cas_supported; + printk(BIOS_INFO, " CAS latencies :"); + i = 0; + cl = 0; + do { + if (val8 & 1) { + printk(BIOS_INFO, " %u", i); + cl = i; + } + i++; + val8 >>= 1; + } while (val8); + printk(BIOS_INFO, "\n"); + + for (i = cl - 2; i <= cl; i++) { + if (i < 0) + continue; + strcpy(buf, " tCK at CLx : "); + /* Simple snprintf replacement */ + buf[11] = '0' + i; + print_ns(buf, dimm->cycle_time[i]); + + strcpy(buf, " tAC at CLx : "); + /* Simple snprintf replacement */ + buf[11] = '0' + i; + print_ns(buf, dimm->access_time[i]); + } + print_ns(" tCKmax : ", dimm->tCK); + print_ns(" tWRmin : ", dimm->tWR); + print_ns(" tRCDmin : ", dimm->tRCD); + print_ns(" tRRDmin : ", dimm->tRRD); + print_ns(" tRPmin : ", dimm->tRP); + print_ns(" tRASmin : ", dimm->tRAS); + print_ns(" tRCmin : ", dimm->tRC); + print_ns(" tRFCmin : ", dimm->tRFC); + print_ns(" tWTRmin : ", dimm->tWTR); + print_ns(" tRTPmin : ", dimm->tRTP); + print_ns(" tDS : ", dimm->tDS); + print_ns(" tDH : ", dimm->tDH); + print_ns(" tDQSQmax : ", dimm->tDQSQ); + print_ns(" tQHSmax : ", dimm->tQHS); + print_us(" tPLL : ", dimm->tPLL); + print_us(" tRR : ", dimm->tRR); +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h new file mode 100644 index 0000000..a7b3ad9 --- /dev/null +++ b/src/include/device/dram/ddr2.h @@ -0,0 +1,205 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * + * This program is free software: you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation, either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +/* + * JEDEC Standard No. 21-C + * Annex J: Annex J: Serial Presence Detects for DDR2 SDRAM (Revision 1.3) + */ + +#ifndef DEVICE_DRAM_DDR2L_H +#define DEVICE_DRAM_DDR2L_H + +/** + * @file ddr2.h + * + * \brief Utilities for decoding DDR2 SPDs + */ + +#include <stdint.h> +#include <spd.h> + +/** + * \brief Convenience definitions for TCK values + * + * Different values for tCK, representing standard DDR2 frequencies. + * These values are in 1/256 ns units. + * @{ + */ +#define TCK_800MHZ 320 +#define TCK_700MHZ 365 +#define TCK_666MHZ 384 +#define TCK_533MHZ 480 +#define TCK_400MHZ 640 +#define TCK_333MHZ 768 +#define TCK_266MHZ 960 +#define TCK_200MHZ 1280 +/** @} */ + +/** + * \brief Convenience macro for enabling printk with CONFIG_DEBUG_RAM_SETUP + * + * Use this macro instead of printk(); for verbose RAM initialization messages. + * When CONFIG_DEBUG_RAM_SETUP is not selected, these messages are automatically + * disabled. + * @{ + */ +#if IS_ENABLED(CONFIG_DEBUG_RAM_SETUP) +#define printram(x, ...) printk(BIOS_DEBUG, x, ##__VA_ARGS__) +#else +#define printram(x, ...) +#endif +/** @} */ + +/* + * Module type (byte 20, bits 5:0) of SPD + * This definition is specific to DDR2. DDR3 SPDs have a different structure. + */ +enum spd_dimm_type { + SPD_DIMM_TYPE_UNDEFINED = 0x00, + SPD_DIMM_TYPE_RDIMM = 0x01, + SPD_DIMM_TYPE_UDIMM = 0x02, + SPD_DIMM_TYPE_SO_DIMM = 0x04, + SPD_DIMM_TYPE_72B_SO_CDIMM = 0x06, + SPD_DIMM_TYPE_72B_SO_RDIMM = 0x07, + SPD_DIMM_TYPE_MICRO_DIMM = 0x08, + SPD_DIMM_TYPE_MINI_DIMM = 0x10, + SPD_DIMM_TYPE_MINI_UDIMM = 0x20, + /* Masks to bits 5:0 to give the dimm type */ + SPD_DIMM_TYPE_MASK = 0x3f, +}; + +/** + * \brief DIMM flags + * + * Characteristic flags for the DIMM, as presented by the SPD + */ +typedef union dimm_flags_st { + /* The whole point of the union/struct construct is to allow us to clear + * all the bits with one line: flags.raw = 0. + * We do not care how these bits are ordered */ + struct { + /* Module can work at 5.00V */ + unsigned operable_5_00V:1; + /* Module can work at 3.33V */ + unsigned operable_3_33V:1; + /* Module can work at 2.50V */ + unsigned operable_2_50V:1; + /* Module can work at 1.80V - All DIMMS must be 1.8V operable */ + unsigned operable_1_80V:1; + /* Module can work at 1.50V */ + unsigned operable_1_50V:1; + /* Module can work at 1.35V */ + unsigned operable_1_35V:1; + /* Module can work at 1.20V */ + unsigned operable_1_25V:1; + /* Has an 8-bit bus extension, meaning the DIMM supports ECC */ + unsigned is_ecc:1; + /* Supports weak driver */ + unsigned weak_driver:1; + /* Supports terminating at 50 Ohm */ + unsigned terminate_50ohms:1; + /* Partial Array Self Refresh */ + unsigned pasr:1; + /* Supports burst length 8 */ + unsigned bl8:1; + /* Supports burst length 4 */ + unsigned bl4:1; + /* DIMM Package is stack */ + unsigned stacked:1; + }; + unsigned int raw; +} dimm_flags_t; + +/** + * \brief DIMM characteristics + * + * The characteristics of each DIMM, as presented by the SPD + */ +typedef struct dimm_attr_st { + enum spd_memory_type dram_type; + enum spd_dimm_type dimm_type; + u8 cas_supported; + + /* Maximum cloclk to data cycle times for various CAS */ + u32 cycle_time[8]; + /* Maximum data access times for various CAS */ + u32 access_time[8]; + /* Flags extracted from SPD */ + dimm_flags_t flags; + /* Number of banks */ + u8 banks; + /* SDRAM width */ + u8 width; + /* Module width */ + u8 mod_width; + /* Number of ranks */ + u8 ranks; + /* Number or row address bits */ + u8 row_bits; + /* Number or column address bits */ + u8 col_bits; + /* Number of PLLs on module */ + u8 plls; + /* Size of module in MiB */ + u32 size_mb; + /* Latencies are in units of 1/256 ns */ + u32 tCK; + u32 tWR; + u32 tRCD; + u32 tRRD; + u32 tRP; + u32 tRAS; + u32 tIS; + u32 tIH; + u32 tDS; + u32 tDH; + + u32 tRC; + u32 tRFC; + u32 tWTR; + u32 tRTP; + u32 tDQSQ; + u32 tQHS; + + /* Latencies are in units of 1/256 us */ + u32 tPLL; + u32 tRR; + + /* Manufacturer ID */ + u32 manufacturer_id; // + /* ASCII part number - NULL terminated */ + u8 part_number[17]; +} dimm_attr; + +/** Result of the SPD decoding process */ +enum spd_status { + SPD_STATUS_OK = 0, + SPD_STATUS_INVALID, + SPD_STATUS_CRC_ERROR, + SPD_STATUS_INVALID_FIELD, +}; + +typedef u8 spd_raw_data[128]; + +int dimm_is_registered(enum spd_dimm_type type); +u8 spd_ddr2_calc_checksum(u8 *spd, int len); +u32 spd_decode_spd_size_ddr2(u8 byte0); +u32 spd_decode_eeprom_size_ddr2(u8 byte1); +int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); +void dram_print_spd_ddr2(const dimm_attr *dimm); + + +#endif /* DEVICE_DRAM_DDR2L_H */

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Patch set updated for coreboot: ddr3 spd: move accessor code into lib/spd_bin.c
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18265 -gerrit commit 47fb4edfddc1061ddc6cd6a0ab40dcabcb8edbf8 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:59:25 2017 +0100 ddr3 spd: move accessor code into lib/spd_bin.c It's an attempt to consolidate the access code, even if there are still multiple implementations in the code. Change-Id: I4b2b9cbc24a445f8fa4e0148f52fd15950535240 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/Kconfig | 4 -- src/device/dram/Makefile.inc | 2 +- src/device/dram/spd_cache.c | 67 ----------------------------- src/include/spd_bin.h | 3 ++ src/include/spd_cache.h | 26 ----------- src/lib/Makefile.inc | 4 +- src/lib/spd_bin.c | 44 +++++++++++++++++++ src/mainboard/amd/db-ft3b-lc/Kconfig | 1 - src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e20XX/Kconfig | 1 - src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/Kconfig | 1 - src/mainboard/gizmosphere/gizmo/Kconfig | 1 - src/mainboard/gizmosphere/gizmo2/Kconfig | 1 - src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/Kconfig | 1 - src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/Kconfig | 1 - src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 20 files changed, 56 insertions(+), 113 deletions(-) diff --git a/src/device/Kconfig b/src/device/Kconfig index d1f5694..4036a3d 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -210,10 +210,6 @@ config SMBUS_HAS_AUX_CHANNELS bool default n -config SPD_CACHE - bool - default n - config PCI bool default n diff --git a/src/device/dram/Makefile.inc b/src/device/dram/Makefile.inc index 05f440b..b1a6755 100644 --- a/src/device/dram/Makefile.inc +++ b/src/device/dram/Makefile.inc @@ -1 +1 @@ -romstage-$(CONFIG_SPD_CACHE) += spd_cache.c ddr3.c +romstage-y += ddr3.c diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c deleted file mode 100644 index a74e4a7..0000000 --- a/src/device/dram/spd_cache.c +++ /dev/null @@ -1,67 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2013 Advanced Micro Devices, Inc. - * Copyright (C) 2013 Sage Electronic Engineering, LLC - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <cbfs.h> -#include <console/console.h> -#include <device/dram/ddr3.h> -#include <spd_cache.h> -#include <stdint.h> -#include <string.h> - -#define SPD_SIZE 128 - -_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); - -int read_ddr3_spd_from_cbfs(u8 *buf, int idx) -{ - const int SPD_CRC_HI = 127; - const int SPD_CRC_LO = 126; - - const char *spd_file; - size_t spd_file_len = 0; - size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; - - spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, - &spd_file_len); - if (!spd_file) - printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); - if (spd_file_len < min_len) - printk(BIOS_EMERG, "Missing SPD data."); - if (!spd_file || spd_file_len < min_len) - return -1; - - memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - - u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); - - if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) - || (buf[SPD_CRC_LO] != (crc & 0xff)) - || (buf[SPD_CRC_HI] != (crc >> 8))) { - printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", - buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); - buf[SPD_CRC_LO] = crc & 0xff; - buf[SPD_CRC_HI] = crc >> 8; - u16 i; - printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { - if((i % 16) == 0x00) - printk(BIOS_WARNING, "\n%02x: ", i); - printk(BIOS_WARNING, "%02x ", buf[i]); - } - printk(BIOS_WARNING, "\n"); - } - return 0; -} diff --git a/src/include/spd_bin.h b/src/include/spd_bin.h index a0c1bbd..4d5ce2f 100644 --- a/src/include/spd_bin.h +++ b/src/include/spd_bin.h @@ -54,4 +54,7 @@ int get_spd_cbfs_rdev(struct region_device *spd_rdev, u8 spd_index); void dump_spd_info(struct spd_block *blk); void get_spd_smbus(struct spd_block *blk); +/* expects SPD size to be 128 bytes, reads from "spd.bin" in CBFS and + verifies the checksum. Only available if CONFIG_DIMM_SPD_SIZE == 128. */ +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #endif diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h deleted file mode 100644 index 912aa64..0000000 --- a/src/include/spd_cache.h +++ /dev/null @@ -1,26 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; either version 2 of the License, or - * (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#ifndef _SPD_CACHE_H_ -#define _SPD_CACHE_H_ - -#include <stdint.h> - -#if IS_ENABLED(CONFIG_SPD_CACHE) -int read_ddr3_spd_from_cbfs(u8 *buf, int idx); -#else -static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } -#endif - -#endif diff --git a/src/lib/Makefile.inc b/src/lib/Makefile.inc index 38b3c12..977770f 100644 --- a/src/lib/Makefile.inc +++ b/src/lib/Makefile.inc @@ -287,9 +287,9 @@ ramstage-$(CONFIG_HAVE_MONOTONIC_TIMER) += hw-time-timer.adb endif # CONFIG_RAMSTAGE_LIBHWBASE -ifeq ($(CONFIG_GENERIC_SPD_BIN),y) -romstage-$(CONFIG_GENERIC_SPD_BIN) += spd_bin.c +romstage-y += spd_bin.c +ifeq ($(CONFIG_GENERIC_SPD_BIN),y) LIB_SPD_BIN = $(obj)/spd.bin LIB_SPD_DEPS = $(foreach f, $(SPD_SOURCES), src/mainboard/$(MAINBOARDDIR)/spd/$(f).spd.hex) diff --git a/src/lib/spd_bin.c b/src/lib/spd_bin.c index 4108839..8f358bb 100644 --- a/src/lib/spd_bin.c +++ b/src/lib/spd_bin.c @@ -19,6 +19,7 @@ #include <spd_bin.h> #include <string.h> #include <device/early_smbus.h> +#include <device/dram/ddr3.h> static u8 spd_data[CONFIG_DIMM_MAX * CONFIG_DIMM_SPD_SIZE] CAR_GLOBAL; @@ -164,3 +165,46 @@ void get_spd_smbus(struct spd_block *blk) update_spd_len(blk); } + +#if CONFIG_DIMM_SPD_SIZE == 128 +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) +{ + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + + const char *spd_file; + size_t spd_file_len = 0; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; + + spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, + &spd_file_len); + if (!spd_file) + printk(BIOS_EMERG, "file [spd.bin] not found in CBFS"); + if (spd_file_len < min_len) + printk(BIOS_EMERG, "Missing SPD data."); + if (!spd_file || spd_file_len < min_len) + return -1; + + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); + + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); + + if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) + || (buf[SPD_CRC_LO] != (crc & 0xff)) + || (buf[SPD_CRC_HI] != (crc >> 8))) { + printk(BIOS_WARNING, "SPD CRC %02x%02x is invalid, should be %04x\n", + buf[SPD_CRC_HI], buf[SPD_CRC_LO], crc); + buf[SPD_CRC_LO] = crc & 0xff; + buf[SPD_CRC_HI] = crc >> 8; + u16 i; + printk(BIOS_WARNING, "\nDisplay the SPD"); + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { + if((i % 16) == 0x00) + printk(BIOS_WARNING, "\n%02x: ", i); + printk(BIOS_WARNING, "%02x ", buf[i]); + } + printk(BIOS_WARNING, "\n"); + } + return 0; +} +#endif diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index 7bf3c86..3999039 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 2ceb5c8..e6773b8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -24,7 +24,7 @@ #include "imc.h" #endif #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINTN FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ee26772..6631ac8 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_4096 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 10ec422..9b241fc 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -25,7 +25,7 @@ #endif #include "hudson.h" #include <stdlib.h> -#include <spd_cache.h> +#include <spd_bin.h> static AGESA_STATUS Fch_Oem_config(UINT32 Func, UINT32 FchData, VOID *ConfigPtr); static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr); diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index 60a59ac..c8472c4 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select BOARD_ROMSIZE_KB_8192 select GFXUMA select SUPERIO_FINTEK_F81866D - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 8109019..4177b1d 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_2048 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 349f827..f5509f6 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -27,7 +27,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_4096 select GFXUMA - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index f35cbd2..7604277 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/agesa/BiosCallOuts.h> #include "heapManager.h" #include "SB800.h" diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index f882b78..5e927cc 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -29,7 +29,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_OPTION_TABLE select HAVE_CMOS_DEFAULT select BOARD_ROMSIZE_KB_2048 - select SPD_CACHE config MAINBOARD_DIR string diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index 221b315..ab9d521 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -15,7 +15,7 @@ #include "AGESA.h" #include "amdlib.h" -#include <spd_cache.h> +#include <spd_bin.h> #include <northbridge/amd/pi/BiosCallOuts.h> #include "Ids.h" #include "OptionsIds.h" diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index de42721..4303b84 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -26,7 +26,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy select HAVE_MP_TABLE select HAVE_ACPI_TABLES select BOARD_ROMSIZE_KB_8192 - select SPD_CACHE select HUDSON_DISABLE_IMC select USE_BLOBS diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index 953774a..0805c02 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h" diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index e38d807..6b8aaee 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -15,7 +15,7 @@ */ #include <cbfs.h> -#include <spd_cache.h> +#include <spd_bin.h> #include "AGESA.h" #include "amdlib.h"

1 0

Patch set updated for coreboot: ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs()
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18264 -gerrit commit fa56c370929c8afc944963883199fd15247e1842 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 15:26:43 2017 +0100 ddr3 spd: Rename read_spd_from_cbfs() to read_ddr3_spd_from_cbfs() Since it checks for DDR3 style checksums, it's a more appropriate name. Also make its configuration local for a future code move. Change-Id: I417ae165579618d9215b8ca5f0500ff9a61af42f Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/device/dram/spd_cache.c | 7 ++++--- src/include/spd_cache.h | 4 ++-- src/mainboard/bap/ode_e20XX/BiosCallOuts.c | 2 +- src/mainboard/bap/ode_e21XX/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu1/BiosCallOuts.c | 2 +- src/mainboard/pcengines/apu2/BiosCallOuts.c | 2 +- src/northbridge/amd/agesa/def_callouts.c | 2 +- src/northbridge/amd/pi/def_callouts.c | 2 +- 8 files changed, 12 insertions(+), 11 deletions(-) diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index 3bdd9c1..a74e4a7 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -22,13 +22,14 @@ #include <string.h> #define SPD_SIZE 128 -#define SPD_CRC_HI 127 -#define SPD_CRC_LO 126 _Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); -int read_spd_from_cbfs(u8 *buf, int idx) +int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { + const int SPD_CRC_HI = 127; + const int SPD_CRC_LO = 126; + const char *spd_file; size_t spd_file_len = 0; size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; diff --git a/src/include/spd_cache.h b/src/include/spd_cache.h index 669639b..912aa64 100644 --- a/src/include/spd_cache.h +++ b/src/include/spd_cache.h @@ -18,9 +18,9 @@ #include <stdint.h> #if IS_ENABLED(CONFIG_SPD_CACHE) -int read_spd_from_cbfs(u8 *buf, int idx); +int read_ddr3_spd_from_cbfs(u8 *buf, int idx); #else -static inline int read_spd_from_cbfs(u8 *buf, int idx) { return -1; } +static inline int read_ddr3_spd_from_cbfs(u8 *buf, int idx) { return -1; } #endif #endif diff --git a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c index 9880b60..2ceb5c8 100644 --- a/src/mainboard/bap/ode_e20XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e20XX/BiosCallOuts.c @@ -239,7 +239,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c index 41603da..10ec422 100644 --- a/src/mainboard/bap/ode_e21XX/BiosCallOuts.c +++ b/src/mainboard/bap/ode_e21XX/BiosCallOuts.c @@ -328,7 +328,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8 *)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8 *)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu1/BiosCallOuts.c b/src/mainboard/pcengines/apu1/BiosCallOuts.c index 536ec5f..f35cbd2 100644 --- a/src/mainboard/pcengines/apu1/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu1/BiosCallOuts.c @@ -63,7 +63,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *Confi return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/mainboard/pcengines/apu2/BiosCallOuts.c b/src/mainboard/pcengines/apu2/BiosCallOuts.c index fe64d64..221b315 100644 --- a/src/mainboard/pcengines/apu2/BiosCallOuts.c +++ b/src/mainboard/pcengines/apu2/BiosCallOuts.c @@ -141,7 +141,7 @@ static AGESA_STATUS board_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *Conf return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, index) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, index) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/agesa/def_callouts.c b/src/northbridge/amd/agesa/def_callouts.c index a2e12a9..953774a 100644 --- a/src/northbridge/amd/agesa/def_callouts.c +++ b/src/northbridge/amd/agesa/def_callouts.c @@ -143,7 +143,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINTN Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS; diff --git a/src/northbridge/amd/pi/def_callouts.c b/src/northbridge/amd/pi/def_callouts.c index 61b5c8b..e38d807 100644 --- a/src/northbridge/amd/pi/def_callouts.c +++ b/src/northbridge/amd/pi/def_callouts.c @@ -132,7 +132,7 @@ AGESA_STATUS agesa_ReadSpd_from_cbfs(UINT32 Func, UINT32 Data, VOID *ConfigPtr) return AGESA_UNSUPPORTED; /* Read index 0, first SPD_SIZE bytes of spd.bin file. */ - if (read_spd_from_cbfs((u8*)info->Buffer, 0) < 0) + if (read_ddr3_spd_from_cbfs((u8*)info->Buffer, 0) < 0) die("No SPD data\n"); Status = AGESA_SUCCESS;

1 0

Patch set updated for coreboot: device/dram: use global DIMM_SPD_SIZE Kconfig variable
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18254 -gerrit commit af541b7456c034765e008f702ff8150484b57b71 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Sat Jan 28 13:12:09 2017 +0100 device/dram: use global DIMM_SPD_SIZE Kconfig variable Also make sure that no board changes behaviour because of that by adding a static assert. TEST=abuild over all builds still succeeds (where it doesn't if DIMM_SPD_SIZE isn't set to 128 bytes for boards that use the device/dram code). Change-Id: Iddb962b16857ee859ddcf1b52d18da9b3be56449 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/Kconfig | 1 - src/device/dram/spd_cache.c | 10 ++++++---- src/mainboard/amd/db-ft3b-lc/Kconfig | 4 ++++ src/mainboard/bap/ode_e20XX/Kconfig | 4 ++++ src/mainboard/bap/ode_e21XX/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo/Kconfig | 4 ++++ src/mainboard/gizmosphere/gizmo2/Kconfig | 4 ++++ src/mainboard/pcengines/apu1/Kconfig | 4 ++++ src/mainboard/pcengines/apu2/Kconfig | 4 ++++ 9 files changed, 34 insertions(+), 5 deletions(-) diff --git a/src/Kconfig b/src/Kconfig index e18a1dd..e2e66de 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -1236,7 +1236,6 @@ config DIMM_MAX config DIMM_SPD_SIZE int default 256 - depends on GENERIC_SPD_BIN help Total SPD size that will be used for DIMM. Ex: DDR3 256, DDR4 512. diff --git a/src/device/dram/spd_cache.c b/src/device/dram/spd_cache.c index c7dd97d..3bdd9c1 100644 --- a/src/device/dram/spd_cache.c +++ b/src/device/dram/spd_cache.c @@ -25,11 +25,13 @@ #define SPD_CRC_HI 127 #define SPD_CRC_LO 126 +_Static_assert(SPD_SIZE == CONFIG_DIMM_SPD_SIZE, "configured SPD sizes differ"); + int read_spd_from_cbfs(u8 *buf, int idx) { const char *spd_file; size_t spd_file_len = 0; - size_t min_len = (idx + 1) * SPD_SIZE; + size_t min_len = (idx + 1) * CONFIG_DIMM_SPD_SIZE; spd_file = cbfs_boot_map_with_leak("spd.bin", CBFS_TYPE_SPD, &spd_file_len); @@ -40,9 +42,9 @@ int read_spd_from_cbfs(u8 *buf, int idx) if (!spd_file || spd_file_len < min_len) return -1; - memcpy(buf, spd_file + (idx * SPD_SIZE), SPD_SIZE); + memcpy(buf, spd_file + (idx * CONFIG_DIMM_SPD_SIZE), CONFIG_DIMM_SPD_SIZE); - u16 crc = spd_ddr3_calc_crc(buf, SPD_SIZE); + u16 crc = spd_ddr3_calc_crc(buf, CONFIG_DIMM_SPD_SIZE); if (((buf[SPD_CRC_LO] == 0) && (buf[SPD_CRC_HI] == 0)) || (buf[SPD_CRC_LO] != (crc & 0xff)) @@ -53,7 +55,7 @@ int read_spd_from_cbfs(u8 *buf, int idx) buf[SPD_CRC_HI] = crc >> 8; u16 i; printk(BIOS_WARNING, "\nDisplay the SPD"); - for (i = 0; i < SPD_SIZE; i++) { + for (i = 0; i < CONFIG_DIMM_SPD_SIZE; i++) { if((i % 16) == 0x00) printk(BIOS_WARNING, "\n%02x: ", i); printk(BIOS_WARNING, "%02x ", buf[i]); diff --git a/src/mainboard/amd/db-ft3b-lc/Kconfig b/src/mainboard/amd/db-ft3b-lc/Kconfig index ace741d..7bf3c86 100644 --- a/src/mainboard/amd/db-ft3b-lc/Kconfig +++ b/src/mainboard/amd/db-ft3b-lc/Kconfig @@ -53,4 +53,8 @@ config HUDSON_LEGACY_FREE bool default y +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_AMD_DB_FT3B_LC diff --git a/src/mainboard/bap/ode_e20XX/Kconfig b/src/mainboard/bap/ode_e20XX/Kconfig index ad1c3de..ee26772 100644 --- a/src/mainboard/bap/ode_e20XX/Kconfig +++ b/src/mainboard/bap/ode_e20XX/Kconfig @@ -80,4 +80,8 @@ config BAP_E20_DDR3_1066 endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E20XX diff --git a/src/mainboard/bap/ode_e21XX/Kconfig b/src/mainboard/bap/ode_e21XX/Kconfig index b356749..60a59ac 100644 --- a/src/mainboard/bap/ode_e21XX/Kconfig +++ b/src/mainboard/bap/ode_e21XX/Kconfig @@ -74,4 +74,8 @@ config BAP_E21_DDR3_1333 endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_ODE_E21XX diff --git a/src/mainboard/gizmosphere/gizmo/Kconfig b/src/mainboard/gizmosphere/gizmo/Kconfig index 0c78f79..8109019 100644 --- a/src/mainboard/gizmosphere/gizmo/Kconfig +++ b/src/mainboard/gizmosphere/gizmo/Kconfig @@ -70,4 +70,8 @@ config SB800_AHCI_ROM bool default n +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO diff --git a/src/mainboard/gizmosphere/gizmo2/Kconfig b/src/mainboard/gizmosphere/gizmo2/Kconfig index 55beca6..349f827 100644 --- a/src/mainboard/gizmosphere/gizmo2/Kconfig +++ b/src/mainboard/gizmosphere/gizmo2/Kconfig @@ -61,4 +61,8 @@ config HUDSON_LEGACY_FREE bool default y +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_GIZMOSPHERE_GIZMO2 diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig index 3099d14..f882b78 100644 --- a/src/mainboard/pcengines/apu1/Kconfig +++ b/src/mainboard/pcengines/apu1/Kconfig @@ -116,4 +116,8 @@ endchoice config UART_D_RS485 bool "UART D drives RTS# in RS485 mode" if APU1_PINMUX_UART_D +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU1 diff --git a/src/mainboard/pcengines/apu2/Kconfig b/src/mainboard/pcengines/apu2/Kconfig index 0acf416..de42721 100644 --- a/src/mainboard/pcengines/apu2/Kconfig +++ b/src/mainboard/pcengines/apu2/Kconfig @@ -88,4 +88,8 @@ config APU2_PINMUX_UART_D endchoice +config DIMM_SPD_SIZE + int + default 128 + endif # BOARD_PCENGINES_APU2

1 0

Patch set updated for coreboot: mainboard/google/reef: Increase PL1 sampling period
by Sumeet R Pawnikar 10 Feb '17

10 Feb '17

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18317 -gerrit commit 9d24b8ec3a3962b49a76ad393b206776b1b12338 Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Feb 10 11:13:36 2017 +0530 mainboard/google/reef: Increase PL1 sampling period Performance degradation seen with current PL1 throttling rate as 8 seconds for TSR1 sensor with Aquarium workload. After fine tuning PL1 throttling rate to 15 seconds, fps score improved. BUG=chrome-os-partner:60038 BRANCH=reef TEST=Built and tested on electro system Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- .../google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index dba182e..0addae8 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -61,7 +61,7 @@ Name (DTRT, Package () { #endif /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },

1 0

Patch set updated for coreboot: [WIP] nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18305 -gerrit commit a36b251f908af542e6540d5e1f693c5894c7ad30 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 6 22:40:14 2017 +0100 [WIP] nb/i945/raminit: Use common ddr2 decode functions Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/raminit.c | 483 ++++++++--------------------------- src/northbridge/intel/i945/raminit.h | 5 +- 3 files changed, 116 insertions(+), 373 deletions(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 18e90b6..955b91c 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select RELOCATABLE_RAMSTAGE + select SPD_DDR2 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..f53c6db 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,8 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; - + dimm_attr dimm; /** * i945 supports two DIMMs, in two configurations: * @@ -357,9 +357,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i = 0; i<(2 * DIMM_SOCKETS); i++) { + int i, j, spd_size; + spd_raw_data raw_spd; + + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); - u8 reg8; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -368,31 +370,37 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (i >> 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + spd_size = spd_decode_spd_size_ddr2(spd_read_byte(device, 0)); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { - printk(BIOS_DEBUG, "N/A\n"); + for (j = 0; j < spd_size; j++) + raw_spd[j] = spd_read_byte(device, j); + + if (spd_decode_ddr2(&dimm, raw_spd) == SPD_STATUS_INVALID) continue; - } + dram_print_spd_ddr2(&dimm); + + sysinfo->dimm_decoded[i] = dimm; - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); - if (reg8 == ERROR_SCHEME_ECC) + if (sysinfo->dimm_decoded[i].flags.is_ecc) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); - if (reg8 & MODULE_BUFFERED) - die("Error: Buffered memory not supported by this chipset\n"); - if (reg8 & MODULE_REGISTERED) + switch (sysinfo->dimm_decoded[i].dimm_type) { + case SPD_RDIMM: + case SPD_72B_SO_RDIMM: + case SPD_MINI_RDIMM: die("Error: Registered memory not supported by this chipset\n"); + default: break; + } - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + switch (sysinfo->dimm_decoded[i].width) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_decoded[i].ranks) { + case 2: printk(BIOS_DEBUG, "x8DDS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x8DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; break; @@ -401,12 +409,12 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_decoded[i].ranks) { + case 2: printk(BIOS_DEBUG, "x16DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x16SS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; break; @@ -417,15 +425,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) default: die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); } - if (!dimm_mask) { die("No memory installed.\n"); } if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + /* Possible does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } } @@ -438,7 +445,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) static void sdram_verify_package_type(struct sys_info * sysinfo) { int i; - /* Assume no stacked DIMMs are available until we find one */ sysinfo->package = 0; for (i = 0; i < 2*DIMM_SOCKETS; i++) { @@ -446,314 +452,85 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->dimm_decoded[i].flags.stacked) sysinfo->package = 1; } } -static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) +static void select_cas_dramfreq(struct sys_info * sysinfo) { - int i; - u8 cas_mask; + dimm_attr dimm[2 * DIMM_SOCKETS]; + u8 selected_freq, selected_cas; + int max_ram_speed = 0, i; + int ret; + u8 cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 + | SPD_CAS_LATENCY_DDR2_5; - /* Setup CAS mask with all supported CAS Latencies */ - cas_mask = SPD_CAS_LATENCY_DDR2_3 | - SPD_CAS_LATENCY_DDR2_4 | - SPD_CAS_LATENCY_DDR2_5; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); - } - - if (!cas_mask) { - die("No DDR-II modules with accepted CAS latencies found.\n"); - } - - return cas_mask; -} - -static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) -{ - int i, j, idx; - int lowest_common_cas = 0; - int max_ram_speed = 0; - - const u8 ddr2_speeds_table[] = { - 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ - 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ - 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ - }; - - const u8 spd_lookup_table[] = { - SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, - SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, - SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD - }; + for (i = 0; i < 2 * DIMM_SOCKETS; i++) + dimm[i] = sysinfo->dimm_decoded[i]; switch (sdram_capabilities_max_supported_memory_frequency()) { - case 400: max_ram_speed = 0; break; - case 533: max_ram_speed = 1; break; - case 667: max_ram_speed = 2; break; - } - - sysinfo->memory_frequency = 0; - sysinfo->cas = 0; - - if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { - lowest_common_cas = 3; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { - lowest_common_cas = 4; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) { - lowest_common_cas = 5; + case 400: max_ram_speed = DDR2_200MHZ; break; + case 533: max_ram_speed = DDR2_266MHZ; break; + case 667: max_ram_speed = DDR2_333MHZ; break; } - PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas); - - for (j = max_ram_speed; j>=0; j--) { - int freq_cas_mask = cas_mask; - - PRINTK_DEBUG("Probing Speed %d\n", j); - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); - int current_cas_mask; - - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { - continue; - } - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); - - while (current_cas_mask) { - int highest_supported_cas = 0, current_cas = 0; - PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask); - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - highest_supported_cas = 5; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - highest_supported_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - highest_supported_cas = 3; - } else { - die("Invalid max. CAS.\n"); - } - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - current_cas = 3; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - current_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - current_cas = 5; - } else { - die("Invalid CAS.\n"); - } - - idx = highest_supported_cas - current_cas; - PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); - - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { - PRINTK_DEBUG(": OK\n"); - break; - } - - PRINTK_DEBUG(": Not fast enough!\n"); - - current_cas_mask &= ~(1 << (current_cas)); - } - - freq_cas_mask &= current_cas_mask; - if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); - break; - } - } - PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask); - if (freq_cas_mask) { - switch (j) { - case 0: sysinfo->memory_frequency = 400; break; - case 1: sysinfo->memory_frequency = 533; break; - case 2: sysinfo->memory_frequency = 667; break; - } - if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - sysinfo->cas = 3; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - sysinfo->cas = 4; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - sysinfo->cas = 5; - } - break; - } - } - - if (sysinfo->memory_frequency && sysinfo->cas) { - printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", - sysinfo->memory_frequency, sysinfo->cas); - } else { + ret = get_common_freq_cas(max_ram_speed, cas_mask, + dimm, 2 * DIMM_SOCKETS, &selected_freq, + &selected_cas); + if (ret) die("Could not find common memory frequency and CAS\n"); - } -} -static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) -{ - int i; - int tRAS_time; - int tRAS_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + sysinfo->cas = selected_cas; + switch (selected_freq) { + case DDR2_200MHZ: sysinfo->memory_frequency = 400; break; + case DDR2_266MHZ: sysinfo->memory_frequency = 533; break; + case DDR2_333MHZ: sysinfo->memory_frequency = 667; break; } - - tRAS_cycles = 4; /* 4 clocks minimum */ - tRAS_time = tRAS_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (!reg8) { - die("Invalid tRAS value.\n"); - } - - while ((tRAS_time >> 2) < reg8) { - tRAS_time += freq_multiplier; - tRAS_cycles++; - } - } - if (tRAS_cycles > 0x18) { - die("DDR-II Module does not support this frequency (tRAS error)\n"); - } - - printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles); - sysinfo->tras = tRAS_cycles; -} - -static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) -{ - int i; - int tRP_time; - int tRP_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRP_cycles = 2; /* 2 clocks minimum */ - tRP_time = tRP_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); - if (!reg8) { - die("Invalid tRP value.\n"); - } - - while (tRP_time < reg8) { - tRP_time += freq_multiplier; - tRP_cycles++; - } - } - - if (tRP_cycles > 6) { - die("DDR-II Module does not support this frequency (tRP error)\n"); - } - - printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles); - sysinfo->trp = tRP_cycles; -} - -static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) -{ - int i; - int tRCD_time; - int tRCD_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRCD_cycles = 2; /* 2 clocks minimum */ - tRCD_time = tRCD_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); - if (!reg8) { - die("Invalid tRCD value.\n"); - } - - while (tRCD_time < reg8) { - tRCD_time += freq_multiplier; - tRCD_cycles++; - } - } - if (tRCD_cycles > 6) { - die("DDR-II Module does not support this frequency (tRCD error)\n"); - } - - printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles); - sysinfo->trcd = tRCD_cycles; + printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", + sysinfo->cas, sysinfo->memory_frequency); } -static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) +static void select_dram_timings(struct sys_info * sysinfo) { int i; - int tWR_time; - int tWR_cycles; - int freq_multiplier = 0; + int tCLK = 0; + int tRAS_cycles, tRP_cycles, tRCD_cycles, tWR_cycles; switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + case 400: tCLK = TCK_200MHZ; break; + case 533: tCLK = TCK_266MHZ; break; + case 667: tCLK = TCK_333MHZ; break; } - tWR_cycles = 2; /* 2 clocks minimum */ - tWR_time = tWR_cycles * freq_multiplier; - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); - if (!reg8) { - die("Invalid tWR value.\n"); - } - - while (tWR_time < reg8) { - tWR_time += freq_multiplier; - tWR_cycles++; - } - } - if (tWR_cycles > 5) { - die("DDR-II Module does not support this frequency (tWR error)\n"); - } - - printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles); - sysinfo->twr = tWR_cycles; + tRAS_cycles = sysinfo->dimm_decoded[i].tRAS / tCLK + + ((sysinfo->dimm_decoded[i].tRAS % tCLK) ? 1 : 0); + if (tRAS_cycles > sysinfo->tras) + sysinfo->tras = tRAS_cycles; + + tRP_cycles = sysinfo->dimm_decoded[i].tRP / tCLK + + ((sysinfo->dimm_decoded[i].tRP % tCLK) ? 1 : 0); + if (tRP_cycles > sysinfo->trp) + sysinfo->trp = tRP_cycles; + + tRCD_cycles = sysinfo->dimm_decoded[i].tRCD / tCLK + + ((sysinfo->dimm_decoded[i].tRCD % tCLK) ? 1 : 0); + if (tRCD_cycles > sysinfo->trcd) + sysinfo->trcd = tRCD_cycles; + + tWR_cycles = sysinfo->dimm_decoded[i].tWR / tCLK + + ((sysinfo->dimm_decoded[i].tWR % tCLK) ? 1 : 0); + if (tWR_cycles > sysinfo->twr) + sysinfo->twr = tWR_cycles; + } + printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); + printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); + printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); + printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); } static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) @@ -819,23 +596,20 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); - - /* 15.6us */ - if (!refresh) - continue; + refresh = sysinfo->dimm_decoded[i].tRR; /* Refresh is slower than 15.6us, use 15.6us */ - if (refresh > 2) + /* tRR is decoded in units of 1/256us */ + if (refresh >= 15625 * 256) continue; - if (refresh == 2) { + if (refresh == 15625 * 256 / 2) { sysinfo->refresh = 1; break; } - die("DDR-II module has unsupported refresh value\n"); + if (refresh == 15625 * 256 / 4) + die("DDR-II module has unsupported refresh value\n"); } printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); } @@ -848,8 +622,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!sysinfo->dimm_decoded[i].flags.bl8) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1385,47 +1158,36 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, rows, columns, device; + int value, rows, columns; - device = get_dimm_spd_address(sysinfo, dimmno); sz.side1 = 0; sz.side2 = 0; - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + rows = sysinfo->dimm_decoded[dimmno].row_bits; if (rows < 0) goto hw_err; if ((rows & 0xf) == 0) goto val_err; sz.side1 += rows & 0xf; - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columns = sysinfo->dimm_decoded[dimmno].col_bits; if (columns < 0) goto hw_err; if ((columns & 0xf) == 0) goto val_err; sz.side1 += columns & 0xf; - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + value = sysinfo->dimm_decoded[dimmno].banks; if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; sz.side1 += log2(value & 0xff); - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + value = sysinfo->dimm_decoded[dimmno].mod_width; if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); if ((value != 72) && (value != 64)) goto val_err; sz.side1 += log2(value); - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; + switch (sysinfo->dimm_decoded[dimmno].ranks) { + case 1: goto out; + case 2: break; + default: goto val_err; + } /* Start with the symmetrical case */ sz.side2 = sz.side1; @@ -1472,9 +1234,6 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) sz = sdram_get_dimm_size(sysinfo, i); - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ - if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1564,25 +1323,19 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int i; u16 dra0 = 0, dra1 = 0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes...\n"); for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; u8 columnsrows; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - columnsrows = (value & 0x0f); - - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - columnsrows |= (value & 0xf) << 4; + columnsrows = (sysinfo->dimm_decoded[i].row_bits & 0x0f) + | (sysinfo->dimm_decoded[i].col_bits & 0xf) << 4; switch (columnsrows) { case 0x9d: dra = 2; break; @@ -1630,7 +1383,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (sysinfo->banks[i] != 8) + if (sysinfo->dimm_decoded[i].banks != 8) continue; printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); @@ -1729,8 +1482,8 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) /* CL 3, 4, 5 */ 3, 4, 5, /* FSB533, DDR667/533/400 */ 4, 5, 6, /* FSB667, DDR667/533/400 */ - 5, 6, 7, /* FSB800, DDR400/533 */ - 6, 7, 8, /* FSB800, DDR667 */ + 4, 5, 6, /* FSB800, DDR400/533 */ + 5, 6, 7, /* FSB800, DDR667 */ 5, 6, 7, /* FSB1066, DDR400 */ 7, 8, 9, /* FSB1066, DDR533/DDR667 */ }; @@ -3062,7 +2815,7 @@ static void sdram_setup_processor_side(void) void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sys_info sysinfo; - u8 reg8, cas_mask; + u8 reg8; printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -3080,20 +2833,11 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Check whether we have stacked DIMMs */ sdram_verify_package_type(&sysinfo); - /* Determine common CAS */ - cas_mask = sdram_possible_cas_latencies(&sysinfo); + /* Select common CAS latency and dram frequency */ + select_cas_dramfreq(&sysinfo); - /* Choose Common Frequency */ - sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask); - - /* Determine smallest common tRAS */ - sdram_detect_smallest_tRAS(&sysinfo); - - /* Determine tRP */ - sdram_detect_smallest_tRP(&sysinfo); - - /* Determine tRCD */ - sdram_detect_smallest_tRCD(&sysinfo); + /* Select nRAS, nRP, nRCD, nWR */ + select_dram_timings(&sysinfo); /* Determine smallest refresh period */ sdram_detect_smallest_refresh(&sysinfo); @@ -3101,9 +2845,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Verify all DIMMs support burst length 8 */ sdram_verify_burst_length(&sysinfo); - /* determine tWR */ - sdram_detect_smallest_tWR(&sysinfo); - /* Determine DIMM size parameters (rows, columns banks) */ sdram_detect_dimm_size(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 0554900..56d30e5 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -23,6 +23,8 @@ /* Burst length is always 8 */ #define BURSTLENGTH 8 +#include <device/dram/ddr2.h> + struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */ @@ -50,14 +52,13 @@ struct sys_info { #define SYSINFO_PACKAGE_PLANAR 0x00 #define SYSINFO_PACKAGE_STACKED 0x01 u8 dimm[2 * DIMM_SOCKETS]; + dimm_attr dimm_decoded[2 * DIMM_SOCKETS]; #define SYSINFO_DIMM_X16DS 0x00 #define SYSINFO_DIMM_X8DS 0x01 #define SYSINFO_DIMM_X16SS 0x02 #define SYSINFO_DIMM_X8DDS 0x03 #define SYSINFO_DIMM_NOT_POPULATED 0x04 - u8 banks[2 * DIMM_SOCKETS]; - u8 banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses;

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Patch set updated for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit 592032919490b2e88d6dca68d127c87cb470f972 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function has a CAS mask as input encoded in the same way as SPD byte 18. It tries to find the fastest frequency at the lowest possible CAS latency. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 87 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 15 +++++++- 2 files changed, 101 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index b712192..21480eb 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,6 +111,21 @@ static u8 spd_get_msbs(u8 c) } /** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_lsbs(u8 c) +{ + int i; + for (i = 0; i < 7; i++) + if (c & (1 << i)) + return i; + + return 0; +} + +/** * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -593,3 +609,74 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr *dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas) +{ + int i, found, high_supp_cas, low_supp_cas; + u8 curr_freq, curr_cas; + + const int ddr2_speeds_table[] = { + TCK_200MHZ, + TCK_266MHZ, + TCK_333MHZ, + TCK_400MHZ, + TCK_533MHZ, + TCK_666MHZ, + TCK_700MHZ, + TCK_800MHZ, + }; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i].cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 1; + } + + high_supp_cas = spd_get_msbs(cas_mask); + low_supp_cas = spd_get_lsbs(cas_mask); + + /* Loop from fast to slow frequency, from low to high CAS latency */ + for (curr_freq = max_freq; + curr_freq >= 0; curr_freq--) { + printram("Trying speed: %d\n", curr_freq); + for (curr_cas = low_supp_cas; + curr_cas <= high_supp_cas; curr_cas++) { + printram(" Trying CAS: %d\n", curr_cas); + found = 1; + for (i = 0; i < num_dimms; i++) { + if (dimm[i].dimm_type == + SPD_DIMM_TYPE_UNDEFINED) + continue; + + printram(" Testing DIMM %d:", i); + if (dimm[i].cycle_time[curr_cas] == 0) { + printram(" CAS not supported"); + found = 0; + break; + } + + if (dimm[i].cycle_time[curr_cas] > + ddr2_speeds_table[curr_freq]) { + printram(" Timing too fast\n"); + found = 0; + break; + } + printram(" ok\n"); + } + if (found) { + *selected_freq = curr_freq; + *selected_cas = curr_cas; + return 0; + } + } + } + + printk(BIOS_DEBUG, "No common CAS Frequency combination possible!\n"); + return 1; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 236be49..8bfcfc1 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -46,6 +46,18 @@ #define TCK_333MHZ 768 #define TCK_266MHZ 960 #define TCK_200MHZ 1280 + +enum dram_freq { + DDR2_200MHZ, + DDR2_266MHZ, + DDR2_333MHZ, + DDR2_400MHZ, + DDR2_533MHZ, + DDR2_666MHZ, + DDR2_700MHZ, + DDR2_800MHZ, +}; + /** @} */ /** @@ -198,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr *dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

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New patch to review for coreboot: asus/m2v: Make _CRS methods serialized
by Paul Menzel 10 Feb '17

10 Feb '17

Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18323 -gerrit commit 8234b22209a65b4679ff55a46e536c5a895fdd45 Author: Paul Menzel <pmenzel(a)molgen.mpg.de> Date: Fri Feb 10 14:49:29 2017 +0100 asus/m2v: Make _CRS methods serialized Address the iasl 20160108-64 (Ubuntu 16.04) warnings below. ``` Intel ACPI Component Architecture ASL+ Optimizing Compiler version 20160108-64 Copyright (c) 2000 - 2016 Intel Corporation dsdt.aml 245: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 262: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 277: Method (_CRS, 0, NotSerialized) Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) dsdt.aml 295: Method(_CRS, 0) { Remark 2120 - ^ Control Method should be made Serialized (due to creation of named objects within) ``` Change-Id: Id5b0f33fba8ea25e4a6aa4f01c69a69aaf5aef23 Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de> --- src/mainboard/asus/m2v/dsdt.asl | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/mainboard/asus/m2v/dsdt.asl b/src/mainboard/asus/m2v/dsdt.asl index bfa3ba4..0753082 100644 --- a/src/mainboard/asus/m2v/dsdt.asl +++ b/src/mainboard/asus/m2v/dsdt.asl @@ -348,7 +348,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { Return (0x0f) } - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, Serialized) { Name (TMP, ResourceTemplate () { IO (Decode16, 0x0060, 0x0060, 0x01, 0x01) @@ -367,7 +367,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { Return (0x0f) } - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, Serialized) { Name (TMP, ResourceTemplate () { IRQNoFlags () {12} @@ -384,7 +384,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) { Return (0x0f) } - Method (_CRS, 0, NotSerialized) + Method (_CRS, 0, Serialized) { Name (TMP, ResourceTemplate () { IO (Decode16, 0x0378, 0x0378, 0x01, 0x08) @@ -406,7 +406,7 @@ DefinitionBlock ("DSDT.aml", "DSDT", 2, "CORE ", "COREBOOT", 1) External(TOM1) /* top of memory below 4GB */ - Method(_CRS, 0) { + Method(_CRS, 0, Serialized) { Name(TMP, ResourceTemplate() { WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, 0x0000, // Granularity

1 0

New patch to review for coreboot: google/gru: Fix whitespace
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18322 -gerrit commit 24de2e44d02a8981ca60f40e3acc383438c14a98 Author: Patrick Georgi <pgeorgi(a)chromium.org> Date: Fri Feb 10 14:59:27 2017 +0100 google/gru: Fix whitespace Change-Id: I538c28fb1bc412947ef9df947fa3f6a3312aeb4b Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> --- src/mainboard/google/gru/Kconfig.name | 1 - 1 file changed, 1 deletion(-) diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name index deace91..55d7a65 100644 --- a/src/mainboard/google/gru/Kconfig.name +++ b/src/mainboard/google/gru/Kconfig.name @@ -13,4 +13,3 @@ config BOARD_GOOGLE_BOB config BOARD_GOOGLE_SCARLET bool "Scarlet" select BOARD_GOOGLE_GRU_COMMON -

1 0

Patch set updated for coreboot: qualcomm/ipq40xx: add vector operation method to SPI
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18297 -gerrit commit ba2e6d2740a2e0059d26a94761a37af7c509c1b1 Author: Yuji Sasaki <sasakiy(a)google.com> Date: Thu Jan 26 10:17:45 2017 -0800 qualcomm/ipq40xx: add vector operation method to SPI Adding spi_xfer_two_vectors as .xfer_vector for ipq40xx spi_ctrlr. Commit c2973d196d1 ("UPSTREAM: spi: Get rid of SPI_ATOMIC_SEQUENCING") has added a new driver method xfer_vector to support combined write-read operation within a single CS cycle. The method is wrapped in the spi_xfer_vector() API. When spi_ctrlr structure does not have xfer_vector method, API calls write and read operations sequentially. However the QCA40xx SPI driver has "forced" CS activation-inactivation in xfer method, so individual operation will break CS after write operation, making combined write-read cycle broken. Adding xfer_vector method to spi_ctrlr is a simple fix to prevent this. BUG=None BRANCH=none TEST=built and run on Gale Change-Id: I2258e563d0793bcacd626f78b8e96b3649a8e4a4 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: 88a8824951cef4fe293dfa6e3a1a837ae07b6156 Original-Change-Id: I031e85ce5b847353cb1084f6f68b2af8c6f702e1 Original-Signed-off-by: Yuji Sasaki <sasakiy(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/433439 Original-Reviewed-by: Aaron Durbin <adurbin(a)chromium.org> Original-Reviewed-by: Kan Yan <kyan(a)google.com> --- src/soc/qualcomm/ipq40xx/spi.c | 1 + 1 file changed, 1 insertion(+) diff --git a/src/soc/qualcomm/ipq40xx/spi.c b/src/soc/qualcomm/ipq40xx/spi.c index 6d044b3..68c2dd0 100644 --- a/src/soc/qualcomm/ipq40xx/spi.c +++ b/src/soc/qualcomm/ipq40xx/spi.c @@ -656,6 +656,7 @@ static const struct spi_ctrlr spi_ctrlr = { .claim_bus = spi_ctrlr_claim_bus, .release_bus = spi_ctrlr_release_bus, .xfer = spi_ctrlr_xfer, + .xfer_vector = spi_xfer_two_vectors, }; int spi_setup_slave(unsigned int bus, unsigned int cs, struct spi_slave *slave)

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coreboot-gerrit February 2017