coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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Patch set updated for coreboot: google/gru: add scarlet variant
by Patrick Georgi 10 Feb '17

10 Feb '17

Patrick Georgi (pgeorgi(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18296 -gerrit commit d5feb791364aed9a3f8b9b9b98c147ede3c988fe Author: philipchen <philipchen(a)google.com> Date: Wed Jan 25 13:37:48 2017 -0800 google/gru: add scarlet variant There will be more follow-up changes. BUG=chrome-os-partner:62377 BRANCH=None TEST=emerge-scarlet coreboot libpayload Change-Id: I9ca45598ff0ab12bf8063d16a86be564cf509390 Signed-off-by: Patrick Georgi <pgeorgi(a)chromium.org> Original-Commit-Id: a020a9ba1228b15599e202972df0096f58b1b31c Original-Change-Id: I4804239483f8b35bc3703aa62c2a8fd642e0234a Original-Signed-off-by: philipchen <philipchen(a)google.com> Original-Reviewed-on: https://chromium-review.googlesource.com/433039 Original-Commit-Ready: Philip Chen <philipchen(a)chromium.org> Original-Tested-by: Philip Chen <philipchen(a)chromium.org> Original-Reviewed-by: Julius Werner <jwerner(a)chromium.org> --- src/mainboard/google/gru/Kconfig | 2 ++ src/mainboard/google/gru/Kconfig.name | 5 +++++ 2 files changed, 7 insertions(+) diff --git a/src/mainboard/google/gru/Kconfig b/src/mainboard/google/gru/Kconfig index 7ebae8d..6361bac 100644 --- a/src/mainboard/google/gru/Kconfig +++ b/src/mainboard/google/gru/Kconfig @@ -86,6 +86,7 @@ config CONSOLE_SERIAL_UART_ADDRESS ########################################################## config MAINBOARD_PART_NUMBER string + default "Scarlet" if BOARD_GOOGLE_SCARLET default "Bob" if BOARD_GOOGLE_BOB default "Gru" if BOARD_GOOGLE_GRU default "Kevin" if BOARD_GOOGLE_KEVIN @@ -93,6 +94,7 @@ config MAINBOARD_PART_NUMBER config GBB_HWID string depends on CHROMEOS + default "SCARLET TEST 7598" if BOARD_GOOGLE_SCARLET default "BOB TEST 7422" if BOARD_GOOGLE_BOB default "GRU TEST 5431" if BOARD_GOOGLE_GRU default "KEVIN TEST 1422" if BOARD_GOOGLE_KEVIN diff --git a/src/mainboard/google/gru/Kconfig.name b/src/mainboard/google/gru/Kconfig.name index 0aba8fb..deace91 100644 --- a/src/mainboard/google/gru/Kconfig.name +++ b/src/mainboard/google/gru/Kconfig.name @@ -9,3 +9,8 @@ config BOARD_GOOGLE_GRU config BOARD_GOOGLE_BOB bool "Bob" select BOARD_GOOGLE_GRU_COMMON + +config BOARD_GOOGLE_SCARLET + bool "Scarlet" + select BOARD_GOOGLE_GRU_COMMON +

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Patch set updated for coreboot: [WIP] nb/i945/raminit: Use common ddr2 decode functions
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18305 -gerrit commit 8366e2ea9f1284a1b7c12d44793220066d25c5e4 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Mon Feb 6 22:40:14 2017 +0100 [WIP] nb/i945/raminit: Use common ddr2 decode functions Change-Id: I97c93939d11807752797785dd88c70b43a236ee3 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/northbridge/intel/i945/Kconfig | 1 + src/northbridge/intel/i945/raminit.c | 483 ++++++++--------------------------- src/northbridge/intel/i945/raminit.h | 5 +- 3 files changed, 116 insertions(+), 373 deletions(-) diff --git a/src/northbridge/intel/i945/Kconfig b/src/northbridge/intel/i945/Kconfig index 18e90b6..955b91c 100644 --- a/src/northbridge/intel/i945/Kconfig +++ b/src/northbridge/intel/i945/Kconfig @@ -26,6 +26,7 @@ config NORTHBRIDGE_SPECIFIC_OPTIONS # dummy select INTEL_GMA_ACPI select INTEL_GMA_SSC_ALTERNATE_REF select RELOCATABLE_RAMSTAGE + select SPD_DDR2 config NORTHBRIDGE_INTEL_SUBTYPE_I945GC def_bool n diff --git a/src/northbridge/intel/i945/raminit.c b/src/northbridge/intel/i945/raminit.c index cc227cc..bac22d0 100644 --- a/src/northbridge/intel/i945/raminit.c +++ b/src/northbridge/intel/i945/raminit.c @@ -28,6 +28,7 @@ #include "i945.h" #include "chip.h" #include <cbmem.h> +#include <device/dram/ddr2.h> /* Debugging macros. */ #if CONFIG_DEBUG_RAM_SETUP @@ -315,8 +316,7 @@ static void sdram_detect_errors(struct sys_info *sysinfo) static void sdram_get_dram_configuration(struct sys_info *sysinfo) { u32 dimm_mask = 0; - int i; - + dimm_attr dimm; /** * i945 supports two DIMMs, in two configurations: * @@ -357,9 +357,11 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) * */ - for (i = 0; i<(2 * DIMM_SOCKETS); i++) { + int i, j, spd_size; + spd_raw_data raw_spd; + + for (i = 0; i < (2 * DIMM_SOCKETS); i++) { int device = get_dimm_spd_address(sysinfo, i); - u8 reg8; /* Initialize the socket information with a sane value */ sysinfo->dimm[i] = SYSINFO_DIMM_NOT_POPULATED; @@ -368,31 +370,37 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) if (!sdram_capabilities_dual_channel() && (i >> 1)) continue; - printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + spd_size = spd_decode_spd_size_ddr2(spd_read_byte(device, 0)); - if (spd_read_byte(device, SPD_MEMORY_TYPE) != SPD_MEMORY_TYPE_SDRAM_DDR2) { - printk(BIOS_DEBUG, "N/A\n"); + for (j = 0; j < spd_size; j++) + raw_spd[j] = spd_read_byte(device, j); + + if (spd_decode_ddr2(&dimm, raw_spd) == SPD_STATUS_INVALID) continue; - } + dram_print_spd_ddr2(&dimm); + + sysinfo->dimm_decoded[i] = dimm; - reg8 = spd_read_byte(device, SPD_DIMM_CONFIG_TYPE); - if (reg8 == ERROR_SCHEME_ECC) + if (sysinfo->dimm_decoded[i].flags.is_ecc) die("Error: ECC memory not supported by this chipset\n"); - reg8 = spd_read_byte(device, SPD_MODULE_ATTRIBUTES); - if (reg8 & MODULE_BUFFERED) - die("Error: Buffered memory not supported by this chipset\n"); - if (reg8 & MODULE_REGISTERED) + switch (sysinfo->dimm_decoded[i].dimm_type) { + case SPD_RDIMM: + case SPD_72B_SO_RDIMM: + case SPD_MINI_RDIMM: die("Error: Registered memory not supported by this chipset\n"); + default: break; + } - switch (spd_read_byte(device, SPD_PRIMARY_SDRAM_WIDTH)) { + printk(BIOS_DEBUG, "DDR II Channel %d Socket %d: ", (i >> 1), (i & 1)); + switch (sysinfo->dimm_decoded[i].width) { case 0x08: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_decoded[i].ranks) { + case 2: printk(BIOS_DEBUG, "x8DDS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DDS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x8DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X8DS; break; @@ -401,12 +409,12 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) } break; case 0x10: - switch (spd_read_byte(device, SPD_NUM_DIMM_BANKS) & 0x0f) { - case 1: + switch (sysinfo->dimm_decoded[i].ranks) { + case 2: printk(BIOS_DEBUG, "x16DS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16DS; break; - case 0: + case 1: printk(BIOS_DEBUG, "x16SS\n"); sysinfo->dimm[i] = SYSINFO_DIMM_X16SS; break; @@ -417,15 +425,14 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) default: die("Unsupported DDR-II memory width.\n"); } - dimm_mask |= (1 << i); } - if (!dimm_mask) { die("No memory installed.\n"); } if (!(dimm_mask & ((1 << DIMM_SOCKETS) - 1))) { + /* Possible does not boot in this case */ printk(BIOS_INFO, "Channel 0 has no memory populated.\n"); } } @@ -438,7 +445,6 @@ static void sdram_get_dram_configuration(struct sys_info *sysinfo) static void sdram_verify_package_type(struct sys_info * sysinfo) { int i; - /* Assume no stacked DIMMs are available until we find one */ sysinfo->package = 0; for (i = 0; i < 2*DIMM_SOCKETS; i++) { @@ -446,314 +452,85 @@ static void sdram_verify_package_type(struct sys_info * sysinfo) continue; /* Is the current DIMM a stacked DIMM? */ - if (spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_NUM_DIMM_BANKS) & (1 << 4)) + if (sysinfo->dimm_decoded[i].flags.stacked) sysinfo->package = 1; } } -static u8 sdram_possible_cas_latencies(struct sys_info * sysinfo) +static void select_cas_dramfreq(struct sys_info * sysinfo) { - int i; - u8 cas_mask; + dimm_attr *dimm; + u8 selected_freq, selected_cas; + int max_ram_speed = 0, i; + int ret; + u8 cas_mask = SPD_CAS_LATENCY_DDR2_3 | SPD_CAS_LATENCY_DDR2_4 + | SPD_CAS_LATENCY_DDR2_5; - /* Setup CAS mask with all supported CAS Latencies */ - cas_mask = SPD_CAS_LATENCY_DDR2_3 | - SPD_CAS_LATENCY_DDR2_4 | - SPD_CAS_LATENCY_DDR2_5; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - if (sysinfo->dimm[i] != SYSINFO_DIMM_NOT_POPULATED) - cas_mask &= spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_ACCEPTABLE_CAS_LATENCIES); - } - - if (!cas_mask) { - die("No DDR-II modules with accepted CAS latencies found.\n"); - } - - return cas_mask; -} - -static void sdram_detect_cas_latency_and_ram_speed(struct sys_info * sysinfo, u8 cas_mask) -{ - int i, j, idx; - int lowest_common_cas = 0; - int max_ram_speed = 0; - - const u8 ddr2_speeds_table[] = { - 0x50, 0x60, /* DDR2 400: tCLK = 5.0ns tAC = 0.6ns */ - 0x3d, 0x50, /* DDR2 533: tCLK = 3.75ns tAC = 0.5ns */ - 0x30, 0x45, /* DDR2 667: tCLK = 3.0ns tAC = 0.45ns */ - }; - - const u8 spd_lookup_table[] = { - SPD_MIN_CYCLE_TIME_AT_CAS_MAX, SPD_ACCESS_TIME_FROM_CLOCK, - SPD_SDRAM_CYCLE_TIME_2ND, SPD_ACCESS_TIME_FROM_CLOCK_2ND, - SPD_SDRAM_CYCLE_TIME_3RD, SPD_ACCESS_TIME_FROM_CLOCK_3RD - }; + for (i = 0; i < 2 * DIMM_SOCKETS; i++) + dimm[i] = sysinfo->dimm_decoded[i]; switch (sdram_capabilities_max_supported_memory_frequency()) { - case 400: max_ram_speed = 0; break; - case 533: max_ram_speed = 1; break; - case 667: max_ram_speed = 2; break; - } - - sysinfo->memory_frequency = 0; - sysinfo->cas = 0; - - if (cas_mask & SPD_CAS_LATENCY_DDR2_3) { - lowest_common_cas = 3; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_4) { - lowest_common_cas = 4; - } else if (cas_mask & SPD_CAS_LATENCY_DDR2_5) { - lowest_common_cas = 5; + case 400: max_ram_speed = DDR2_200MHZ; break; + case 533: max_ram_speed = DDR2_266MHZ; break; + case 667: max_ram_speed = DDR2_333MHZ; break; } - PRINTK_DEBUG("lowest common cas = %d\n", lowest_common_cas); - - for (j = max_ram_speed; j>=0; j--) { - int freq_cas_mask = cas_mask; - - PRINTK_DEBUG("Probing Speed %d\n", j); - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - int device = get_dimm_spd_address(sysinfo, i); - int current_cas_mask; - - PRINTK_DEBUG(" DIMM: %d\n", i); - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { - continue; - } - current_cas_mask = spd_read_byte(device, SPD_ACCEPTABLE_CAS_LATENCIES); - - while (current_cas_mask) { - int highest_supported_cas = 0, current_cas = 0; - PRINTK_DEBUG(" Current CAS mask: %04x; ", current_cas_mask); - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - highest_supported_cas = 5; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - highest_supported_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - highest_supported_cas = 3; - } else { - die("Invalid max. CAS.\n"); - } - if (current_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - current_cas = 3; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - current_cas = 4; - } else if (current_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - current_cas = 5; - } else { - die("Invalid CAS.\n"); - } - - idx = highest_supported_cas - current_cas; - PRINTK_DEBUG("idx=%d, ", idx); - PRINTK_DEBUG("tCLK=%x, ", spd_read_byte(device, spd_lookup_table[2*idx])); - PRINTK_DEBUG("tAC=%x", spd_read_byte(device, spd_lookup_table[(2*idx)+1])); - - if (spd_read_byte(device, spd_lookup_table[2*idx]) <= ddr2_speeds_table[2*j] && - spd_read_byte(device, spd_lookup_table[(2*idx)+1]) <= ddr2_speeds_table[(2*j)+1]) { - PRINTK_DEBUG(": OK\n"); - break; - } - - PRINTK_DEBUG(": Not fast enough!\n"); - - current_cas_mask &= ~(1 << (current_cas)); - } - - freq_cas_mask &= current_cas_mask; - if (!current_cas_mask) { - PRINTK_DEBUG(" No valid CAS for this speed on DIMM %d\n", i); - break; - } - } - PRINTK_DEBUG(" freq_cas_mask for speed %d: %04x\n", j, freq_cas_mask); - if (freq_cas_mask) { - switch (j) { - case 0: sysinfo->memory_frequency = 400; break; - case 1: sysinfo->memory_frequency = 533; break; - case 2: sysinfo->memory_frequency = 667; break; - } - if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_3) { - sysinfo->cas = 3; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_4) { - sysinfo->cas = 4; - } else if (freq_cas_mask & SPD_CAS_LATENCY_DDR2_5) { - sysinfo->cas = 5; - } - break; - } - } - - if (sysinfo->memory_frequency && sysinfo->cas) { - printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", - sysinfo->memory_frequency, sysinfo->cas); - } else { + ret = get_common_freq_cas(max_ram_speed, cas_mask, + (const dimm_attr **) &dimm, 2 * DIMM_SOCKETS, &selected_freq, + &selected_cas); + if (ret) die("Could not find common memory frequency and CAS\n"); - } -} -static void sdram_detect_smallest_tRAS(struct sys_info * sysinfo) -{ - int i; - int tRAS_time; - int tRAS_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + sysinfo->cas = selected_cas; + switch (selected_freq) { + case DDR2_200MHZ: sysinfo->memory_frequency = 400; break; + case DDR2_266MHZ: sysinfo->memory_frequency = 533; break; + case DDR2_333MHZ: sysinfo->memory_frequency = 667; break; } - - tRAS_cycles = 4; /* 4 clocks minimum */ - tRAS_time = tRAS_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ACTIVE_TO_PRECHARGE_DELAY); - if (!reg8) { - die("Invalid tRAS value.\n"); - } - - while ((tRAS_time >> 2) < reg8) { - tRAS_time += freq_multiplier; - tRAS_cycles++; - } - } - if (tRAS_cycles > 0x18) { - die("DDR-II Module does not support this frequency (tRAS error)\n"); - } - - printk(BIOS_DEBUG, "tRAS = %d cycles\n", tRAS_cycles); - sysinfo->tras = tRAS_cycles; -} - -static void sdram_detect_smallest_tRP(struct sys_info * sysinfo) -{ - int i; - int tRP_time; - int tRP_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRP_cycles = 2; /* 2 clocks minimum */ - tRP_time = tRP_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_ROW_PRECHARGE_TIME); - if (!reg8) { - die("Invalid tRP value.\n"); - } - - while (tRP_time < reg8) { - tRP_time += freq_multiplier; - tRP_cycles++; - } - } - - if (tRP_cycles > 6) { - die("DDR-II Module does not support this frequency (tRP error)\n"); - } - - printk(BIOS_DEBUG, "tRP = %d cycles\n", tRP_cycles); - sysinfo->trp = tRP_cycles; -} - -static void sdram_detect_smallest_tRCD(struct sys_info * sysinfo) -{ - int i; - int tRCD_time; - int tRCD_cycles; - int freq_multiplier = 0; - - switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ - } - - tRCD_cycles = 2; /* 2 clocks minimum */ - tRCD_time = tRCD_cycles * freq_multiplier; - - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) - continue; - - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_MIN_RAS_TO_CAS_DELAY); - if (!reg8) { - die("Invalid tRCD value.\n"); - } - - while (tRCD_time < reg8) { - tRCD_time += freq_multiplier; - tRCD_cycles++; - } - } - if (tRCD_cycles > 6) { - die("DDR-II Module does not support this frequency (tRCD error)\n"); - } - - printk(BIOS_DEBUG, "tRCD = %d cycles\n", tRCD_cycles); - sysinfo->trcd = tRCD_cycles; + printk(BIOS_DEBUG, "Memory will be driven at %dMHz with CAS=%d clocks\n", + sysinfo->cas, sysinfo->memory_frequency); } -static void sdram_detect_smallest_tWR(struct sys_info * sysinfo) +static void select_dram_timings(struct sys_info * sysinfo) { int i; - int tWR_time; - int tWR_cycles; - int freq_multiplier = 0; + int tCLK = 0; + int tRAS_cycles, tRP_cycles, tRCD_cycles, tWR_cycles; switch (sysinfo->memory_frequency) { - case 400: freq_multiplier = 0x14; break; /* 5ns */ - case 533: freq_multiplier = 0x0f; break; /* 3.75ns */ - case 667: freq_multiplier = 0x0c; break; /* 3ns */ + case 400: tCLK = TCK_200MHZ; break; + case 533: tCLK = TCK_266MHZ; break; + case 667: tCLK = TCK_333MHZ; break; } - tWR_cycles = 2; /* 2 clocks minimum */ - tWR_time = tWR_cycles * freq_multiplier; - for (i = 0; i < 2*DIMM_SOCKETS; i++) { - u8 reg8; - if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - reg8 = spd_read_byte(get_dimm_spd_address(sysinfo, i), SPD_WRITE_RECOVERY_TIME); - if (!reg8) { - die("Invalid tWR value.\n"); - } - - while (tWR_time < reg8) { - tWR_time += freq_multiplier; - tWR_cycles++; - } - } - if (tWR_cycles > 5) { - die("DDR-II Module does not support this frequency (tWR error)\n"); - } - - printk(BIOS_DEBUG, "tWR = %d cycles\n", tWR_cycles); - sysinfo->twr = tWR_cycles; + tRAS_cycles = sysinfo->dimm_decoded[i].tRAS / tCLK + + ((sysinfo->dimm_decoded[i].tRAS % tCLK) ? 1 : 0); + if (tRAS_cycles > sysinfo->tras) + sysinfo->tras = tRAS_cycles; + + tRP_cycles = sysinfo->dimm_decoded[i].tRP / tCLK + + ((sysinfo->dimm_decoded[i].tRP % tCLK) ? 1 : 0); + if (tRP_cycles > sysinfo->trp) + sysinfo->trp = tRP_cycles; + + tRCD_cycles = sysinfo->dimm_decoded[i].tRCD / tCLK + + ((sysinfo->dimm_decoded[i].tRCD % tCLK) ? 1 : 0); + if (tRCD_cycles > sysinfo->trcd) + sysinfo->trcd = tRCD_cycles; + + tWR_cycles = sysinfo->dimm_decoded[i].tWR / tCLK + + ((sysinfo->dimm_decoded[i].tWR % tCLK) ? 1 : 0); + if (tWR_cycles > sysinfo->twr) + sysinfo->twr = tWR_cycles; + } + printk(BIOS_DEBUG, "tRAS = %d cycles\n", sysinfo->tras); + printk(BIOS_DEBUG, "tRP = %d cycles\n", sysinfo->trp); + printk(BIOS_DEBUG, "tRCD = %d cycles\n", sysinfo->trcd); + printk(BIOS_DEBUG, "tWR = %d cycles\n", sysinfo->twr); } static void sdram_detect_smallest_tRFC(struct sys_info * sysinfo) @@ -819,23 +596,20 @@ static void sdram_detect_smallest_refresh(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - refresh = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_REFRESH) & ~(1 << 7); - - /* 15.6us */ - if (!refresh) - continue; + refresh = sysinfo->dimm_decoded[i].tRR; /* Refresh is slower than 15.6us, use 15.6us */ - if (refresh > 2) + /* tRR is decoded in units of 1/256us */ + if (refresh >= 15625 * 256) continue; - if (refresh == 2) { + if (refresh == 15625 * 256 / 2) { sysinfo->refresh = 1; break; } - die("DDR-II module has unsupported refresh value\n"); + if (refresh == 15625 * 256 / 4) + die("DDR-II module has unsupported refresh value\n"); } printk(BIOS_DEBUG, "Refresh: %s\n", sysinfo->refresh?"7.8us":"15.6us"); } @@ -848,8 +622,7 @@ static void sdram_verify_burst_length(struct sys_info * sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (!(spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_SUPPORTED_BURST_LENGTHS) & SPD_BURST_LENGTH_8)) + if (!sysinfo->dimm_decoded[i].flags.bl8) die("Only DDR-II RAM with burst length 8 is supported by this chipset.\n"); } } @@ -1385,47 +1158,36 @@ static struct dimm_size sdram_get_dimm_size(struct sys_info *sysinfo, u16 dimmno { /* Calculate the log base 2 size of a DIMM in bits */ struct dimm_size sz; - int value, low, rows, columns, device; + int value, rows, columns; - device = get_dimm_spd_address(sysinfo, dimmno); sz.side1 = 0; sz.side2 = 0; - rows = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ + rows = sysinfo->dimm_decoded[dimmno].row_bits; if (rows < 0) goto hw_err; if ((rows & 0xf) == 0) goto val_err; sz.side1 += rows & 0xf; - columns = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ + columns = sysinfo->dimm_decoded[dimmno].col_bits; if (columns < 0) goto hw_err; if ((columns & 0xf) == 0) goto val_err; sz.side1 += columns & 0xf; - value = spd_read_byte(device, SPD_NUM_BANKS_PER_SDRAM); /* banks */ + value = sysinfo->dimm_decoded[dimmno].banks; if (value < 0) goto hw_err; if ((value & 0xff) == 0) goto val_err; sz.side1 += log2(value & 0xff); - /* Get the module data width and convert it to a power of two */ - value = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_MSB); /* (high byte) */ + value = sysinfo->dimm_decoded[dimmno].mod_width; if (value < 0) goto hw_err; - value &= 0xff; - value <<= 8; - - low = spd_read_byte(device, SPD_MODULE_DATA_WIDTH_LSB); /* (low byte) */ - if (low < 0) goto hw_err; - value = value | (low & 0xff); if ((value != 72) && (value != 64)) goto val_err; sz.side1 += log2(value); - /* side 2 */ - value = spd_read_byte(device, SPD_NUM_DIMM_BANKS); /* number of physical banks */ - - if (value < 0) goto hw_err; - value &= 7; - value++; - if (value == 1) goto out; - if (value != 2) goto val_err; + switch (sysinfo->dimm_decoded[dimmno].ranks) { + case 1: goto out; + case 2: break; + default: goto val_err; + } /* Start with the symmetrical case */ sz.side2 = sz.side1; @@ -1472,9 +1234,6 @@ static void sdram_detect_dimm_size(struct sys_info * sysinfo) sz = sdram_get_dimm_size(sysinfo, i); - sysinfo->banks[i] = spd_read_byte(get_dimm_spd_address(sysinfo, i), - SPD_NUM_BANKS_PER_SDRAM); /* banks */ - if (sz.side1 < 30) die("DDR-II rank size smaller than 128MB is not supported.\n"); @@ -1564,25 +1323,19 @@ static int sdram_program_row_boundaries(struct sys_info *sysinfo) static int sdram_set_row_attributes(struct sys_info *sysinfo) { - int i, value; + int i; u16 dra0 = 0, dra1 = 0, dra = 0; printk(BIOS_DEBUG, "Setting row attributes...\n"); for (i = 0; i < 2 * DIMM_SOCKETS; i++) { - u16 device; u8 columnsrows; if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) { continue; } - device = get_dimm_spd_address(sysinfo, i); - - value = spd_read_byte(device, SPD_NUM_ROWS); /* rows */ - columnsrows = (value & 0x0f); - - value = spd_read_byte(device, SPD_NUM_COLUMNS); /* columns */ - columnsrows |= (value & 0xf) << 4; + columnsrows = (sysinfo->dimm_decoded[i].row_bits & 0x0f) + | (sysinfo->dimm_decoded[i].col_bits & 0xf) << 4; switch (columnsrows) { case 0x9d: dra = 2; break; @@ -1630,7 +1383,7 @@ static void sdram_set_bank_architecture(struct sys_info *sysinfo) if (sysinfo->dimm[i] == SYSINFO_DIMM_NOT_POPULATED) continue; - if (sysinfo->banks[i] != 8) + if (sysinfo->dimm_decoded[i].banks != 8) continue; printk(BIOS_SPEW, "DIMM%d has 8 banks.\n", i); @@ -1729,8 +1482,8 @@ static void sdram_set_timing_and_control(struct sys_info *sysinfo) /* CL 3, 4, 5 */ 3, 4, 5, /* FSB533, DDR667/533/400 */ 4, 5, 6, /* FSB667, DDR667/533/400 */ - 5, 6, 7, /* FSB800, DDR400/533 */ - 6, 7, 8, /* FSB800, DDR667 */ + 4, 5, 6, /* FSB800, DDR400/533 */ + 5, 6, 7, /* FSB800, DDR667 */ 5, 6, 7, /* FSB1066, DDR400 */ 7, 8, 9, /* FSB1066, DDR533/DDR667 */ }; @@ -3062,7 +2815,7 @@ static void sdram_setup_processor_side(void) void sdram_initialize(int boot_path, const u8 *spd_addresses) { struct sys_info sysinfo; - u8 reg8, cas_mask; + u8 reg8; printk(BIOS_DEBUG, "Setting up RAM controller.\n"); @@ -3080,20 +2833,11 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Check whether we have stacked DIMMs */ sdram_verify_package_type(&sysinfo); - /* Determine common CAS */ - cas_mask = sdram_possible_cas_latencies(&sysinfo); + /* Select common CAS latency and dram frequency */ + select_cas_dramfreq(&sysinfo); - /* Choose Common Frequency */ - sdram_detect_cas_latency_and_ram_speed(&sysinfo, cas_mask); - - /* Determine smallest common tRAS */ - sdram_detect_smallest_tRAS(&sysinfo); - - /* Determine tRP */ - sdram_detect_smallest_tRP(&sysinfo); - - /* Determine tRCD */ - sdram_detect_smallest_tRCD(&sysinfo); + /* Select nRAS, nRP, nRCD, nWR */ + select_dram_timings(&sysinfo); /* Determine smallest refresh period */ sdram_detect_smallest_refresh(&sysinfo); @@ -3101,9 +2845,6 @@ void sdram_initialize(int boot_path, const u8 *spd_addresses) /* Verify all DIMMs support burst length 8 */ sdram_verify_burst_length(&sysinfo); - /* determine tWR */ - sdram_detect_smallest_tWR(&sysinfo); - /* Determine DIMM size parameters (rows, columns banks) */ sdram_detect_dimm_size(&sysinfo); diff --git a/src/northbridge/intel/i945/raminit.h b/src/northbridge/intel/i945/raminit.h index 0554900..56d30e5 100644 --- a/src/northbridge/intel/i945/raminit.h +++ b/src/northbridge/intel/i945/raminit.h @@ -23,6 +23,8 @@ /* Burst length is always 8 */ #define BURSTLENGTH 8 +#include <device/dram/ddr2.h> + struct sys_info { u16 memory_frequency; /* 400, 533 or 667 */ u16 fsb_frequency; /* 945GM: 400, 533 or 667 / 945GC: 533, 800, or 1066 */ @@ -50,14 +52,13 @@ struct sys_info { #define SYSINFO_PACKAGE_PLANAR 0x00 #define SYSINFO_PACKAGE_STACKED 0x01 u8 dimm[2 * DIMM_SOCKETS]; + dimm_attr dimm_decoded[2 * DIMM_SOCKETS]; #define SYSINFO_DIMM_X16DS 0x00 #define SYSINFO_DIMM_X8DS 0x01 #define SYSINFO_DIMM_X16SS 0x02 #define SYSINFO_DIMM_X8DDS 0x03 #define SYSINFO_DIMM_NOT_POPULATED 0x04 - u8 banks[2 * DIMM_SOCKETS]; - u8 banksize[2 * 2 * DIMM_SOCKETS]; const u8 *spd_addresses;

1 0

Patch set updated for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit a2875b6968f3c0287dad388fa6921ad254b7fe1c Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function has a CAS mask as input encoded in the same way as SPD byte 18. It tries to find the fastest frequency at the lowest possible CAS latency. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 86 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 15 +++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index b712192..6d13d85 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,6 +111,21 @@ static u8 spd_get_msbs(u8 c) } /** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_lsbs(u8 c) +{ + int i; + for (i = 0; i < 7; i++) + if (c & (1 << i)) + return i; + + return 0; +} + +/** * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -593,3 +609,73 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas) +{ + int i, found, high_supp_cas, low_supp_cas; + u8 curr_freq, curr_cas; + + const int ddr2_speeds_table[] = { + TCK_200MHZ, + TCK_266MHZ, + TCK_333MHZ, + TCK_400MHZ, + TCK_533MHZ, + TCK_666MHZ, + TCK_700MHZ, + TCK_800MHZ, + }; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i]->cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 1; + } + + high_supp_cas = spd_get_msbs(cas_mask); + low_supp_cas = spd_get_lsbs(cas_mask); + + /* Loop from fast to slow frequency, from low to high CAS latency */ + for (curr_freq = max_freq; + curr_freq >= 0; curr_freq--) { + printram("Trying speed: %d\n", curr_freq); + for (curr_cas = low_supp_cas; + curr_cas <= low_supp_cas; curr_cas++) { + printram(" Trying CAS: %d\n", curr_freq); + found = 1; + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == + SPD_DIMM_TYPE_UNDEFINED) + continue; + + printram(" Testing DIMM: %d\n", i); + if (dimm[i]->cycle_time[curr_cas] == 0) { + printram(" CAS not supported"); + found = 0; + break; + } + + if (dimm[i]->cycle_time[curr_cas] > + ddr2_speeds_table[curr_freq]) { + printram(" Timing too fast\n"); + found = 0; + break; + } + } + if (found) { + *selected_freq = curr_freq; + *selected_cas = curr_cas; + return 0; + } + } + } + + printk(BIOS_DEBUG, "No common CAS Frequency combination possible!\n"); + return 1; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 236be49..d13559e 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -46,6 +46,18 @@ #define TCK_333MHZ 768 #define TCK_266MHZ 960 #define TCK_200MHZ 1280 + +enum dram_freq { + DDR2_200MHZ, + DDR2_266MHZ, + DDR2_333MHZ, + DDR2_400MHZ, + DDR2_533MHZ, + DDR2_666MHZ, + DDR2_700MHZ, + DDR2_800MHZ, +}; + /** @} */ /** @@ -198,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

1 0

Patch set updated for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit 3c7a20cc63b7079f2190247003fc76f25156c25a Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function has a CAS mask as input encoded in the same way as SPD byte 18. It tries to find the fastest frequency at the lowest possible CAS latency. Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 86 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 15 +++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index b712192..8a43c56 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,6 +111,21 @@ static u8 spd_get_msbs(u8 c) } /** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_lsbs(u8 c) +{ + int i; + for (i = 0; i < 7; i++) + if (c & (1 << i)) + return i; + + return 0; +} + +/** * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -593,3 +609,73 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas) +{ + int i, found, high_supp_cas, low_supp_cas; + u8 curr_freq, curr_cas; + + const int ddr2_speeds_table[] = { + TCK_200MHZ, + TCK_266MHZ, + TCK_333MHZ, + TCK_400MHZ, + TCK_533MHZ, + TCK_666MHZ, + TCK_700MHZ, + TCK_800MHZ, + }; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i]->cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 1; + } + + high_supp_cas = spd_get_msbs(cas_mask); + low_supp_cas = spd_get_lsbs(cas_mask); + + /* Loop from fast to slow frequency, from low to high CAS latency */ + for (curr_freq = max_freq; + curr_freq >= 0; curr_freq--) { + printram("Trying speed: %d\n", curr_freq); + for (curr_cas = low_supp_cas; + curr_cas <= low_supp_cas; curr_cas++) { + printram(" Trying CAS: %d\n"; curr_freq); + found = 1; + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == + SPD_DIMM_TYPE_UNDEFINED) + continue; + + printram(" Testing DIMM: %d\n", i); + if (dimm[i]->cycle_time[curr_cas] == 0) { + printram(" CAS not supported"); + found = 0; + break; + } + + if (dimm[i]->cycle_time[curr_cas] > + ddr2_speeds_table[curr_freq]) { + printram(" Timing too fast\n"); + found = 0; + break; + } + } + if (found) { + *selected_freq = curr_freq; + *selected_cas = curr_cas; + return 0; + } + } + } + + printk(BIOS_DEBUG, "No common CAS Frequency combination possible!\n"); + return 1; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 236be49..d13559e 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -46,6 +46,18 @@ #define TCK_333MHZ 768 #define TCK_266MHZ 960 #define TCK_200MHZ 1280 + +enum dram_freq { + DDR2_200MHZ, + DDR2_266MHZ, + DDR2_333MHZ, + DDR2_400MHZ, + DDR2_533MHZ, + DDR2_666MHZ, + DDR2_700MHZ, + DDR2_800MHZ, +}; + /** @} */ /** @@ -198,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +int get_common_freq_cas(u8 max_freq, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

1 0

Patch set updated for coreboot: mb/*/*/cmos.layout: Make multibyte options byte aligned
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18321 -gerrit commit 93f01935a868b1c8fc39e268a5b3936eabb3fcd5 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 8 18:12:31 2017 +0100 mb/*/*/cmos.layout: Make multibyte options byte aligned Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/adi/rcc-dff/cmos.layout | 10 ++++----- .../amd/serengeti_cheetah_fam10/cmos.layout | 3 ++- src/mainboard/asus/kcma-d8/cmos.layout | 6 ++++-- src/mainboard/asus/kfsn4-dre/cmos.layout | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 6 ++++-- src/mainboard/esd/atom15/cmos.layout | 10 ++++----- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 3 ++- src/mainboard/intel/littleplains/cmos.layout | 10 ++++----- src/mainboard/intel/minnowmax/cmos.layout | 10 ++++----- src/mainboard/intel/mohonpeak/cmos.layout | 10 ++++----- src/mainboard/kontron/ktqm77/cmos.layout | 11 +++++----- src/mainboard/lenovo/t400/cmos.layout | 24 ++++++++++------------ src/mainboard/lenovo/x200/cmos.layout | 19 ++++++++--------- src/mainboard/msi/ms9652_fam10/cmos.layout | 3 ++- src/mainboard/pcengines/apu1/cmos.layout | 5 +++-- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 3 ++- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 3 ++- src/mainboard/tyan/s2912_fam10/cmos.layout | 3 ++- 18 files changed, 75 insertions(+), 67 deletions(-) diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ b/src/mainboard/adi/rcc-dff/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index b9dadf4..0bab4c9 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -51,6 +52,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 169af87..d0f6211 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 18c7a3f..e65f7c8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -52,6 +53,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/esd/atom15/cmos.layout +++ b/src/mainboard/esd/atom15/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 37ab3bd..21bbf28 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/littleplains/cmos.layout +++ b/src/mainboard/intel/littleplains/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index b17ee51..7cf1040 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -61,14 +61,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused # coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader 448 64 r 0 write_protected_by_bios diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..3cd076a 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -65,23 +65,21 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb -# coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +# coreboot config options: bootloader +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 2 e 12 hybrid_graphics_mode -946 4 e 11 gfx_uma_size - -# coreboot config options: EC -952 8 h 0 volume +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..59a1c6d 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -65,20 +65,19 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default - -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 8 h 0 volume -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index e0501f6..1c560eb 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -7,8 +7,9 @@ entries 392 1 e 2 boot_option 393 1 e 1 multi_core 394 3 e 3 baud_rate -397 4 e 4 debug_level -# leave 7 bits to make checksummed area end byte-aligned +#397 3 unused +400 4 e 4 debug_level +# leave 4 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum enumerations diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart

1 0

Patch set updated for coreboot: util/nvramtool: Bail out on unaligned multi-byte entries
by Nico Huber 10 Feb '17

10 Feb '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18246 -gerrit commit 256500fcf3fc8afcd0e837395060ee6ba816a0ed Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Jan 26 23:22:46 2017 +0100 util/nvramtool: Bail out on unaligned multi-byte entries coreboot doesn't support CMOS options that are not byte aligned but span multiple bytes. So treat them as error. Change-Id: I2bcff62f153932e9c6646b4ce08e8da1c1532947 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/nvramtool/accessors/layout-bin.c | 6 ++++++ util/nvramtool/accessors/layout-text.c | 6 ++++++ util/nvramtool/layout.c | 3 +++ util/nvramtool/layout.h | 1 + 4 files changed, 16 insertions(+) diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c index 34507c9..fa6344b 100644 --- a/util/nvramtool/accessors/layout-bin.c +++ b/util/nvramtool/accessors/layout-bin.c @@ -481,6 +481,12 @@ static void try_add_cmos_table_entry(cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index bea3b3e..b6cbc2e 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -695,6 +695,12 @@ static void try_add_layout_file_entry(const cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c index 241dd19..6fdb282 100644 --- a/util/nvramtool/layout.c +++ b/util/nvramtool/layout.c @@ -169,6 +169,9 @@ int add_cmos_entry(const cmos_entry_t * e, const cmos_entry_t ** conflict) if (e->length < 1) return LAYOUT_ENTRY_BAD_LENGTH; + if (e->bit % 8 && e->bit / 8 != (e->bit + e->length - 1) / 8) + return LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED; + if ((new_entry = (cmos_entry_item_t *) malloc(sizeof(*new_entry))) == NULL) out_of_memory(); diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index 8a39ab9..bde0603 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -40,6 +40,7 @@ #define LAYOUT_CHECKSUM_OVERLAPS_SUMMED_AREA (LAYOUT_RESULT_START + 7) #define LAYOUT_SUMMED_AREA_OUT_OF_RANGE (LAYOUT_RESULT_START + 8) #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) +#define LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED (LAYOUT_RESULT_START + 10) typedef enum { CMOS_ENTRY_ENUM = 'e',

1 0

Patch set updated for coreboot: mb/*/*/cmos.layout: Make multibyte options byte aligned
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18321 -gerrit commit e66d63d43ae7ea4e2eb81a4d9cbd17f8f9392258 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 8 18:12:31 2017 +0100 mb/*/*/cmos.layout: Make multibyte options byte aligned Changes the offsets of some options so that options that span multiple bytes are byte aligned. To make the cmos.layout file more consistent some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/adi/rcc-dff/cmos.layout | 10 ++++----- .../amd/serengeti_cheetah_fam10/cmos.layout | 3 ++- src/mainboard/asus/kcma-d8/cmos.layout | 6 ++++-- src/mainboard/asus/kfsn4-dre/cmos.layout | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 6 ++++-- src/mainboard/esd/atom15/cmos.layout | 10 ++++----- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 3 ++- src/mainboard/intel/littleplains/cmos.layout | 10 ++++----- src/mainboard/intel/minnowmax/cmos.layout | 10 ++++----- src/mainboard/intel/mohonpeak/cmos.layout | 10 ++++----- src/mainboard/kontron/ktqm77/cmos.layout | 11 +++++----- src/mainboard/lenovo/t400/cmos.layout | 24 ++++++++++------------ src/mainboard/lenovo/x200/cmos.layout | 19 ++++++++--------- src/mainboard/msi/ms9652_fam10/cmos.layout | 3 ++- src/mainboard/pcengines/apu1/cmos.layout | 3 ++- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 3 ++- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 3 ++- src/mainboard/tyan/s2912_fam10/cmos.layout | 3 ++- 18 files changed, 74 insertions(+), 66 deletions(-) diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ b/src/mainboard/adi/rcc-dff/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index b9dadf4..0bab4c9 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -51,6 +52,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 169af87..d0f6211 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 18c7a3f..e65f7c8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -52,6 +53,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/esd/atom15/cmos.layout +++ b/src/mainboard/esd/atom15/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 37ab3bd..21bbf28 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/littleplains/cmos.layout +++ b/src/mainboard/intel/littleplains/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index b17ee51..7cf1040 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -61,14 +61,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused # coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader 448 64 r 0 write_protected_by_bios diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..3cd076a 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -65,23 +65,21 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb -# coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +# coreboot config options: bootloader +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 2 e 12 hybrid_graphics_mode -946 4 e 11 gfx_uma_size - -# coreboot config options: EC -952 8 h 0 volume +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..59a1c6d 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -65,20 +65,19 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default - -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 8 h 0 volume -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index e0501f6..959a2d3 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -7,7 +7,8 @@ entries 392 1 e 2 boot_option 393 1 e 1 multi_core 394 3 e 3 baud_rate -397 4 e 4 debug_level +#397 3 unused +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart

1 0

Patch set updated for coreboot: soc/intel/apollolake: Use intel/common/xhci driver
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18222 -gerrit commit 4a4e5bced484690d9e01d2c06562fbbc2ae6b9ba Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:54:58 2017 +0530 soc/intel/apollolake: Use intel/common/xhci driver Change-Id: If161b1e11041ea7a380222ba555f14cd114de617 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 2 +- src/soc/intel/apollolake/xhci.c | 105 ---------------------------------- 3 files changed, 2 insertions(+), 106 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b37cde6..afd617e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_XHCI_DRIVER select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5a65f43..1284708 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../common/block/* bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c @@ -82,7 +83,6 @@ ramstage-y += reset.c ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c -ramstage-y += xhci.c postcar-y += flash_ctrlr.c postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c deleted file mode 100644 index 7b3cb46..0000000 --- a/src/soc/intel/apollolake/xhci.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> -#include <soc/pci_ids.h> -#include <timer.h> - -#define DUAL_ROLE_CFG0 0x80d8 -# define DRD_CONFIG_MASK (0x3 << 0) -# define DRD_CONFIG_DYNAMIC (0x0 << 0) -# define DRD_CONFIG_HOST (0x1 << 0) -# define DRD_CONFIG_DEVICE (0x2 << 0) -# define SW_VBUS_VALID_MASK (1 << 24) -# define SW_VBUS_DEASSERT_VALID (0 << 24) -# define SW_VBUS_ASSERT_VALID (1 << 24) -# define SW_IDPIN_EN_MASK (1 << 21) -# define SW_IDPIN_DIS (0 << 21) -# define SW_IDPIN_EN (1 << 21) -# define SW_IDPIN_MASK (1 << 20) -# define SW_IDPIN_HOST (0 << 20) -# define SW_IDPIN_DEVICE (1 << 20) -#define DUAL_ROLE_CFG1 0x80dc -# define DRD_MODE_MASK (1 << 29) -# define DRD_MODE_DEVICE (0 << 29) -# define DRD_MODE_HOST (1 << 29) - -static void configure_host_mode_port0(struct device *dev) -{ - uint32_t *cfg0; - uint32_t *cfg1; - const struct resource *res; - uint32_t reg; - struct device *xdci_dev = XDCI_DEV; - struct stopwatch sw; - - /* - * Only default to host mode if the xdci device is present and - * enabled. If it's disabled assume the switch was already done - * in FSP. - */ - if (xdci_dev == NULL || !xdci_dev->enabled) - return; - - printk(BIOS_INFO, "Putting port 0 into host mode.\n"); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); - cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); - - reg = read32(cfg0); - reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); - reg &= ~(SW_VBUS_VALID_MASK); - reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; - reg |= SW_VBUS_DEASSERT_VALID; - write32(cfg0, reg); - - stopwatch_init_msecs_expire(&sw, 10); - - /* Wait for the host mode status bit. */ - while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { - if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "Timed out waiting for host mode.\n"); - break; - } - } - - printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -static void xhci_init(struct device *dev) -{ - configure_host_mode_port0(dev); -} - -static const struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = xhci_init, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_APOLLOLAKE_XHCI, -};

1 0

Patch set updated for coreboot: soc/intel/skylake: Use intel/common/xhci driver
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18223 -gerrit commit 7a7c00125da838d71a855d0c2e92665120b03723 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:56:12 2017 +0530 soc/intel/skylake: Use intel/common/xhci driver Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 2 +- src/soc/intel/skylake/xhci.c | 43 -------------------------------------- 3 files changed, 2 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..4fca67e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_XHCI_DRIVER select SMM_TSEG select SMP select SSE2 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..6ae5897 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../common/block/* bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S @@ -90,7 +91,6 @@ ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c -ramstage-y += xhci.c smm-y += cpu_info.c smm-y += gpio.c diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c deleted file mode 100644 index 6b4a19a..0000000 --- a/src/soc/intel/skylake/xhci.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> -#include <soc/cpu.h> - -static struct device_operations usb_xhci_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d2f, /* SunRisePoint LP */ - 0 -}; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -};

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Patch set updated for coreboot: soc/intel/common/block: Add Intel XHCI driver support
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221 -gerrit commit bf904f48204c8db50014824a39933a4e85f6afb5 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:53:10 2017 +0530 soc/intel/common/block: Add Intel XHCI driver support Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/Kconfig | 3 ++ src/soc/intel/common/block/include/xhci.h | 22 ++++++++++++++ src/soc/intel/common/block/xhci/Kconfig | 4 +++ src/soc/intel/common/block/xhci/Makefile.inc | 7 +++++ src/soc/intel/common/block/xhci/xhci.c | 44 ++++++++++++++++++++++++++++ 5 files changed, 80 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 436964c..e6e8e03 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -471,6 +471,9 @@ source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" +# Intel SoC Family IP model Kconfig +source "src/soc/intel/common/block/*/Kconfig" + source "src/southbridge/intel/common/firmware/Kconfig" source "src/vboot/Kconfig" source "src/vendorcode/*/Kconfig" diff --git a/src/soc/intel/common/block/include/xhci.h b/src/soc/intel/common/block/include/xhci.h new file mode 100644 index 0000000..1ad1c4e --- /dev/null +++ b/src/soc/intel/common/block/include/xhci.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __XHCI_H +#define __XHCI_H + +void xhci_init(struct device *dev); + +#endif /* __XHCI_H */ + diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig new file mode 100644 index 0000000..7070dd3 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_XHCI_DRIVER + bool + help + Intel Processor XHCI Driver support diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..826f3da --- /dev/null +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_XHCI_DRIVER),y) + +ramstage-y += xhci.c + +CPPFLAGS_common += -I$(src)/soc/intel/common/block/include + +endif diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c new file mode 100644 index 0000000..2bec54f --- /dev/null +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -0,0 +1,44 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <xhci.h> + +__attribute__((weak)) void xhci_init(struct device *dev) { /* no-op */ } + +static struct device_operations usb_xhci_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .init = xhci_init, +}; + +static const unsigned short pci_device_ids[] = { + 0x5aa8, /* ApolloLake */ + 0x31a8, /* GLK */ + 0x9d2f, /* SunRisePoint LP */ + 0 +}; + +static const struct pci_driver pch_usb_xhci __pci_driver = { + .ops = &usb_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

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coreboot-gerrit February 2017