coreboot-gerrit February 2017

coreboot-gerrit@coreboot.org

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1019 discussions

Patch set updated for coreboot: mainboard/eve: select SOC_INTEL_KABYLAKE
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18314 -gerrit commit b5dffa61d36f23b552795e5ac24ef285037a973b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 16:34:08 2017 +0530 mainboard/eve: select SOC_INTEL_KABYLAKE eve is based on Kabylake SoC hence select the appropriate config. Change-Id: I756dda5a1924e83a02ac1cebb1907884f436a13f Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/eve/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/eve/Kconfig b/src/mainboard/google/eve/Kconfig index e83e7d9..95ad4de 100644 --- a/src/mainboard/google/eve/Kconfig +++ b/src/mainboard/google/eve/Kconfig @@ -13,7 +13,7 @@ config BOARD_SPECIFIC_OPTIONS select MAINBOARD_HAS_I2C_TPM_CR50 select MAINBOARD_HAS_TPM2 select MAINBOARD_USES_FSP2_0 - select SOC_INTEL_SKYLAKE + select SOC_INTEL_KABYLAKE select TPM2 config CHROMEOS

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Patch set updated for coreboot: mainboard/poppy: select SOC_INTEL_KABYLAKE
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18313 -gerrit commit faffe3d7e073a15446764148b091812d5583da4e Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 16:32:20 2017 +0530 mainboard/poppy: select SOC_INTEL_KABYLAKE poppy is based on Kabylake SoC hence select the appropriate config. Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/mainboard/google/poppy/Kconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 742eb64..f1749e3 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -10,7 +10,7 @@ config BOARD_SPECIFIC_OPTIONS select HAVE_ACPI_TABLES select MAINBOARD_HAS_CHROMEOS select MAINBOARD_USES_FSP2_0 - select SOC_INTEL_SKYLAKE + select SOC_INTEL_KABYLAKE config CHROMEOS select EC_GOOGLE_CHROMEEC_SWITCHES

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Patch set updated for coreboot: soc/intel/skylake: Add config option for Kabylake
by Rizwan Qureshi 10 Feb '17

10 Feb '17

Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18312 -gerrit commit 6328b5493c14f928b91f4392f2614f081a17682b Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Date: Thu Feb 9 15:57:45 2017 +0530 soc/intel/skylake: Add config option for Kabylake Currently there is no distinction between mainboards using Skylake or Kabylake SoC, Add a config option for Kabylake SoC to allow mainboards to explicitly select if they are using it. Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4 Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com> --- src/soc/intel/skylake/Kconfig | 7 +++++++ 1 file changed, 7 insertions(+) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..11953a6 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -3,6 +3,13 @@ config SOC_INTEL_SKYLAKE help Intel Skylake support +config SOC_INTEL_KABYLAKE + bool + default n + select SOC_INTEL_SKYLAKE + help + Intel Kabylake support + if SOC_INTEL_SKYLAKE config CPU_SPECIFIC_OPTIONS

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New patch to review for coreboot: mainboard/google/snappy: Update DPTF settings
by Wisley Chen 10 Feb '17

10 Feb '17

Wisley Chen (wisley.chen(a)quantatw.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18318 -gerrit commit 4e2d61a566618f8d5c9e1ca365a8d0412834d26a Author: Wisley Chen <wisley.chen(a)quantatw.com> Date: Fri Feb 10 04:43:29 2017 -0500 mainboard/google/snappy: Update DPTF settings Update DPTF parameters based on thermal team test result. 1. Update TSR2 trigger points. TSR2 passive point: 70, critical point: 90 2. Set PL2 Max to 15W. BUG=chrome-os-partner:61383 BRANCH=reef TEST=build, boot on snappy, and verified by thermal team Change-Id: I8d01d6c1d7eabd359ceb131f3cd10965d4ac2c42 Signed-off-by: Wisley Chen <wisley.chen(a)quantatw.com> --- .../google/reef/variants/snappy/include/variant/acpi/dptf.asl | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl index a233c92..adf9828 100644 --- a/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/snappy/include/variant/acpi/dptf.asl @@ -34,8 +34,8 @@ #define DPTF_TSR2_SENSOR_ID 2 #define DPTF_TSR2_SENSOR_NAME "Charger" -#define DPTF_TSR2_PASSIVE 90 -#define DPTF_TSR2_CRITICAL 100 +#define DPTF_TSR2_PASSIVE 70 +#define DPTF_TSR2_CRITICAL 90 #define DPTF_ENABLE_CHARGER @@ -81,7 +81,7 @@ Name (MPPC, Package () Package () { /* Power Limit 2 */ 1, /* PowerLimitIndex, 1 for Power Limit 2 */ 8000, /* PowerLimitMinimum */ - 8000, /* PowerLimitMaximum */ + 15000, /* PowerLimitMaximum */ 1000, /* TimeWindowMinimum */ 1000, /* TimeWindowMaximum */ 1000 /* StepSize */

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Patch set updated for coreboot: soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18288 -gerrit commit cd358eadee3c2459f68a70733f06d0a5ce2b43a3 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Feb 3 19:05:27 2017 +0530 soc/intel/skylake: Enable ACPI PM timer emulation on all CPUs This patch enables ACPI timer emulation on all the logical cpus. BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Verify MSR 0x121 gets programmed on all logical cpus during CB MP Init. Change-Id: I2246cdfe1f60fd359b0a0eda89b4a45b5554dc4a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/cpu.c | 19 ++++++++++++++++++- src/soc/intel/skylake/include/soc/msr.h | 5 +++++ 2 files changed, 23 insertions(+), 1 deletion(-) diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index 684680d..ffb9f9a 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -37,6 +37,7 @@ #include <soc/cpu.h> #include <soc/msr.h> #include <soc/pci_devs.h> +#include <soc/pm.h> #include <soc/ramstage.h> #include <soc/smm.h> #include <soc/systemagent.h> @@ -351,6 +352,19 @@ static void configure_mca(void) wrmsr(IA32_MC0_STATUS + (i * 4), msr); } +/* The emulated ACPI timer allows disabling of the ACPI timer + * (PM1_TMR) to have no impart on the system. + */ +static void configure_emulation_timer(void) +{ + msr_t msr; + + msr.hi = uCODE_TMR_EMULATION; + msr.lo = (EMULATE_DELAY_VALUE << EMULATE_DELAY_OFFSET_VALUE) | + EMULATE_PM_TMR_EN | (ACPI_BASE_ADDRESS + PM1_TMR); + wrmsr(MSR_EMULATE_PM_TIMER, msr); +} + /* All CPUs including BSP will run the following function. */ static void cpu_core_init(device_t cpu) { @@ -367,6 +381,9 @@ static void cpu_core_init(device_t cpu) /* Configure Intel Speed Shift */ configure_isst(); + /* Enable ACPI Timer Emulation via MSR 0x121 */ + configure_emulation_timer(); + /* Enable Direct Cache Access */ configure_dca_cap(); @@ -510,4 +527,4 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) * Do CPU MP Init before FSP Silicon Init */ BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); -BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); \ No newline at end of file +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); diff --git a/src/soc/intel/skylake/include/soc/msr.h b/src/soc/intel/skylake/include/soc/msr.h index 4d295e1..405b13f 100644 --- a/src/soc/intel/skylake/include/soc/msr.h +++ b/src/soc/intel/skylake/include/soc/msr.h @@ -26,6 +26,11 @@ #define PLATFORM_INFO_SET_TDP (1 << 29) #define MSR_PMG_CST_CONFIG_CONTROL 0xe2 #define MSR_PMG_IO_CAPTURE_BASE 0xe4 +#define MSR_EMULATE_PM_TIMER 0x121 +#define EMULATE_PM_TMR_EN (1 << 16) +#define uCODE_TMR_EMULATION 0x262E8B51 +#define EMULATE_DELAY_OFFSET_VALUE 20 +#define EMULATE_DELAY_VALUE 0x13 #define MSR_FEATURE_CONFIG 0x13c #define SMM_MCA_CAP_MSR 0x17d #define SMM_CPU_SVRSTR_BIT 57

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Patch set updated for coreboot: soc/intel/skylake: Perform CPU MP Init before FSP-S Init
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18287 -gerrit commit 4426428d1a6de812f94e7dd39f9638940b904a0a Author: Subrata Banik <subrata.banik(a)intel.com> Date: Fri Feb 3 18:57:49 2017 +0530 soc/intel/skylake: Perform CPU MP Init before FSP-S Init As per BWG, CPU MP Init (loading ucode) should be done prior to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry (before FSP-S call). BUG=chrome-os-partner:62438 BRANCH=NONE TEST=Boot to OS with all threads enabled. Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/chip.c | 4 +-- src/soc/intel/skylake/chip_fsp20.c | 4 +-- src/soc/intel/skylake/cpu.c | 33 +++++++++++++++------- src/soc/intel/skylake/include/fsp11/soc/ramstage.h | 3 +- src/soc/intel/skylake/include/fsp20/soc/ramstage.h | 3 +- 5 files changed, 29 insertions(+), 18 deletions(-) diff --git a/src/soc/intel/skylake/chip.c b/src/soc/intel/skylake/chip.c index c64a8df..060c4ee 100644 --- a/src/soc/intel/skylake/chip.c +++ b/src/soc/intel/skylake/chip.c @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -49,7 +49,7 @@ static struct device_operations pci_domain_ops = { }; static struct device_operations cpu_bus_ops = { - .init = &soc_init_cpus, + .init = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index ebd3134..f1a32c4 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -1,7 +1,7 @@ /* * This file is part of the coreboot project. * - * Copyright (C) 2016 Intel Corporation. + * Copyright (C) 2016-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -59,7 +59,7 @@ static struct device_operations cpu_bus_ops = { .read_resources = DEVICE_NOOP, .set_resources = DEVICE_NOOP, .enable_resources = DEVICE_NOOP, - .init = &soc_init_cpus, + .init = DEVICE_NOOP, #if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES) .acpi_fill_ssdt_generator = generate_cpu_entries, #endif diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c index e8616f0..684680d 100644 --- a/src/soc/intel/skylake/cpu.c +++ b/src/soc/intel/skylake/cpu.c @@ -3,7 +3,7 @@ * * Copyright (C) 2007-2009 coresystems GmbH * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -397,13 +398,6 @@ static const struct cpu_driver driver __cpu_driver = { static const void *microcode_patch; static int ht_disabled; -static void pre_mp_init(void) -{ - /* Setup MTRRs based on physical address size. */ - x86_setup_mtrrs_with_detect(); - x86_mtrr_check(); -} - static int get_cpu_count(void) { msr_t msr; @@ -463,7 +457,12 @@ static void post_mp_init(void) } static const struct mp_ops mp_ops = { - .pre_mp_init = pre_mp_init, + /* + * Skip Pre MP init MTRR programming as MTRRs are mirrored from BSP, + * that are set prior to ramstage. + * Real MTRRs programming are being done after resource allocation. + */ + .pre_mp_init = NULL, .get_cpu_count = get_cpu_count, .get_smm_info = smm_info, .get_microcode_info = get_microcode_info, @@ -474,8 +473,9 @@ static const struct mp_ops mp_ops = { .post_mp_init = post_mp_init, }; -void soc_init_cpus(device_t dev) +static void soc_init_cpus(void *unused) { + device_t dev = dev_find_path(NULL, DEVICE_PATH_CPU_CLUSTER); struct bus *cpu_bus = dev->link_list; if (mp_init_with_smm(cpu_bus, &mp_ops)) { @@ -486,6 +486,13 @@ void soc_init_cpus(device_t dev) configure_thermal_target(); } +/* Ensure to re-program all MTRRs based on DRAM resource settings */ +static void soc_post_cpus_init(void *unused) +{ + if (mp_run_on_all_cpus(&x86_setup_mtrrs_with_detect, 1000) < 0) + printk(BIOS_ERR, "MTRR programming failure\n"); +} + int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) { msr_t msr; @@ -498,3 +505,9 @@ int soc_skip_ucode_update(u32 current_patch_id, u32 new_patch_id) msr = rdmsr(MTRR_CAP_MSR); return (msr.lo & PRMRR_SUPPORTED) && (current_patch_id == new_patch_id - 1); } + +/* + * Do CPU MP Init before FSP Silicon Init + */ +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT_CHIPS, BS_ON_ENTRY, soc_init_cpus, NULL); +BOOT_STATE_INIT_ENTRY(BS_DEV_INIT, BS_ON_EXIT, soc_post_cpus_init, NULL); \ No newline at end of file diff --git a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h index 8df7796..f1a9e53 100644 --- a/src/soc/intel/skylake/include/fsp11/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp11/soc/ramstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +29,6 @@ void soc_irq_settings(FSP_SIL_UPD *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); -void soc_init_cpus(device_t dev); const char *soc_acpi_name(struct device *dev); int init_igd_opregion(igd_opregion_t *igd_opregion); extern struct pci_operations soc_pci_ops; diff --git a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h index 0ae87f4..136c4f2 100644 --- a/src/soc/intel/skylake/include/fsp20/soc/ramstage.h +++ b/src/soc/intel/skylake/include/fsp20/soc/ramstage.h @@ -2,7 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. + * Copyright (C) 2015-2017 Intel Corporation. * * This program is free software; you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -29,7 +29,6 @@ void mainboard_silicon_init_params(FSP_S_CONFIG *params); void pch_enable_dev(device_t dev); void soc_init_pre_device(void *chip_info); -void soc_init_cpus(device_t dev); void soc_irq_settings(FSP_SIL_UPD *params); const char *soc_acpi_name(struct device *dev);

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New patch to review for coreboot: mainboard/google/reef: Increase PL1 sampling period
by Sumeet R Pawnikar 10 Feb '17

10 Feb '17

Sumeet R Pawnikar (sumeet.r.pawnikar(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18317 -gerrit commit 518e565ecb25b333790a3b94b2a6043271c8900e Author: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> Date: Fri Feb 10 11:13:36 2017 +0530 mainboard/google/reef: Increase PL1 sampling period Increased PL1 sampling period value to 15 seconds for TSR1 sensor. BUG=chrome-os-partner:60038 BRANCH=reef TEST=Built and tested on electro system Change-Id: I5cdebb08e00f0f28b88f1c6b2b1cafaeb8cdb453 Signed-off-by: Sumeet Pawnikar <sumeet.r.pawnikar(a)intel.com> --- .../google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl index dba182e..0addae8 100644 --- a/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl +++ b/src/mainboard/google/reef/variants/baseboard/include/baseboard/acpi/dptf.asl @@ -61,7 +61,7 @@ Name (DTRT, Package () { #endif /* CPU Effect on Temp Sensor 1 */ - Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 80, 0, 0, 0, 0 }, + Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR1, 100, 150, 0, 0, 0, 0 }, /* CPU Effect on Temp Sensor 2 */ Package () { \_SB.PCI0.TCPU, \_SB.DPTF.TSR2, 100, 1200, 0, 0, 0, 0 },

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Patch set updated for coreboot: util/lint: Don't check license text for files with under 5 lines
by Martin Roth 10 Feb '17

10 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18316 -gerrit commit bbaf4d38ffc78197b47dd0373b9bd70c9ce29c01 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 16:44:24 2017 -0800 util/lint: Don't check license text for files with under 5 lines Change-Id: I7c1e3cf558d447838819b4d6a63d93d48d5f13e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-000-license-headers | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 0d2a3af..e705929 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -93,8 +93,10 @@ check_for_license '"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES' check_for_license 'No license required' for file in $headerlist; do - #verify the file exists, and has content that requires a header - if [ -f "$file" ] && [ "$(wc -l < "$file")" -ne 0 ]; then + # Verify the file exists, and has content that requires a header + # This assumes that a file that has 4 lines or fewer is not notable + # enough to require a license. + if [ -f "$file" ] && [ "$(wc -l < "$file")" -gt 4 ]; then echo "$file has no recognized license header." fi done

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Patch set updated for coreboot: mainboard/intel: Add MinnowBoard 3
by Martin Roth 10 Feb '17

10 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18298 -gerrit commit 223a73dc503871f770939d4f4e976219d0dd8439 Author: Brenton Dong <brenton.m.dong(a)intel.com> Date: Mon Feb 6 16:07:27 2017 -0700 mainboard/intel: Add MinnowBoard 3 This commit adds the initial scaffolding for the MinnowBoard 3 with Apollo Lake silicon. This mainboard is based on Intel's Leafhill CRB with Apollo Lake silicon. In a first step, it concerns only a copy of intel/leafhill directory with name changes. Special adaptations for MinnowBoard 3 mainboard will follow in separate commits. Change-Id: I7563fe37c89511c7035c5bffc9b034b379cfcaf4 Signed-off-by: Brenton Dong <brenton.m.dong(a)intel.com> --- src/mainboard/intel/minnow3/Kconfig | 20 +++ src/mainboard/intel/minnow3/Kconfig.name | 2 + src/mainboard/intel/minnow3/Makefile.inc | 3 + src/mainboard/intel/minnow3/acpi_tables.c | 1 + src/mainboard/intel/minnow3/board_info.txt | 6 + src/mainboard/intel/minnow3/bootblock.c | 22 +++ src/mainboard/intel/minnow3/brd_gpio.h | 62 ++++++++ src/mainboard/intel/minnow3/devicetree.cb | 230 +++++++++++++++++++++++++++++ src/mainboard/intel/minnow3/dsdt.asl | 42 ++++++ src/mainboard/intel/minnow3/mainboard.c | 25 ++++ src/mainboard/intel/minnow3/minnow3.fmd | 40 +++++ src/mainboard/intel/minnow3/romstage.c | 119 +++++++++++++++ 12 files changed, 572 insertions(+) diff --git a/src/mainboard/intel/minnow3/Kconfig b/src/mainboard/intel/minnow3/Kconfig new file mode 100644 index 0000000..3a5f7c7 --- /dev/null +++ b/src/mainboard/intel/minnow3/Kconfig @@ -0,0 +1,20 @@ +if BOARD_INTEL_MINNOW3 + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_INTEL_APOLLOLAKE + select BOARD_ROMSIZE_KB_16384 + select HAVE_ACPI_TABLES +# select HAVE_INTEL_FIRMWARE +# select HAVE_ME_BIN +# select LOCK_MANAGEMENT_ENGINE + +config MAINBOARD_DIR + string + default intel/minnow3 + +config MAINBOARD_PART_NUMBER + string + default "Minnow3" + +endif # BOARD_INTEL_MINNOW3 diff --git a/src/mainboard/intel/minnow3/Kconfig.name b/src/mainboard/intel/minnow3/Kconfig.name new file mode 100644 index 0000000..a62f36f --- /dev/null +++ b/src/mainboard/intel/minnow3/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_INTEL_MINNOW3 + bool "Minnow3" diff --git a/src/mainboard/intel/minnow3/Makefile.inc b/src/mainboard/intel/minnow3/Makefile.inc new file mode 100644 index 0000000..9e3e892 --- /dev/null +++ b/src/mainboard/intel/minnow3/Makefile.inc @@ -0,0 +1,3 @@ +bootblock-y += bootblock.c + +ramstage-y += mainboard.c diff --git a/src/mainboard/intel/minnow3/acpi_tables.c b/src/mainboard/intel/minnow3/acpi_tables.c new file mode 100644 index 0000000..158af61 --- /dev/null +++ b/src/mainboard/intel/minnow3/acpi_tables.c @@ -0,0 +1 @@ +/*Blank file required by build system assumptions of this file being present.*/ diff --git a/src/mainboard/intel/minnow3/board_info.txt b/src/mainboard/intel/minnow3/board_info.txt new file mode 100644 index 0000000..0b891a2 --- /dev/null +++ b/src/mainboard/intel/minnow3/board_info.txt @@ -0,0 +1,6 @@ +Vendor name: Intel +Board name: MinnowBoard 3 +Category: eval +ROM protocol: SPI +ROM socketed: n +Flashrom support: y diff --git a/src/mainboard/intel/minnow3/bootblock.c b/src/mainboard/intel/minnow3/bootblock.c new file mode 100644 index 0000000..3de44a8 --- /dev/null +++ b/src/mainboard/intel/minnow3/bootblock.c @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <bootblock_common.h> +#include <soc/lpc.h> + +void bootblock_mainboard_init(void) +{ + lpc_configure_pads(); +} diff --git a/src/mainboard/intel/minnow3/brd_gpio.h b/src/mainboard/intel/minnow3/brd_gpio.h new file mode 100644 index 0000000..33b839b --- /dev/null +++ b/src/mainboard/intel/minnow3/brd_gpio.h @@ -0,0 +1,62 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015-2016 Intel Corporation. All Rights Reserved. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <soc/gpio.h> + +#if ENV_ROMSTAGE + +static const struct pad_config gpio_table[] = { + PAD_CFG_NF(GPIO_134, NATIVE, DEEP, NF2), /* ISH_I2C0_SDA/IO-OD */ + PAD_CFG_NF(GPIO_135, NATIVE, DEEP, NF2), /* ISH_I2C0_SCL/IO-OD */ + PAD_CFG_NF(GPIO_136, NATIVE, DEEP, NF2), /* ISH_I2C1_SDA/IO-OD */ + PAD_CFG_NF(GPIO_137, NATIVE, DEEP, NF2), /* ISH_I2C1_SCL/IO-OD */ + + PAD_CFG_NF(GPIO_0, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_1, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_2, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_3, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_4, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_5, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_6, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + /* EXP_I2C_SDA and I2C_PSS_SDA and I2C_2_SDA_IOEXP */ + PAD_CFG_NF(GPIO_7, NATIVE, DEEP, NF1), + /* EXP_I2C_SCL and I2C_PSS_SCL and I2C_2_SCL_IOEXP */ + PAD_CFG_NF(GPIO_8, NATIVE, DEEP, NF1), + + PAD_CFG_GPO(GPIO_152, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_19, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_13, 0, DEEP), /* PERST# */ + PAD_CFG_GPO(GPIO_17, 1, DEEP), /* PFET */ + PAD_CFG_GPO(GPIO_15, 0, DEEP), /* PERST# */ + + PAD_CFG_NF(GPIO_210, NATIVE, DEEP, NF1), /* CLKREQ# */ + + PAD_CFG_NF(SMB_CLK, NATIVE, DEEP, NF1), + PAD_CFG_NF(SMB_DATA, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_ILB_SERIRQ, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKOUT1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD0, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD1, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD2, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_AD3, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_CLKRUNB, NATIVE, DEEP, NF1), + PAD_CFG_NF(LPC_FRAMEB, NATIVE, DEEP, NF1), +}; + +#endif diff --git a/src/mainboard/intel/minnow3/devicetree.cb b/src/mainboard/intel/minnow3/devicetree.cb new file mode 100644 index 0000000..2ccf277 --- /dev/null +++ b/src/mainboard/intel/minnow3/devicetree.cb @@ -0,0 +1,230 @@ +chip soc/intel/apollolake + + device cpu_cluster 0 on + device lapic 0 on end + end + + register "pcie_rp0_clkreq_pin" = "0" # wifi/bt + # Disable unused clkreq of PCIe root ports + register "pcie_rp1_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp2_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp3_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp4_clkreq_pin" = "CLKREQ_DISABLED" + register "pcie_rp5_clkreq_pin" = "CLKREQ_DISABLED" + + # GPIO for PERST_0 + # If the Board has PERST_0 signal, assign the GPIO + # If the Board does not have PERST_0, assign GPIO_PRT0_UDEF + register "prt0_gpio" = "GPIO_122" + + # EMMC TX DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [14:8] steps of delay for HS400, each 125ps. + # [6:0] steps of delay for SDR104/HS200, each 125ps. + register "emmc_tx_data_cntl1" = "0x0C16" + + # EMMC TX DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_tx_data_cntl2" = "0x28162828" + + # EMMC RX CMD/DATA Delay 1 + # Refer to EDS-Vol2-22.3. + # [30:24] steps of delay for SDR50, each 125ps. + # [22:16] steps of delay for DDR50, each 125ps. + # [14:8] steps of delay for SDR25/HS50, each 125ps. + # [6:0] steps of delay for SDR12, each 125ps. + register "emmc_rx_cmd_data_cntl1" = "0x00181717" + + # EMMC RX CMD/DATA Delay 2 + # Refer to EDS-Vol2-22.3. + # [17:16] stands for Rx Clock before Output Buffer + # [14:8] steps of delay for Auto Tuning Mode, each 125ps. + # [6:0] steps of delay for HS200, each 125ps. + register "emmc_rx_cmd_data_cntl2" = "0x10008" + + # Enable DPTF + register "dptf_enable" = "1" + + # PL1 override 12000 mW: the energy calculation is wrong with the + # current VR solution. Experiments show that SoC TDP max (6W) can + # be reached when RAPL PL1 is set to 12W. + register "tdp_pl1_override_mw" = "12000" + # Set RAPL PL2 to 15W. + register "tdp_pl2_override_mw" = "15000" + + # Enable Audio Clock and Power gating + register "hdaudio_clk_gate_enable" = "1" + register "hdaudio_pwr_gate_enable" = "1" + register "hdaudio_bios_config_lockdown" = "1" + + # Enable lpss s0ix + register "lpss_s0ix_enable" = "1" + + # GPE configuration + # Note that GPE events called out in ASL code rely on this + # route, i.e., if this route changes then the affected GPE + # offset bits also need to be changed. This sets the PMC register + # GPE_CFG fields. + register "gpe0_dw1" = "PMC_GPE_N_31_0" + register "gpe0_dw2" = "PMC_GPE_N_63_32" + register "gpe0_dw3" = "PMC_GPE_SW_31_0" + + # Enable I2C0 for audio codec at 400kHz + register "i2c[0]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 104, + .fall_time_ns = 52, + }" + + # Enable I2C2 bus early for TPM at 400kHz + register "i2c[2]" = "{ + .early_init = 1, + .speed = I2C_SPEED_FAST, + .rise_time_ns = 57, + .fall_time_ns = 28, + }" + + # touchscreen at 400kHz + register "i2c[3]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 76, + .fall_time_ns = 164, + }" + + # trackpad at 400kHz + register "i2c[4]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 114, + .fall_time_ns = 164, + }" + + # digitizer at 400kHz + register "i2c[5]" = "{ + .speed = I2C_SPEED_FAST, + .rise_time_ns = 152, + .fall_time_ns = 30, + }" + + # Minimum SLP S3 assertion width 28ms. + register "slp_s3_assertion_width_usecs" = "28000" + + device domain 0 on + device pci 00.0 on end # - Host Bridge + device pci 00.1 on end # - DPTF + device pci 00.2 on end # - NPK + device pci 02.0 on end # - Gen + device pci 03.0 on end # - Iunit + device pci 0d.0 on end # - P2SB + device pci 0d.1 on end # - PMC + device pci 0d.2 on end # - SPI + device pci 0d.3 on end # - Shared SRAM + device pci 0e.0 on # - Audio + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_76)" + register "sdmode_delay" = "5" + device generic 0 on end + end + end + device pci 11.0 off end # - ISH + device pci 12.0 off end # - SATA + device pci 13.0 off end # - Root Port 2 - PCIe-A 0 + device pci 13.1 off end # - Root Port 3 - PCIe-A 1 + device pci 13.2 off end # - Root Port 4 - PCIe-A 2 + device pci 13.3 off end # - Root Port 5 - PCIe-A 3 + device pci 14.0 on + chip drivers/intel/wifi + register "wake" = "GPE0_DW3_00" + device pci 00.0 on end + end + end # - Root Port 0 - PCIe-B 0 - Wifi + device pci 14.1 off end # - Root Port 1 - PCIe-B 1 + device pci 15.0 on end # - XHCI + device pci 15.1 off end # - XDCI + device pci 16.0 on # - I2C 0 + chip drivers/i2c/da7219 + register "irq" = "IRQ_LEVEL_LOW(GPIO_116_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1a on end + end + end + device pci 16.1 on end # - I2C 1 + device pci 16.2 on + chip drivers/i2c/tpm + register "hid" = ""GOOG0005"" + register "irq" = "IRQ_EDGE_LOW(GPIO_28_IRQ)" + device i2c 50 on end + end + end # - I2C 2 + device pci 16.3 on + chip drivers/i2c/generic + register "hid" = ""ELAN0001"" + register "desc" = ""ELAN Touchscreen"" + register "irq" = "IRQ_EDGE_LOW(GPIO_21_IRQ)" + register "probed" = "1" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_36)" + register "reset_delay_ms" = "20" + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPIO_152)" + register "enable_delay_ms" = "1" + register "has_power_resource" = "1" + device i2c 10 on end + end + end # - I2C 3 + device pci 17.0 on + chip drivers/i2c/generic + register "hid" = ""ELAN0000"" + register "desc" = ""ELAN Touchpad"" + register "irq" = "IRQ_EDGE_LOW(GPIO_18_IRQ)" + register "wake" = "GPE0_DW1_15" + register "probed" = "1" + device i2c 15 on end + end + end # - I2C 4 + device pci 17.1 on + chip drivers/i2c/wacom + register "generic" = "{ + .hid = WCOM50C1_HID, + .cid = PNP0C50_CID, + .desc = WCOM_DT_DESC, + .irq = IRQ_LEVEL_LOW(GPIO_13_IRQ), + }" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # - I2C 5 + device pci 17.2 off end # - I2C 6 + device pci 17.3 off end # - I2C 7 + device pci 18.0 on end # - UART 0 + device pci 18.1 on end # - UART 1 + device pci 18.2 on end # - UART 2 + device pci 18.3 off end # - UART 3 + device pci 19.0 on end # - SPI 0 + device pci 19.1 off end # - SPI 1 + device pci 19.2 off end # - SPI 2 + device pci 1a.0 on end # - PWM + device pci 1b.0 on end # - SDCARD + device pci 1c.0 on end # - eMMC + device pci 1e.0 off end # - SDIO + device pci 1f.0 on # - LPC + chip ec/google/chromeec + device pnp 0c09.0 on end + end + end + device pci 1f.1 on end # - SMBUS + end +end diff --git a/src/mainboard/intel/minnow3/dsdt.asl b/src/mainboard/intel/minnow3/dsdt.asl new file mode 100644 index 0000000..004523a --- /dev/null +++ b/src/mainboard/intel/minnow3/dsdt.asl @@ -0,0 +1,42 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x05, // DSDT revision: ACPI v5.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + /* global NVS and variables */ + #include <soc/intel/apollolake/acpi/globalnvs.asl> + + /* CPU */ + #include <soc/intel/apollolake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/apollolake/acpi/northbridge.asl> + #include <soc/intel/apollolake/acpi/southbridge.asl> + #include <soc/intel/apollolake/acpi/pch_hda.asl> + } + } + + /* Chipset specific sleep states */ + #include <soc/intel/apollolake/acpi/sleepstates.asl> +} diff --git a/src/mainboard/intel/minnow3/mainboard.c b/src/mainboard/intel/minnow3/mainboard.c new file mode 100644 index 0000000..f7a2ef1 --- /dev/null +++ b/src/mainboard/intel/minnow3/mainboard.c @@ -0,0 +1,25 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <device/device.h> + +static void mainboard_init(void *chip_info) +{ + /* Nothing Here Yet */ +} + +struct chip_operations mainboard_ops = { + .init = mainboard_init, +}; diff --git a/src/mainboard/intel/minnow3/minnow3.fmd b/src/mainboard/intel/minnow3/minnow3.fmd new file mode 100644 index 0000000..0782047 --- /dev/null +++ b/src/mainboard/intel/minnow3/minnow3.fmd @@ -0,0 +1,40 @@ +FLASH 16M { + WP_RO@0x0 0x480000 { + SI_DESC@0x0 0x1000 + IFWI@0x1000 0x27f000 + RO_VPD@0x280000 0x4000 + RO_SECTION@0x284000 0x1fc000 { + FMAP@0x0 0x800 + COREBOOT(CBFS)@0x1000 0x1bb000 + RO_UNUSED@0x1bc000 0x40000 + } + } + MISC_RW@0x480000 0x30000 { + UNIFIED_MRC_CACHE@0x0 0x21000 { + RECOVERY_MRC_CACHE@0x0 0x10000 + RW_MRC_CACHE@0x10000 0x10000 + RW_VAR_MRC_CACHE@0x20000 0x1000 + } + RW_ELOG@0x21000 0x3000 + RW_SHARED@0x24000 0x4000 { + SHARED_DATA@0x0 0x2000 + VBLOCK_DEV@0x2000 0x2000 + } + RW_VPD@0x28000 0x2000 + RW_NVRAM@0x2a000 0x6000 + } + RW_LEGACY(CBFS)@0xd30000 0x200000 + BIOS_UNUSABLE@0xf30000 0x4f000 + DEVICE_EXTENSION@0xf7f000 0x80000 + # Currently, it is required that the BIOS region be a multiple of 8KiB. + # This is required so that the recovery mechanism can find SIGN_CSE + # region aligned to 4K at the center of BIOS region. Since the + # descriptor at the beginning uses 4K and BIOS starts at an offset of + # 4K, a hole of 4K is created towards the end of the flash to compensate + # for the size requirement of BIOS region. + # FIT tool thus creates descriptor with following regions: + # Descriptor --> 0 to 4K + # BIOS --> 4K to 0xf7f000 + # Device ext --> 0xf7f000 to 0xfff000 + UNUSED_HOLE@0xfff000 0x1000 +} diff --git a/src/mainboard/intel/minnow3/romstage.c b/src/mainboard/intel/minnow3/romstage.c new file mode 100644 index 0000000..5c784ba --- /dev/null +++ b/src/mainboard/intel/minnow3/romstage.c @@ -0,0 +1,119 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <string.h> +#include <soc/romstage.h> +#include <fsp/api.h> +#include <FspmUpd.h> +#include "brd_gpio.h" + +static const uint8_t Ch0_Bit_swizzling[] = { + 0x09, 0x0e, 0x0c, 0x0d, 0x0a, 0x0b, 0x08, 0x0f, + 0x05, 0x06, 0x01, 0x00, 0x02, 0x07, 0x04, 0x03, + 0x1a, 0x1f, 0x1c, 0x1b, 0x1d, 0x19, 0x18, 0x1e, + 0x14, 0x16, 0x17, 0x11, 0x12, 0x13, 0x10, 0x15 +}; +static const uint8_t Ch1_Bit_swizzling[] = { + 0x06, 0x07, 0x05, 0x04, 0x03, 0x01, 0x00, 0x02, + 0x0c, 0x0a, 0x0b, 0x0d, 0x0e, 0x08, 0x09, 0x0f, + 0x14, 0x10, 0x16, 0x15, 0x12, 0x11, 0x13, 0x17, + 0x1e, 0x1c, 0x1d, 0x19, 0x18, 0x1a, 0x1b, 0x1f +}; +static const uint8_t Ch2_Bit_swizzling[] = { + 0x0f, 0x09, 0x08, 0x0b, 0x0c, 0x0d, 0x0e, 0x0a, + 0x05, 0x02, 0x00, 0x03, 0x06, 0x07, 0x01, 0x04, + 0x19, 0x1c, 0x1e, 0x1f, 0x1a, 0x1b, 0x18, 0x1d, + 0x14, 0x17, 0x16, 0x15, 0x12, 0x13, 0x10, 0x11 +}; +static const uint8_t Ch3_Bit_swizzling[] = { + 0x03, 0x04, 0x06, 0x05, 0x00, 0x01, 0x02, 0x07, + 0x0b, 0x0a, 0x08, 0x09, 0x0e, 0x0c, 0x0f, 0x0d, + 0x11, 0x17, 0x13, 0x10, 0x15, 0x16, 0x14, 0x12, + 0x1c, 0x1d, 0x1a, 0x19, 0x1e, 0x1b, 0x18, 0x1f +}; + +void mainboard_memory_init_params(FSPM_UPD *memupd) +{ + /* setup early gpio before memory */ + gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table)); + + /* DRAM Config settings */ + memupd->FspmConfig.Package = 0x1; + memupd->FspmConfig.Profile = 0xB; + memupd->FspmConfig.MemoryDown = 0x1; + memupd->FspmConfig.DDR3LPageSize = 0x0; + memupd->FspmConfig.DDR3LASR = 0x0; + memupd->FspmConfig.ScramblerSupport = 0x1; + memupd->FspmConfig.ChannelHashMask = 0x36; + memupd->FspmConfig.SliceHashMask = 0x9; + memupd->FspmConfig.InterleavedMode = 0x2; + memupd->FspmConfig.ChannelsSlicesEnable = 0x0; + memupd->FspmConfig.MinRefRate2xEnable = 0x0; + memupd->FspmConfig.DualRankSupportEnable = 0x1; + memupd->FspmConfig.RmtMode = 0x0; + memupd->FspmConfig.MemorySizeLimit = 0x1800; + memupd->FspmConfig.LowMemoryMaxValue = 0x0; + memupd->FspmConfig.DisableFastBoot = 0x0; + memupd->FspmConfig.HighMemoryMaxValue = 0x0; + memupd->FspmConfig.DIMM0SPDAddress = 0x0; + memupd->FspmConfig.DIMM1SPDAddress = 0x0; + memupd->FspmConfig.Ch0_RankEnable = 0x3; + memupd->FspmConfig.Ch0_DeviceWidth = 0x1; + memupd->FspmConfig.Ch0_DramDensity = 0x2; + memupd->FspmConfig.Ch0_Option = 0x3; + memupd->FspmConfig.Ch0_OdtConfig = 0x0; + memupd->FspmConfig.Ch0_TristateClk1 = 0x0; + memupd->FspmConfig.Ch0_Mode2N = 0x0; + memupd->FspmConfig.Ch0_OdtLevels = 0x0; + memupd->FspmConfig.Ch1_RankEnable = 0x3; + memupd->FspmConfig.Ch1_DeviceWidth = 0x1; + memupd->FspmConfig.Ch1_DramDensity = 0x2; + memupd->FspmConfig.Ch1_Option = 0x3; + memupd->FspmConfig.Ch1_OdtConfig = 0x0; + memupd->FspmConfig.Ch1_TristateClk1 = 0x0; + memupd->FspmConfig.Ch1_Mode2N = 0x0; + memupd->FspmConfig.Ch1_OdtLevels = 0x0; + memupd->FspmConfig.Ch2_RankEnable = 0x3; + memupd->FspmConfig.Ch2_DeviceWidth = 0x1; + memupd->FspmConfig.Ch2_DramDensity = 0x2; + memupd->FspmConfig.Ch2_Option = 0x3; + memupd->FspmConfig.Ch2_OdtConfig = 0x0; + memupd->FspmConfig.Ch2_TristateClk1 = 0x0; + memupd->FspmConfig.Ch2_Mode2N = 0x0; + memupd->FspmConfig.Ch2_OdtLevels = 0x0; + memupd->FspmConfig.Ch3_RankEnable = 0x3; + memupd->FspmConfig.Ch3_DeviceWidth = 0x1; + memupd->FspmConfig.Ch3_DramDensity = 0x2; + memupd->FspmConfig.Ch3_Option = 0x3; + memupd->FspmConfig.Ch3_OdtConfig = 0x0; + memupd->FspmConfig.Ch3_TristateClk1 = 0x0; + memupd->FspmConfig.Ch3_Mode2N = 0x0; + memupd->FspmConfig.Ch3_OdtLevels = 0x0; + memupd->FspmConfig.RmtCheckRun = 0x0; + memupd->FspmConfig.MrcDataSaving = 0x0; + memupd->FspmConfig.MrcFastBoot = 0x0; + + memcpy(memupd->FspmConfig.Ch0_Bit_swizzling, &Ch0_Bit_swizzling, + sizeof(Ch0_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch1_Bit_swizzling, &Ch1_Bit_swizzling, + sizeof(Ch1_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch2_Bit_swizzling, &Ch2_Bit_swizzling, + sizeof(Ch2_Bit_swizzling)); + memcpy(memupd->FspmConfig.Ch3_Bit_swizzling, &Ch3_Bit_swizzling, + sizeof(Ch3_Bit_swizzling)); + + memupd->FspmConfig.RmtMarginCheckScaleHighThreshold = 0x0; + memupd->FspmConfig.MsgLevelMask = 0x0; +}

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New patch to review for coreboot: util/line: Don't check license text for files with under 5 lines
by Martin Roth 10 Feb '17

10 Feb '17

Martin Roth (martinroth(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18316 -gerrit commit f05d5a3385680d15fc60d9edf410bbaed38dce04 Author: Martin Roth <martinroth(a)google.com> Date: Thu Feb 9 16:44:24 2017 -0800 util/line: Don't check license text for files with under 5 lines Change-Id: I7c1e3cf558d447838819b4d6a63d93d48d5f13e0 Signed-off-by: Martin Roth <martinroth(a)google.com> --- util/lint/lint-000-license-headers | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-) diff --git a/util/lint/lint-000-license-headers b/util/lint/lint-000-license-headers index 0d2a3af..e705929 100755 --- a/util/lint/lint-000-license-headers +++ b/util/lint/lint-000-license-headers @@ -93,8 +93,10 @@ check_for_license '"AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES' check_for_license 'No license required' for file in $headerlist; do - #verify the file exists, and has content that requires a header - if [ -f "$file" ] && [ "$(wc -l < "$file")" -ne 0 ]; then + # Verify the file exists, and has content that requires a header + # This assumes that a file that has 4 lines or fewer is not notable + # enough to require a license. + if [ -f "$file" ] && [ "$(wc -l < "$file")" -gt 4 ]; then echo "$file has no recognized license header." fi done

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coreboot-gerrit February 2017