coreboot-gerrit February 2017

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Patch set updated for coreboot: mb/*/*/cmos.layout: Make multibyte options byte alligned
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18321 -gerrit commit d0fa941a5fd612b9fba4ceba4f30e6f2660a68f8 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 8 18:12:31 2017 +0100 mb/*/*/cmos.layout: Make multibyte options byte alligned Changes the offsets of some options so that options that span multiply bytes are byte alligned. To make the cmos.layout file more consistant some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/adi/rcc-dff/cmos.layout | 10 ++++----- .../amd/serengeti_cheetah_fam10/cmos.layout | 3 ++- src/mainboard/asus/kcma-d8/cmos.layout | 6 ++++-- src/mainboard/asus/kfsn4-dre/cmos.layout | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 6 ++++-- src/mainboard/esd/atom15/cmos.layout | 10 ++++----- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 3 ++- src/mainboard/intel/littleplains/cmos.layout | 10 ++++----- src/mainboard/intel/minnowmax/cmos.layout | 10 ++++----- src/mainboard/intel/mohonpeak/cmos.layout | 10 ++++----- src/mainboard/kontron/ktqm77/cmos.layout | 11 +++++----- src/mainboard/lenovo/t400/cmos.layout | 24 ++++++++++------------ src/mainboard/lenovo/x200/cmos.layout | 19 ++++++++--------- src/mainboard/msi/ms9652_fam10/cmos.layout | 3 ++- src/mainboard/pcengines/apu1/cmos.layout | 3 ++- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 3 ++- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 3 ++- src/mainboard/tyan/s2912_fam10/cmos.layout | 3 ++- 18 files changed, 74 insertions(+), 66 deletions(-) diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ b/src/mainboard/adi/rcc-dff/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index b9dadf4..0bab4c9 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -51,6 +52,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 169af87..d0f6211 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 18c7a3f..e65f7c8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -52,6 +53,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/esd/atom15/cmos.layout +++ b/src/mainboard/esd/atom15/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 37ab3bd..21bbf28 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/littleplains/cmos.layout +++ b/src/mainboard/intel/littleplains/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index b17ee51..7cf1040 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -61,14 +61,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused # coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader 448 64 r 0 write_protected_by_bios diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..3cd076a 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -65,23 +65,21 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb -# coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +# coreboot config options: bootloader +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 2 e 12 hybrid_graphics_mode -946 4 e 11 gfx_uma_size - -# coreboot config options: EC -952 8 h 0 volume +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..59a1c6d 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -65,20 +65,19 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default - -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +432 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 8 h 0 volume -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index e0501f6..959a2d3 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -7,7 +7,8 @@ entries 392 1 e 2 boot_option 393 1 e 1 multi_core 394 3 e 3 baud_rate -397 4 e 4 debug_level +#397 3 unused +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart

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Patch set updated for coreboot: soc/intel/apollolake: Move XDCI in its own file
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18226 -gerrit commit 63815e2273a883c9dfb4174e51bdf84510a47e7c Author: Andrey Petrov <andrey.petrov(a)intel.com> Date: Tue Jan 24 21:56:36 2017 -0800 soc/intel/apollolake: Move XDCI in its own file Split out dual-port switching functionality into dedicated xdci.c. Change-Id: Ia58fc3fb6d017dd0c19cc450d1caba307fc89a7b Signed-off-by: Andrey Petrov <andrey.petrov(a)intel.com> --- src/soc/intel/apollolake/Makefile.inc | 1 + src/soc/intel/apollolake/include/soc/pci_ids.h | 1 + src/soc/intel/apollolake/xdci.c | 105 +++++++++++++++++++++++++ 3 files changed, 107 insertions(+) diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 1284708..e6b61ed 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -83,6 +83,7 @@ ramstage-y += reset.c ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c +ramstage-y += xdci.c postcar-y += flash_ctrlr.c postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/include/soc/pci_ids.h b/src/soc/intel/apollolake/include/soc/pci_ids.h index 130263b..4c2956f 100644 --- a/src/soc/intel/apollolake/include/soc/pci_ids.h +++ b/src/soc/intel/apollolake/include/soc/pci_ids.h @@ -28,6 +28,7 @@ #define PCI_DEVICE_ID_APOLLOLAKE_AUDIO 0x5a98 /* 00:0e.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_SATA 0x5ae0 /* 00:12.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_XHCI 0x5aa8 /* 00:15.0 */ +#define PCI_DEVICE_ID_APOLLOLAKE_XDCI 0x5aaa /* 00:15.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C0 0x5aac /* 00:16.0 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C1 0x5aae /* 00:16.1 */ #define PCI_DEVICE_ID_APOLLOLAKE_I2C2 0x5ab0 /* 00:16.2 */ diff --git a/src/soc/intel/apollolake/xdci.c b/src/soc/intel/apollolake/xdci.c new file mode 100644 index 0000000..2812957 --- /dev/null +++ b/src/soc/intel/apollolake/xdci.c @@ -0,0 +1,105 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2016 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <soc/pci_devs.h> +#include <soc/pci_ids.h> +#include <timer.h> + +#define DUAL_ROLE_CFG0 0x80d8 +# define DRD_CONFIG_MASK (0x3 << 0) +# define DRD_CONFIG_DYNAMIC (0x0 << 0) +# define DRD_CONFIG_HOST (0x1 << 0) +# define DRD_CONFIG_DEVICE (0x2 << 0) +# define SW_VBUS_VALID_MASK (1 << 24) +# define SW_VBUS_DEASSERT_VALID (0 << 24) +# define SW_VBUS_ASSERT_VALID (1 << 24) +# define SW_IDPIN_EN_MASK (1 << 21) +# define SW_IDPIN_DIS (0 << 21) +# define SW_IDPIN_EN (1 << 21) +# define SW_IDPIN_MASK (1 << 20) +# define SW_IDPIN_HOST (0 << 20) +# define SW_IDPIN_DEVICE (1 << 20) +#define DUAL_ROLE_CFG1 0x80dc +# define DRD_MODE_MASK (1 << 29) +# define DRD_MODE_DEVICE (0 << 29) +# define DRD_MODE_HOST (1 << 29) + +static void configure_host_mode_port0(struct device *dev) +{ + uint32_t *cfg0; + uint32_t *cfg1; + const struct resource *res; + uint32_t reg; + struct stopwatch sw; + struct device *xhci_dev = XHCI_DEV; + + /* + * Only default to host mode if the xdci device is present and + * enabled. If it's disabled assume the switch was already done + * in FSP. + */ + if (!dev->enabled || !xhci_dev->enabled) + return; + + printk(BIOS_INFO, "Putting port 0 into host mode.\n"); + + res = find_resource(xhci_dev, PCI_BASE_ADDRESS_0); + + cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); + cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); + + reg = read32(cfg0); + reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); + reg &= ~(SW_VBUS_VALID_MASK); + reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; + reg |= SW_VBUS_DEASSERT_VALID; + write32(cfg0, reg); + + stopwatch_init_msecs_expire(&sw, 10); + + /* Wait for the host mode status bit. */ + while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { + if (stopwatch_expired(&sw)) { + printk(BIOS_INFO, "Timed out waiting for host mode.\n"); + break; + } + } + + printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", + stopwatch_duration_msecs(&sw)); +} + +static void xdci_init(struct device *dev) +{ + configure_host_mode_port0(dev); +} + +static const struct device_operations device_ops = { + .read_resources = pci_dev_read_resources, + .set_resources = pci_dev_set_resources, + .enable_resources = pci_dev_enable_resources, + .init = xdci_init, +}; + +static const struct pci_driver pmc __pci_driver = { + .ops = &device_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .device = PCI_DEVICE_ID_APOLLOLAKE_XDCI, +};

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Patch set updated for coreboot: soc/intel/apollolake: Use intel/common/xhci driver
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18222 -gerrit commit 2e298dd140e42dd7dbc582e3e7e7e21429e42292 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:54:58 2017 +0530 soc/intel/apollolake: Use intel/common/xhci driver Change-Id: If161b1e11041ea7a380222ba555f14cd114de617 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/apollolake/Kconfig | 1 + src/soc/intel/apollolake/Makefile.inc | 2 +- src/soc/intel/apollolake/xhci.c | 105 ---------------------------------- 3 files changed, 2 insertions(+), 106 deletions(-) diff --git a/src/soc/intel/apollolake/Kconfig b/src/soc/intel/apollolake/Kconfig index b37cde6..afd617e 100644 --- a/src/soc/intel/apollolake/Kconfig +++ b/src/soc/intel/apollolake/Kconfig @@ -53,6 +53,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_LPSS_I2C select SOC_INTEL_COMMON_SMI select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_XHCI_DRIVER select UDELAY_TSC select TSC_CONSTANT_RATE select TSC_MONOTONIC_TIMER diff --git a/src/soc/intel/apollolake/Makefile.inc b/src/soc/intel/apollolake/Makefile.inc index 5a65f43..1284708 100644 --- a/src/soc/intel/apollolake/Makefile.inc +++ b/src/soc/intel/apollolake/Makefile.inc @@ -7,6 +7,7 @@ subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc subdirs-y += ../../../cpu/x86/cache +subdirs-y += ../common/block/* bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/bootblock.c @@ -82,7 +83,6 @@ ramstage-y += reset.c ramstage-y += smi.c ramstage-y += sram.c ramstage-y += spi.c -ramstage-y += xhci.c postcar-y += flash_ctrlr.c postcar-y += memmap.c diff --git a/src/soc/intel/apollolake/xhci.c b/src/soc/intel/apollolake/xhci.c deleted file mode 100644 index 7b3cb46..0000000 --- a/src/soc/intel/apollolake/xhci.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright 2016 Google Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <arch/io.h> -#include <console/console.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <soc/pci_devs.h> -#include <soc/pci_ids.h> -#include <timer.h> - -#define DUAL_ROLE_CFG0 0x80d8 -# define DRD_CONFIG_MASK (0x3 << 0) -# define DRD_CONFIG_DYNAMIC (0x0 << 0) -# define DRD_CONFIG_HOST (0x1 << 0) -# define DRD_CONFIG_DEVICE (0x2 << 0) -# define SW_VBUS_VALID_MASK (1 << 24) -# define SW_VBUS_DEASSERT_VALID (0 << 24) -# define SW_VBUS_ASSERT_VALID (1 << 24) -# define SW_IDPIN_EN_MASK (1 << 21) -# define SW_IDPIN_DIS (0 << 21) -# define SW_IDPIN_EN (1 << 21) -# define SW_IDPIN_MASK (1 << 20) -# define SW_IDPIN_HOST (0 << 20) -# define SW_IDPIN_DEVICE (1 << 20) -#define DUAL_ROLE_CFG1 0x80dc -# define DRD_MODE_MASK (1 << 29) -# define DRD_MODE_DEVICE (0 << 29) -# define DRD_MODE_HOST (1 << 29) - -static void configure_host_mode_port0(struct device *dev) -{ - uint32_t *cfg0; - uint32_t *cfg1; - const struct resource *res; - uint32_t reg; - struct device *xdci_dev = XDCI_DEV; - struct stopwatch sw; - - /* - * Only default to host mode if the xdci device is present and - * enabled. If it's disabled assume the switch was already done - * in FSP. - */ - if (xdci_dev == NULL || !xdci_dev->enabled) - return; - - printk(BIOS_INFO, "Putting port 0 into host mode.\n"); - - res = find_resource(dev, PCI_BASE_ADDRESS_0); - - cfg0 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG0); - cfg1 = (void *)(uintptr_t)(res->base + DUAL_ROLE_CFG1); - - reg = read32(cfg0); - reg &= ~(DRD_CONFIG_MASK | SW_IDPIN_EN_MASK | SW_IDPIN_MASK); - reg &= ~(SW_VBUS_VALID_MASK); - reg |= DRD_CONFIG_DYNAMIC | SW_IDPIN_EN | SW_IDPIN_HOST; - reg |= SW_VBUS_DEASSERT_VALID; - write32(cfg0, reg); - - stopwatch_init_msecs_expire(&sw, 10); - - /* Wait for the host mode status bit. */ - while ((read32(cfg1) & DRD_MODE_MASK) != DRD_MODE_HOST) { - if (stopwatch_expired(&sw)) { - printk(BIOS_INFO, "Timed out waiting for host mode.\n"); - break; - } - } - - printk(BIOS_INFO, "XHCI port 0 host switch over took %lu ms\n", - stopwatch_duration_msecs(&sw)); -} - -static void xhci_init(struct device *dev) -{ - configure_host_mode_port0(dev); -} - -static const struct device_operations device_ops = { - .read_resources = pci_dev_read_resources, - .set_resources = pci_dev_set_resources, - .enable_resources = pci_dev_enable_resources, - .init = xhci_init, -}; - -static const struct pci_driver pmc __pci_driver = { - .ops = &device_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .device = PCI_DEVICE_ID_APOLLOLAKE_XHCI, -};

1 0

Patch set updated for coreboot: soc/intel/skylake: Use intel/common/xhci driver
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18223 -gerrit commit 4b82f3cad36da4c15589649f17e6eb28eb4b3900 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:56:12 2017 +0530 soc/intel/skylake: Use intel/common/xhci driver Change-Id: I7bd83d293fcc1848f6f64526d8f38d010c1f69a3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/soc/intel/skylake/Kconfig | 1 + src/soc/intel/skylake/Makefile.inc | 2 +- src/soc/intel/skylake/xhci.c | 43 -------------------------------------- 3 files changed, 2 insertions(+), 44 deletions(-) diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig index 24c2e30..4fca67e 100644 --- a/src/soc/intel/skylake/Kconfig +++ b/src/soc/intel/skylake/Kconfig @@ -45,6 +45,7 @@ config CPU_SPECIFIC_OPTIONS select SOC_INTEL_COMMON_NHLT select SOC_INTEL_COMMON_RESET select SOC_INTEL_COMMON_SPI_FLASH_PROTECT + select SOC_INTEL_XHCI_DRIVER select SMM_TSEG select SMP select SSE2 diff --git a/src/soc/intel/skylake/Makefile.inc b/src/soc/intel/skylake/Makefile.inc index 4b6fcfc..6ae5897 100644 --- a/src/soc/intel/skylake/Makefile.inc +++ b/src/soc/intel/skylake/Makefile.inc @@ -8,6 +8,7 @@ subdirs-y += ../../../cpu/x86/lapic subdirs-y += ../../../cpu/x86/mtrr subdirs-y += ../../../cpu/x86/smm subdirs-y += ../../../cpu/x86/tsc +subdirs-y += ../common/block/* bootblock-y += bootblock/bootblock.c bootblock-y += bootblock/cache_as_ram.S @@ -90,7 +91,6 @@ ramstage-y += tsc_freq.c ramstage-y += uart.c ramstage-$(CONFIG_UART_DEBUG) += uart_debug.c ramstage-y += vr_config.c -ramstage-y += xhci.c smm-y += cpu_info.c smm-y += gpio.c diff --git a/src/soc/intel/skylake/xhci.c b/src/soc/intel/skylake/xhci.c deleted file mode 100644 index 6b4a19a..0000000 --- a/src/soc/intel/skylake/xhci.c +++ /dev/null @@ -1,43 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2014 Google Inc. - * Copyright (C) 2015 Intel Corporation. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <delay.h> -#include <device/device.h> -#include <device/pci.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <soc/ramstage.h> -#include <soc/xhci.h> -#include <soc/cpu.h> - -static struct device_operations usb_xhci_ops = { - .read_resources = &pci_dev_read_resources, - .set_resources = &pci_dev_set_resources, - .enable_resources = &pci_dev_enable_resources, - .ops_pci = &soc_pci_ops, -}; - -static const unsigned short pci_device_ids[] = { - 0x9d2f, /* SunRisePoint LP */ - 0 -}; - -static const struct pci_driver pch_usb_xhci __pci_driver = { - .ops = &usb_xhci_ops, - .vendor = PCI_VENDOR_ID_INTEL, - .devices = pci_device_ids, -};

1 0

Patch set updated for coreboot: soc/intel/common/block: Add Intel XHCI driver support
by Subrata Banik 10 Feb '17

10 Feb '17

Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221 -gerrit commit 9d73aeb8c591ee614e4151683b53de69b2af7983 Author: Subrata Banik <subrata.banik(a)intel.com> Date: Tue Jan 24 18:53:10 2017 +0530 soc/intel/common/block: Add Intel XHCI driver support Create sample model for common Intel XHCI driver. Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- src/Kconfig | 3 ++ src/soc/intel/common/block/include/xhci.h | 22 ++++++++++++++ src/soc/intel/common/block/xhci/Kconfig | 4 +++ src/soc/intel/common/block/xhci/Makefile.inc | 7 +++++ src/soc/intel/common/block/xhci/xhci.c | 45 ++++++++++++++++++++++++++++ 5 files changed, 81 insertions(+) diff --git a/src/Kconfig b/src/Kconfig index 436964c..e6e8e03 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -471,6 +471,9 @@ source "src/ec/*/*/Kconfig" # FIXME move to vendorcode source "src/drivers/intel/fsp1_0/Kconfig" +# Intel SoC Family IP model Kconfig +source "src/soc/intel/common/block/*/Kconfig" + source "src/southbridge/intel/common/firmware/Kconfig" source "src/vboot/Kconfig" source "src/vendorcode/*/Kconfig" diff --git a/src/soc/intel/common/block/include/xhci.h b/src/soc/intel/common/block/include/xhci.h new file mode 100644 index 0000000..1ad1c4e --- /dev/null +++ b/src/soc/intel/common/block/include/xhci.h @@ -0,0 +1,22 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __XHCI_H +#define __XHCI_H + +void xhci_init(struct device *dev); + +#endif /* __XHCI_H */ + diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig new file mode 100644 index 0000000..7070dd3 --- /dev/null +++ b/src/soc/intel/common/block/xhci/Kconfig @@ -0,0 +1,4 @@ +config SOC_INTEL_XHCI_DRIVER + bool + help + Intel Processor XHCI Driver support diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc new file mode 100644 index 0000000..826f3da --- /dev/null +++ b/src/soc/intel/common/block/xhci/Makefile.inc @@ -0,0 +1,7 @@ +ifeq ($(CONFIG_SOC_INTEL_XHCI_DRIVER),y) + +ramstage-y += xhci.c + +CPPFLAGS_common += -I$(src)/soc/intel/common/block/include + +endif diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c new file mode 100644 index 0000000..790129b --- /dev/null +++ b/src/soc/intel/common/block/xhci/xhci.c @@ -0,0 +1,45 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <console/console.h> +#include <device/device.h> +#include <device/pci.h> +#include <device/pci_ids.h> +#include <arch/io.h> +#include <xhci.h> + +__attribute__((weak)) void xhci_init(struct device *dev) { /* no-op */ } + +static struct device_operations usb_xhci_ops = { + .read_resources = &pci_dev_read_resources, + .set_resources = &pci_dev_set_resources, + .enable_resources = &pci_dev_enable_resources, + .ops_pci = &soc_pci_ops, + .init = xhci_init, +}; + +static const unsigned short pci_device_ids[] = { + 0x5aa8, /* ApolloLake */ + 0x31a8, /* GLK */ + 0x9d2f, /* SunRisePoint LP */ + 0 +}; + +static const struct pci_driver pch_usb_xhci __pci_driver = { + .ops = &usb_xhci_ops, + .vendor = PCI_VENDOR_ID_INTEL, + .devices = pci_device_ids, +};

1 0

Patch set updated for coreboot: util/nvramtool: Bail out on unaligned multi-byte entries
by Nico Huber 10 Feb '17

10 Feb '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18246 -gerrit commit 9a3fd06f61634ee336925d65549b0c9ffa9c5bcd Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Jan 26 23:22:46 2017 +0100 util/nvramtool: Bail out on unaligned multi-byte entries coreboot doesn't support CMOS options that are not byte aligned but span multiple bytes. So treat them as error. Change-Id: I2bcff62f153932e9c6646b4ce08e8da1c1532947 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/nvramtool/accessors/layout-bin.c | 6 ++++++ util/nvramtool/accessors/layout-text.c | 6 ++++++ util/nvramtool/layout.c | 3 +++ util/nvramtool/layout.h | 1 + 4 files changed, 16 insertions(+) diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c index 34507c9..fa6344b 100644 --- a/util/nvramtool/accessors/layout-bin.c +++ b/util/nvramtool/accessors/layout-bin.c @@ -481,6 +481,12 @@ static void try_add_cmos_table_entry(cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index bea3b3e..b6cbc2e 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -695,6 +695,12 @@ static void try_add_layout_file_entry(const cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c index 241dd19..6fdb282 100644 --- a/util/nvramtool/layout.c +++ b/util/nvramtool/layout.c @@ -169,6 +169,9 @@ int add_cmos_entry(const cmos_entry_t * e, const cmos_entry_t ** conflict) if (e->length < 1) return LAYOUT_ENTRY_BAD_LENGTH; + if (e->bit % 8 && e->bit / 8 != (e->bit + e->length - 1) / 8) + return LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED; + if ((new_entry = (cmos_entry_item_t *) malloc(sizeof(*new_entry))) == NULL) out_of_memory(); diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index 8a39ab9..bde0603 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -40,6 +40,7 @@ #define LAYOUT_CHECKSUM_OVERLAPS_SUMMED_AREA (LAYOUT_RESULT_START + 7) #define LAYOUT_SUMMED_AREA_OUT_OF_RANGE (LAYOUT_RESULT_START + 8) #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) +#define LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED (LAYOUT_RESULT_START + 10) typedef enum { CMOS_ENTRY_ENUM = 'e',

1 0

Patch set updated for coreboot: mb/*/*/cmos.layout: Make multibyte options byte alligned
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18321 -gerrit commit b82e475a7777cf4a1f6ea64582b05f5672acaf17 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 8 18:12:31 2017 +0100 mb/*/*/cmos.layout: Make multibyte options byte alligned Changes the offsets of some options so that options that span multiply bytes are byte alligned. To make the cmos.layout file more consistant some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/adi/rcc-dff/cmos.layout | 10 ++++----- .../amd/serengeti_cheetah_fam10/cmos.layout | 3 ++- src/mainboard/asus/kcma-d8/cmos.layout | 6 ++++-- src/mainboard/asus/kfsn4-dre/cmos.layout | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 6 ++++-- src/mainboard/esd/atom15/cmos.layout | 10 ++++----- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 3 ++- src/mainboard/intel/littleplains/cmos.layout | 10 ++++----- src/mainboard/intel/minnowmax/cmos.layout | 10 ++++----- src/mainboard/intel/mohonpeak/cmos.layout | 10 ++++----- src/mainboard/kontron/ktqm77/cmos.layout | 11 +++++----- src/mainboard/lenovo/t400/cmos.layout | 24 ++++++++++------------ src/mainboard/lenovo/x200/cmos.layout | 19 ++++++++--------- src/mainboard/msi/ms9652_fam10/cmos.layout | 3 ++- src/mainboard/pcengines/apu1/cmos.layout | 3 ++- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 3 ++- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 3 ++- src/mainboard/tyan/s2912_fam10/cmos.layout | 3 ++- 18 files changed, 74 insertions(+), 66 deletions(-) diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ b/src/mainboard/adi/rcc-dff/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index b9dadf4..0bab4c9 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -51,6 +52,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 169af87..d0f6211 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 18c7a3f..e65f7c8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -52,6 +53,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/esd/atom15/cmos.layout +++ b/src/mainboard/esd/atom15/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 37ab3bd..21bbf28 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/littleplains/cmos.layout +++ b/src/mainboard/intel/littleplains/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index b17ee51..7cf1040 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -61,14 +61,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused # coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader 448 64 r 0 write_protected_by_bios diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..ee4f1f7 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -65,23 +65,21 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb -# coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +# coreboot config options: bootloader +429 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 2 e 12 hybrid_graphics_mode -946 4 e 11 gfx_uma_size - -# coreboot config options: EC -952 8 h 0 volume +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..7bb4881 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -65,20 +65,19 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +427 1 e 1 low_battery_beep +428 1 e 1 uwb # coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default - -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +429 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 8 h 0 volume -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index e0501f6..959a2d3 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -7,7 +7,8 @@ entries 392 1 e 2 boot_option 393 1 e 1 multi_core 394 3 e 3 baud_rate -397 4 e 4 debug_level +#397 3 unused +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart

1 0

Patch set updated for coreboot: util/nvramtool: Bail out on unaligned multi-byte entries
by Nico Huber 10 Feb '17

10 Feb '17

Nico Huber (nico.h(a)gmx.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18246 -gerrit commit e5c86963b8e8a69bc66ab609dc528afed282cddf Author: Nico Huber <nico.h(a)gmx.de> Date: Thu Jan 26 23:22:46 2017 +0100 util/nvramtool: Bail out on unaligned multi-byte entries coreboot doesn't support CMOS options that are not byte aligned but span multiple bytes. So treat them as error. Change-Id: I2bcff62f153932e9c6646b4ce08e8da1c1532947 Signed-off-by: Nico Huber <nico.h(a)gmx.de> --- util/nvramtool/accessors/layout-bin.c | 6 ++++++ util/nvramtool/accessors/layout-text.c | 6 ++++++ util/nvramtool/layout.c | 3 +++ util/nvramtool/layout.h | 1 + 4 files changed, 16 insertions(+) diff --git a/util/nvramtool/accessors/layout-bin.c b/util/nvramtool/accessors/layout-bin.c index 34507c9..fa6344b 100644 --- a/util/nvramtool/accessors/layout-bin.c +++ b/util/nvramtool/accessors/layout-bin.c @@ -481,6 +481,12 @@ static void try_add_cmos_table_entry(cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/accessors/layout-text.c b/util/nvramtool/accessors/layout-text.c index bea3b3e..b6cbc2e 100644 --- a/util/nvramtool/accessors/layout-text.c +++ b/util/nvramtool/accessors/layout-text.c @@ -695,6 +695,12 @@ static void try_add_layout_file_entry(const cmos_entry_t * cmos_entry) */ return; + case LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED: + fprintf(stderr, + "%s: Unaligned CMOS option table entry %s spans " + "multiple bytes.\n", prog_name, cmos_entry->name); + break; + default: BUG(); } diff --git a/util/nvramtool/layout.c b/util/nvramtool/layout.c index 241dd19..6fdb282 100644 --- a/util/nvramtool/layout.c +++ b/util/nvramtool/layout.c @@ -169,6 +169,9 @@ int add_cmos_entry(const cmos_entry_t * e, const cmos_entry_t ** conflict) if (e->length < 1) return LAYOUT_ENTRY_BAD_LENGTH; + if (e->bit % 8 && e->bit / 8 != (e->bit + e->length - 1) / 8) + return LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED; + if ((new_entry = (cmos_entry_item_t *) malloc(sizeof(*new_entry))) == NULL) out_of_memory(); diff --git a/util/nvramtool/layout.h b/util/nvramtool/layout.h index 8a39ab9..bde0603 100644 --- a/util/nvramtool/layout.h +++ b/util/nvramtool/layout.h @@ -40,6 +40,7 @@ #define LAYOUT_CHECKSUM_OVERLAPS_SUMMED_AREA (LAYOUT_RESULT_START + 7) #define LAYOUT_SUMMED_AREA_OUT_OF_RANGE (LAYOUT_RESULT_START + 8) #define LAYOUT_CHECKSUM_LOCATION_OUT_OF_RANGE (LAYOUT_RESULT_START + 9) +#define LAYOUT_MULTIBYTE_ENTRY_NOT_ALIGNED (LAYOUT_RESULT_START + 10) typedef enum { CMOS_ENTRY_ENUM = 'e',

1 0

New patch to review for coreboot: mb/*/*/cmos.layout: Make multibyte options byte alligned
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18321 -gerrit commit 60c488bb688af257af75c982ecfaab6771cfac47 Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Wed Feb 8 18:12:31 2017 +0100 mb/*/*/cmos.layout: Make multibyte options byte alligned Changes the offsets of some options so that options that span multiply bytes are byte alligned. To make the cmos.layout file more consistant some things where moved around in the cmos.layout of thinkpads X200 and T400. Change-Id: Ic84a2a5dc6f9c102f041085871c2ed55e2f3692a Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/mainboard/adi/rcc-dff/cmos.layout | 10 ++++----- .../amd/serengeti_cheetah_fam10/cmos.layout | 3 ++- src/mainboard/asus/kcma-d8/cmos.layout | 6 ++++-- src/mainboard/asus/kfsn4-dre/cmos.layout | 3 ++- src/mainboard/asus/kgpe-d16/cmos.layout | 6 ++++-- src/mainboard/esd/atom15/cmos.layout | 10 ++++----- src/mainboard/hp/dl165_g6_fam10/cmos.layout | 3 ++- src/mainboard/intel/littleplains/cmos.layout | 10 ++++----- src/mainboard/intel/minnowmax/cmos.layout | 10 ++++----- src/mainboard/intel/mohonpeak/cmos.layout | 10 ++++----- src/mainboard/kontron/ktqm77/cmos.layout | 11 +++++----- src/mainboard/lenovo/t400/cmos.layout | 24 ++++++++++------------ src/mainboard/lenovo/x200/cmos.layout | 19 ++++++++--------- src/mainboard/msi/ms9652_fam10/cmos.layout | 3 ++- src/mainboard/pcengines/apu1/cmos.layout | 3 ++- src/mainboard/supermicro/h8dmr_fam10/cmos.layout | 3 ++- src/mainboard/supermicro/h8qme_fam10/cmos.layout | 3 ++- src/mainboard/tyan/s2912_fam10/cmos.layout | 3 ++- 18 files changed, 74 insertions(+), 66 deletions(-) diff --git a/src/mainboard/adi/rcc-dff/cmos.layout b/src/mainboard/adi/rcc-dff/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/adi/rcc-dff/cmos.layout +++ b/src/mainboard/adi/rcc-dff/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout +++ b/src/mainboard/amd/serengeti_cheetah_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kcma-d8/cmos.layout b/src/mainboard/asus/kcma-d8/cmos.layout index b9dadf4..0bab4c9 100644 --- a/src/mainboard/asus/kcma-d8/cmos.layout +++ b/src/mainboard/asus/kcma-d8/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -51,6 +52,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/asus/kfsn4-dre/cmos.layout b/src/mainboard/asus/kfsn4-dre/cmos.layout index 169af87..d0f6211 100644 --- a/src/mainboard/asus/kfsn4-dre/cmos.layout +++ b/src/mainboard/asus/kfsn4-dre/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/asus/kgpe-d16/cmos.layout b/src/mainboard/asus/kgpe-d16/cmos.layout index 18c7a3f..e65f7c8 100644 --- a/src/mainboard/asus/kgpe-d16/cmos.layout +++ b/src/mainboard/asus/kgpe-d16/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 4 e 8 max_mem_clock 408 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart @@ -42,7 +43,7 @@ entries 466 1 e 1 cpu_cc6_state 467 1 e 1 sata_ahci_mode 468 1 e 1 sata_alpm -469 4 h 0 maximum_p_state_limit +#469 4 unused 473 2 e 13 dimm_spd_checksum 475 1 e 14 probe_filter 476 1 e 1 l3_cache_partitioning @@ -52,6 +53,7 @@ entries 480 1 e 2 ehci_async_data_cache 481 1 e 1 experimental_memory_speed_boost 482 1 r 0 allow_spd_nvram_cache_restore +483 4 h 0 maximum_p_state_limit 728 256 h 0 user_data 984 16 h 0 check_sum # Reserve the extended AMD configuration registers diff --git a/src/mainboard/esd/atom15/cmos.layout b/src/mainboard/esd/atom15/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/esd/atom15/cmos.layout +++ b/src/mainboard/esd/atom15/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/hp/dl165_g6_fam10/cmos.layout b/src/mainboard/hp/dl165_g6_fam10/cmos.layout index 37ab3bd..21bbf28 100644 --- a/src/mainboard/hp/dl165_g6_fam10/cmos.layout +++ b/src/mainboard/hp/dl165_g6_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/intel/littleplains/cmos.layout b/src/mainboard/intel/littleplains/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/littleplains/cmos.layout +++ b/src/mainboard/intel/littleplains/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout index f65750c..fc92f96 100644 --- a/src/mainboard/intel/minnowmax/cmos.layout +++ b/src/mainboard/intel/minnowmax/cmos.layout @@ -70,11 +70,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/intel/mohonpeak/cmos.layout b/src/mainboard/intel/mohonpeak/cmos.layout index 2704122..235b63c 100644 --- a/src/mainboard/intel/mohonpeak/cmos.layout +++ b/src/mainboard/intel/mohonpeak/cmos.layout @@ -69,11 +69,11 @@ entries #1000 24 r 0 amd_reserved #save timestamps in pre-ram boot areas -1719 64 h 0 timestamp_value1 -1783 64 h 0 timestamp_value2 -1847 64 h 0 timestamp_value3 -1911 64 h 0 timestamp_value4 -1975 64 h 0 timestamp_value5 +1720 64 h 0 timestamp_value1 +1784 64 h 0 timestamp_value2 +1848 64 h 0 timestamp_value3 +1912 64 h 0 timestamp_value4 +1976 64 h 0 timestamp_value5 # ----------------------------------------------------------------- diff --git a/src/mainboard/kontron/ktqm77/cmos.layout b/src/mainboard/kontron/ktqm77/cmos.layout index b17ee51..7cf1040 100644 --- a/src/mainboard/kontron/ktqm77/cmos.layout +++ b/src/mainboard/kontron/ktqm77/cmos.layout @@ -61,14 +61,13 @@ entries 408 1 e 1 nmi 409 2 e 7 power_on_after_fail 411 1 e 11 sata_mode -#412 4 r 0 unused # coreboot config options: additional mainboard options -416 4 e 10 systemp_type -420 7 h 0 fan1_min -427 7 h 0 fan1_max -434 7 h 0 fan2_min -441 7 h 0 fan2_max +412 4 e 10 systemp_type +416 7 h 0 fan1_min +424 7 h 0 fan1_max +432 7 h 0 fan2_min +440 7 h 0 fan2_max # coreboot config options: bootloader 448 64 r 0 write_protected_by_bios diff --git a/src/mainboard/lenovo/t400/cmos.layout b/src/mainboard/lenovo/t400/cmos.layout index 61212dd..9cbd462 100644 --- a/src/mainboard/lenovo/t400/cmos.layout +++ b/src/mainboard/lenovo/t400/cmos.layout @@ -65,23 +65,21 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +927 1 e 1 low_battery_beep +928 1 e 1 uwb -# coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +# coreboot config options: bootloader +429 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 2 e 12 hybrid_graphics_mode -946 4 e 11 gfx_uma_size - -# coreboot config options: EC -952 8 h 0 volume +952 2 e 12 hybrid_graphics_mode +954 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/lenovo/x200/cmos.layout b/src/mainboard/lenovo/x200/cmos.layout index 35d5017..69fda72 100644 --- a/src/mainboard/lenovo/x200/cmos.layout +++ b/src/mainboard/lenovo/x200/cmos.layout @@ -65,20 +65,19 @@ entries 413 1 e 1 wwan 414 1 e 1 wlan 415 1 e 1 trackpoint -416 1 e 1 fn_ctrl_swap -417 1 e 1 sticky_fn +416 8 h 0 volume +424 1 e 1 fn_ctrl_swap +425 1 e 1 sticky_fn +426 1 e 1 power_management_beeps +927 1 e 1 low_battery_beep +928 1 e 1 uwb # coreboot config options: bootloader -418 512 s 0 boot_devices -930 8 h 0 boot_default - -938 1 e 1 power_management_beeps -939 1 e 1 low_battery_beep -940 1 e 1 uwb +429 512 s 0 boot_devices +944 8 h 0 boot_default # coreboot config options: northbridge -944 8 h 0 volume -952 4 e 11 gfx_uma_size +952 4 e 11 gfx_uma_size # coreboot config options: check sums 984 16 h 0 check_sum diff --git a/src/mainboard/msi/ms9652_fam10/cmos.layout b/src/mainboard/msi/ms9652_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/msi/ms9652_fam10/cmos.layout +++ b/src/mainboard/msi/ms9652_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/pcengines/apu1/cmos.layout b/src/mainboard/pcengines/apu1/cmos.layout index e0501f6..959a2d3 100644 --- a/src/mainboard/pcengines/apu1/cmos.layout +++ b/src/mainboard/pcengines/apu1/cmos.layout @@ -7,7 +7,8 @@ entries 392 1 e 2 boot_option 393 1 e 1 multi_core 394 3 e 3 baud_rate -397 4 e 4 debug_level +#397 3 unused +400 4 e 4 debug_level # leave 7 bits to make checksummed area end byte-aligned 408 16 h 0 check_sum diff --git a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8dmr_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8dmr_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/supermicro/h8qme_fam10/cmos.layout b/src/mainboard/supermicro/h8qme_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/supermicro/h8qme_fam10/cmos.layout +++ b/src/mainboard/supermicro/h8qme_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart diff --git a/src/mainboard/tyan/s2912_fam10/cmos.layout b/src/mainboard/tyan/s2912_fam10/cmos.layout index fe0ff4e..7fad0be 100644 --- a/src/mainboard/tyan/s2912_fam10/cmos.layout +++ b/src/mainboard/tyan/s2912_fam10/cmos.layout @@ -22,13 +22,14 @@ entries 384 1 e 4 boot_option 388 4 h 0 reboot_counter 393 3 e 5 baud_rate -396 5 e 10 ecc_scrub_rate +#396 5 unused 401 1 e 1 interleave_chip_selects 402 1 e 1 interleave_nodes 403 1 e 1 interleave_memory_channels 404 2 e 8 max_mem_clock 406 1 e 2 multi_core 412 4 e 6 debug_level +416 5 e 10 ecc_scrub_rate 440 4 e 9 slow_cpu 444 1 e 1 nmi 445 1 e 1 gart

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Patch set updated for coreboot: device/dram/ddr2: Add common function to select common CAS en freq
by Arthur Heymans 10 Feb '17

10 Feb '17

Arthur Heymans (arthur(a)aheymans.xyz) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18320 -gerrit commit 540809ec1c6efb47ea35003f370a8a0af7616f1f Author: Arthur Heymans <arthur(a)aheymans.xyz> Date: Fri Feb 10 12:08:16 2017 +0100 device/dram/ddr2: Add common function to select common CAS en freq This function has CAS and Frequency masks as inputs to support northbridges that have different limits on those. The CAS mask is used as defined in SPD and frequency mask is bitwise mask for supported frequency so e.g. if 200 and 266MHz are supported freq_mask would be (1 << DDR2_200MHZ) | (1 << DDR2_266MHZ). Change-Id: I3ab39d38a243edddfde8f70ebd23f79ff774e90e Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- src/device/dram/ddr2.c | 86 ++++++++++++++++++++++++++++++++++++++++++ src/include/device/dram/ddr2.h | 15 +++++++- 2 files changed, 100 insertions(+), 1 deletion(-) diff --git a/src/device/dram/ddr2.c b/src/device/dram/ddr2.c index b712192..f520904 100644 --- a/src/device/dram/ddr2.c +++ b/src/device/dram/ddr2.c @@ -2,6 +2,7 @@ * This file is part of the coreboot project. * * Copyright (C) 2017 Patrick Rudolph <siro(a)das-labor.org> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by @@ -110,6 +111,21 @@ static u8 spd_get_msbs(u8 c) } /** + * \brief Return index of MSB set + * + * Returns the index fof MSB set. + */ +static u8 spd_get_lsbs(u8 c) +{ + int i; + for (i = 0; i > 7; i++) + if (c & (1 << i)) + return i; + + return 0; +} + +/** * \brief Decode SPD tck cycle time * * Decodes a raw SPD data from a DDR2 DIMM. @@ -593,3 +609,73 @@ void dram_print_spd_ddr2(const dimm_attr *dimm) print_us(" tPLL : ", dimm->tPLL); print_us(" tRR : ", dimm->tRR); } + +int get_common_freq_cas(u8 freq_mask, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas) +{ + int i, found, high_supp_cas, low_supp_cas; + u8 curr_freq, curr_cas; + + const int ddr2_speeds_table[] = { + TCK_200MHZ, + TCK_266MHZ, + TCK_333MHZ, + TCK_400MHZ, + TCK_533MHZ, + TCK_666MHZ, + TCK_700MHZ, + TCK_800MHZ, + }; + + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == SPD_DIMM_TYPE_UNDEFINED) + continue; + cas_mask &= dimm[i]->cas_supported; + } + + if (!cas_mask) { + printk(BIOS_DEBUG, "No common supported CAS\n"); + return 1; + } + + high_supp_cas = spd_get_msbs(cas_mask); + low_supp_cas = spd_get_lsbs(cas_mask); + + /* Loop from fast to slow frequency, from low to high CAS latency */ + for (curr_freq = spd_get_msbs(freq_mask); + curr_freq >= spd_get_lsbs(freq_mask); curr_freq--) { + printram("Trying speed: %d\n", curr_freq); + for (curr_cas = low_supp_cas; + curr_cas <= low_supp_cas; curr_cas++) { + printram(" Trying CAS: %d\n"; curr_freq); + found = 1; + for (i = 0; i < num_dimms; i++) { + if (dimm[i]->dimm_type == + SPD_DIMM_TYPE_UNDEFINED) + continue; + + printram(" Testing DIMM: %d\n", i); + if (dimm[i]->cycle_time[curr_cas] == 0) { + printram(" CAS not supported"); + found = 0; + break; + } + + if (dimm[i]->cycle_time[curr_cas] > + ddr2_speeds_table[curr_freq]) { + printram(" Timing too fast\n"); + found = 0; + break; + } + } + if (found) { + *selected_freq = curr_freq; + *selected_cas = curr_cas; + return 0; + } + } + } + + printk(BIOS_DEBUG, "No common CAS Frequency combination possible!\n"); + return 1; +} diff --git a/src/include/device/dram/ddr2.h b/src/include/device/dram/ddr2.h index 236be49..24d3379 100644 --- a/src/include/device/dram/ddr2.h +++ b/src/include/device/dram/ddr2.h @@ -46,6 +46,18 @@ #define TCK_333MHZ 768 #define TCK_266MHZ 960 #define TCK_200MHZ 1280 + +enum dram_freq { + DDR2_200MHZ, + DDR2_266MHZ, + DDR2_333MHZ, + DDR2_400MHZ, + DDR2_533MHZ, + DDR2_666MHZ, + DDR2_700MHZ, + DDR2_800MHZ, +}; + /** @} */ /** @@ -198,6 +210,7 @@ u32 spd_decode_spd_size_ddr2(u8 byte0); u32 spd_decode_eeprom_size_ddr2(u8 byte1); int spd_decode_ddr2(dimm_attr *dimm, spd_raw_data spd); void dram_print_spd_ddr2(const dimm_attr *dimm); - +int get_common_freq_cas(u8 freq_mask, u8 cas_mask, const dimm_attr **dimm, + int num_dimms, u8 *selected_freq, u8 *selected_cas); #endif /* DEVICE_DRAM_DDR2L_H */

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coreboot-gerrit February 2017