Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18211
-gerrit
commit 5696e7755fd3ec5220b839da942c95c8159fbdda
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Jan 13 22:17:01 2017 +0530
driver/i2c/max98927: add i2c driver for Maxim 98927 codec
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: M Naveen <naveen.m(a)intel.com>
Signed-off-by: Dylan Reid <dgreid(a)chromium.org>
---
src/drivers/i2c/max98927/Kconfig | 4 ++
src/drivers/i2c/max98927/Makefile.inc | 1 +
src/drivers/i2c/max98927/chip.h | 30 ++++++++++
src/drivers/i2c/max98927/max98927.c | 103 ++++++++++++++++++++++++++++++++++
4 files changed, 138 insertions(+)
diff --git a/src/drivers/i2c/max98927/Kconfig b/src/drivers/i2c/max98927/Kconfig
new file mode 100644
index 0000000..b193c6e
--- /dev/null
+++ b/src/drivers/i2c/max98927/Kconfig
@@ -0,0 +1,4 @@
+config DRIVERS_I2C_MAX98927
+ bool
+ default n
+ depends on HAVE_ACPI_TABLES
diff --git a/src/drivers/i2c/max98927/Makefile.inc b/src/drivers/i2c/max98927/Makefile.inc
new file mode 100644
index 0000000..3bafee1
--- /dev/null
+++ b/src/drivers/i2c/max98927/Makefile.inc
@@ -0,0 +1 @@
+ramstage-$(CONFIG_DRIVERS_I2C_MAX98927) += max98927.c
diff --git a/src/drivers/i2c/max98927/chip.h b/src/drivers/i2c/max98927/chip.h
new file mode 100644
index 0000000..c7101bc
--- /dev/null
+++ b/src/drivers/i2c/max98927/chip.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corp.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+/*
+ * Maxim MAX98927 audio codec devicetree bindings
+ */
+struct drivers_i2c_max98927_config {
+ /* I2C Bus Frequency in Hertz (default 400kHz) */
+ unsigned int bus_speed;
+ /* Set ‘1’ if I2S channel size is not 32bit. */
+ bool interleave_mode;
+ /* Identifier for chips */
+ unsigned int uid;
+ /* Device Description */
+ const char *desc;
+ /* ACPI Device Name */
+ const char *name;
+};
diff --git a/src/drivers/i2c/max98927/max98927.c b/src/drivers/i2c/max98927/max98927.c
new file mode 100644
index 0000000..4aaf79c
--- /dev/null
+++ b/src/drivers/i2c/max98927/max98927.c
@@ -0,0 +1,103 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/i2c.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <stdint.h>
+#include <string.h>
+#include "chip.h"
+
+#define MAX98927_ACPI_NAME "MAXI"
+#define MAX98927_ACPI_HID "MX98927"
+
+#define MAX98927_DP_INT(key, val) \
+ acpi_dp_add_integer(dp, "maxim," key, (val))
+
+static void max98927_fill_ssdt(struct device *dev)
+{
+ struct drivers_i2c_max98927_config *config = dev->chip_info;
+ const char *scope = acpi_device_scope(dev);
+ struct acpi_i2c i2c = {
+ .address = dev->path.i2c.device,
+ .mode_10bit = dev->path.i2c.mode_10bit,
+ .speed = config->bus_speed ? : I2C_SPEED_FAST,
+ .resource = scope,
+ };
+ struct acpi_dp *dp = NULL;
+
+ if (!dev->enabled || !scope)
+ return;
+
+ /* Device */
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ acpigen_write_name_string("_HID", MAX98927_ACPI_HID);
+ acpigen_write_name_integer("_UID", config->uid);
+ acpigen_write_name_string("_DDN", config->desc);
+ acpigen_write_STA(ACPI_STATUS_DEVICE_ALL_ON);
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpi_device_write_i2c(&i2c);
+ acpigen_write_resourcetemplate_footer();
+
+ /* Device Properties */
+ dp = acpi_dp_new_table("_DSD");
+
+ acpi_dp_add_integer(dp, "interleave_mode", config->interleave_mode);
+
+ acpi_dp_write(dp);
+
+ acpigen_pop_len(); /* Device */
+ acpigen_pop_len(); /* Scope */
+
+ printk(BIOS_INFO, "%s: %s address 0%xh\n",
+ acpi_device_path(dev), dev->chip_ops->name,
+ dev->path.i2c.device);
+}
+
+static const char *max98927_acpi_name(struct device *dev)
+{
+ struct drivers_i2c_max98927_config *config = dev->chip_info;
+
+ if (config->name)
+ return config->name;
+
+ return MAX98927_ACPI_NAME;
+}
+
+static struct device_operations max98927_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .acpi_name = &max98927_acpi_name,
+ .acpi_fill_ssdt_generator = &max98927_fill_ssdt,
+};
+
+static void max98927_enable(struct device *dev)
+{
+ dev->ops = &max98927_ops;
+}
+
+struct chip_operations drivers_i2c_max98927_ops = {
+ CHIP_NAME("Maxim MAX98927 Codec")
+ .enable_dev = &max98927_enable
+};
Daniel Kulesz (daniel.ina1(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18369
-gerrit
commit 142722e307ee3f86adbc38e9800cadf4b1cbfdd7
Author: Daniel Kulesz <daniel.ina1(a)googlemail.com>
Date: Wed Feb 15 14:35:43 2017 +0100
Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6.
The commit introduced a regression which is causing MC4 failures
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Signed-off-by: Daniel Kulesz <daniel.ina1(a)googlemail.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index 48658f5..ecdd4a2 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -72,9 +72,6 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
-
- if (pDCTstat->Status & (1 << SB_Registered))
- misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;
Daniel Kulesz (daniel.ina1(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18369
-gerrit
commit 29bcfeadc93e5786cb3e83d0b980b36e937d8d70
Author: Daniel Kulesz <daniel.ina1(a)googlemail.com>
Date: Wed Feb 15 14:35:43 2017 +0100
Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6.
The commit introduced a regression which is causing MC4 failuresi
when 8 RDIMMs are populated in a configuration with a single CPU
package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with
1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an
Opteron 6276. The MC4 failures did not occur anymore.
Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
Signed-off-by: Daniel Kulesz <daniel.ina1(a)googlemail.com>
---
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index 48658f5..ecdd4a2 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -72,9 +72,6 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
-
- if (pDCTstat->Status & (1 << SB_Registered))
- misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;
Daniel Kulesz (daniel.ina1(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18369
-gerrit
commit 9339bd342267469c791758a3677a220000c22ed5
Author: Daniel Kulesz <daniel.ina1(a)googlemail.com>
Date: Wed Feb 15 14:35:43 2017 +0100
Revert "nb/amd/mct_ddr3: Fix RDIMM training failure on Fam15h"
This reverts commit fec8872c9dee4411ba1a89fc8ec833a700b476c6.
The commit introduced a regression which is causing MC4 failures when 8 RDIMMs are populated in a configuration with a single CPU package. Using just 4 RDIMMs, the failure does not occur.
After reverting the commit, I tested configurations with 1 CPU (8x8=64GB) and 2 CPU packages (16x8=128GB) using an Opteron 6276. The MC4 failures did not occur anymore.
Change-Id: Ic6c9de84c38f772919597950ba540a3b5de68a65
---
src/northbridge/amd/amdmct/mct_ddr3/mctproc.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
index 48658f5..ecdd4a2 100644
--- a/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
+++ b/src/northbridge/amd/amdmct/mct_ddr3/mctproc.c
@@ -72,9 +72,6 @@ u32 mct_SetDramConfigMisc2(struct DCTStatStruc *pDCTstat,
misc2 |= ((cs_mux_67 & 0x1) << 27);
misc2 &= ~(0x1 << 26); /* CsMux45 = cs_mux_45 */
misc2 |= ((cs_mux_45 & 0x1) << 26);
-
- if (pDCTstat->Status & (1 << SB_Registered))
- misc2 |= 1 << SubMemclkRegDly;
} else if (pDCTstat->LogicalCPUID & (AMD_DR_Dx | AMD_DR_Cx)) {
if (pDCTstat->Status & (1 << SB_Registered)) {
misc2 |= 1 << SubMemclkRegDly;