Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18342
-gerrit
commit 3fe5a43df85695af6da4c803a1db29bf94f464dc
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Sat Feb 11 11:16:18 2017 -0800
drivers/spi: Add support for generating SPI device in SSDT
Similar to I2C driver, add support for generating SPI device and
required properties in SSDT for ACPI.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles succesfully. Verified SPI device generated in SSDT on
poppy.
Change-Id: Ic4da79c823131d54d9eb3652b86f6e40fe643ab5
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/drivers/spi/acpi/Kconfig | 18 +++++
src/drivers/spi/acpi/Makefile.inc | 16 +++++
src/drivers/spi/acpi/acpi.c | 146 ++++++++++++++++++++++++++++++++++++++
src/drivers/spi/acpi/chip.h | 32 +++++++++
4 files changed, 212 insertions(+)
diff --git a/src/drivers/spi/acpi/Kconfig b/src/drivers/spi/acpi/Kconfig
new file mode 100644
index 0000000..c1653d5
--- /dev/null
+++ b/src/drivers/spi/acpi/Kconfig
@@ -0,0 +1,18 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2017 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+config DRIVERS_SPI_ACPI
+ bool
+ depends on HAVE_ACPI_TABLES
diff --git a/src/drivers/spi/acpi/Makefile.inc b/src/drivers/spi/acpi/Makefile.inc
new file mode 100644
index 0000000..7ae6e45
--- /dev/null
+++ b/src/drivers/spi/acpi/Makefile.inc
@@ -0,0 +1,16 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright 2017 Google Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+# GNU General Public License for more details.
+#
+
+ramstage-$(CONFIG_DRIVERS_SPI_ACPI) += acpi.c
diff --git a/src/drivers/spi/acpi/acpi.c b/src/drivers/spi/acpi/acpi.c
new file mode 100644
index 0000000..0d7d2aa
--- /dev/null
+++ b/src/drivers/spi/acpi/acpi.c
@@ -0,0 +1,146 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi_device.h>
+#include <arch/acpigen.h>
+#include <console/console.h>
+#include <device/device.h>
+#include <device/path.h>
+#include <device/spi.h>
+#include <spi-generic.h>
+#include <stdint.h>
+#include <string.h>
+#include "chip.h"
+
+static int spi_acpi_get_bus(struct device *dev)
+{
+ struct device *spi_dev;
+ struct device_operations *ops;
+
+ if (!dev->bus || !dev->bus->dev)
+ return -1;
+
+ spi_dev = dev->bus->dev;
+ ops = spi_dev->ops;
+
+ if (ops && ops->ops_spi_bus &&
+ ops->ops_spi_bus->dev_to_bus)
+ return ops->ops_spi_bus->dev_to_bus(spi_dev);
+
+ return -1;
+}
+
+static void spi_acpi_fill_ssdt_generator(struct device *dev)
+{
+ struct drivers_spi_acpi_config *config = dev->chip_info;
+ const char *scope = acpi_device_scope(dev);
+ struct spi_cfg spi_cfg;
+ struct spi_slave slave;
+ int bus = -1, cs = dev->path.spi.cs;
+ struct acpi_spi spi = {
+ .device_select = cs,
+ .speed = config->speed ? : 1 * MHz,
+ .resource = scope,
+ };
+
+ if (!dev->enabled || !scope)
+ return;
+
+ bus = spi_acpi_get_bus(dev);
+ if (bus == -1) {
+ printk(BIOS_ERR, "%s: ERROR: Cannot get bus for device.\n",
+ dev_path(dev));
+ return;
+ }
+
+ if (!config->hid) {
+ printk(BIOS_ERR, "%s: ERROR: HID required.\n", dev_path(dev));
+ return;
+ }
+
+ if (spi_setup_slave(bus, cs, &slave)) {
+ printk(BIOS_ERR, "%s: ERROR: SPI setup failed.\n",
+ dev_path(dev));
+ return;
+ }
+
+ if (spi_get_config(&slave, &spi_cfg)) {
+ printk(BIOS_ERR, "%s: ERROR: SPI get config failed.\n",
+ dev_path(dev));
+ return;
+ }
+
+ spi.device_select_polarity = spi_cfg.cs_polarity;
+ spi.wire_mode = spi_cfg.wire_mode;
+ spi.data_bit_length = spi_cfg.data_bit_length;
+ spi.clock_phase = spi_cfg.clk_phase;
+
+ /* Device */
+ acpigen_write_scope(scope);
+ acpigen_write_device(acpi_device_name(dev));
+ acpigen_write_name_string("_HID", config->hid);
+ if (config->cid)
+ acpigen_write_name_string("_CID", config->cid);
+ acpigen_write_name_integer("_UID", config->uid);
+ if (config->desc)
+ acpigen_write_name_string("_DDN", config->desc);
+
+ /* Resources */
+ acpigen_write_name("_CRS");
+ acpigen_write_resourcetemplate_header();
+ acpi_device_write_spi(&spi);
+ acpi_device_write_interrupt(&config->irq);
+ acpigen_write_resourcetemplate_footer();
+
+ if (config->compat_string) {
+ struct acpi_dp *dsd = acpi_dp_new_table("_DSD");
+ acpi_dp_add_string(dsd, "compatible", config->compat_string);
+ acpi_dp_write(dsd);
+ }
+
+ acpigen_pop_len(); /* Device */
+ acpigen_pop_len(); /* Scope */
+}
+
+static const char *spi_acpi_name(struct device *dev)
+{
+ struct drivers_spi_acpi_config *config = dev->chip_info;
+ static char name[5];
+
+ if (config->name)
+ return config->name;
+
+ snprintf(name, sizeof(name), "S%03.3X", spi_acpi_get_bus(dev));
+ name[4] = '\0';
+ return name;
+}
+
+static struct device_operations spi_acpi_ops = {
+ .read_resources = DEVICE_NOOP,
+ .set_resources = DEVICE_NOOP,
+ .enable_resources = DEVICE_NOOP,
+ .acpi_name = &spi_acpi_name,
+ .acpi_fill_ssdt_generator = &spi_acpi_fill_ssdt_generator,
+};
+
+static void spi_acpi_enable(struct device *dev)
+{
+ dev->ops = &spi_acpi_ops;
+}
+
+struct chip_operations drivers_spi_acpi_ops = {
+ CHIP_NAME("SPI Device")
+ .enable_dev = &spi_acpi_enable
+};
diff --git a/src/drivers/spi/acpi/chip.h b/src/drivers/spi/acpi/chip.h
new file mode 100644
index 0000000..f0cc941
--- /dev/null
+++ b/src/drivers/spi/acpi/chip.h
@@ -0,0 +1,32 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __SPI_ACPI_CHIP_H__
+#define __SPI_ACPI_CHIP_H__
+
+#include <arch/acpi_device.h>
+
+struct drivers_spi_acpi_config {
+ const char *hid; /* ACPI _HID (required) */
+ const char *cid; /* ACPI _CID */
+ const char *name; /* ACPI Device Name */
+ const char *desc; /* Device Description */
+ unsigned uid; /* ACPI _UID */
+ unsigned speed; /* Bus speed in Hz (default 1MHz) */
+ const char *compat_string; /* Compatible string for _HID=PRP0001 */
+ struct acpi_irq irq; /* Interrupt */
+};
+
+#endif /* __SPI_ACPI_CHIP_H__ */
Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18340
-gerrit
commit 5f63a3abae5bf3270729b811c90fdede76945ee4
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Sat Feb 11 10:57:23 2017 -0800
device: Add a new "SPI" device type
Add support for a new "SPI" device type in the devicetree to bind a
device on the SPI bus. Allow device to provide chip select number for
the device as a parameter.
Add spi_bus_operations with operation dev_to_bus which allows SoCs to
define a translation method for converting "struct device" into a unique
SPI bus number.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully.
Change-Id: I86f09516d3cddd619fef23a4659c9e4eadbcf3fa
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/device/device_util.c | 10 ++++++++++
src/include/device/device.h | 2 ++
src/include/device/path.h | 10 +++++++++-
src/include/device/spi.h | 30 ++++++++++++++++++++++++++++++
4 files changed, 51 insertions(+), 1 deletion(-)
diff --git a/src/device/device_util.c b/src/device/device_util.c
index 1a0a60f..e31ade5 100644
--- a/src/device/device_util.c
+++ b/src/device/device_util.c
@@ -250,6 +250,9 @@ u32 dev_path_encode(device_t dev)
case DEVICE_PATH_GENERIC:
ret |= dev->path.generic.subid << 8 | dev->path.generic.id;
break;
+ case DEVICE_PATH_SPI:
+ ret |= dev->path.spi.cs;
+ break;
case DEVICE_PATH_NONE:
default:
break;
@@ -319,6 +322,10 @@ const char *dev_path(device_t dev)
"GENERIC: %d.%d", dev->path.generic.id,
dev->path.generic.subid);
break;
+ case DEVICE_PATH_SPI:
+ snprintf(buffer, sizeof (buffer), "SPI: %02x",
+ dev->path.spi.cs);
+ break;
default:
printk(BIOS_ERR, "Unknown device path type: %d\n",
dev->path.type);
@@ -390,6 +397,9 @@ int path_eq(struct device_path *path1, struct device_path *path2)
equal = (path1->generic.id == path2->generic.id) &&
(path1->generic.subid == path2->generic.subid);
break;
+ case DEVICE_PATH_SPI:
+ equal = (path1->spi.cs == path2->spi.cs);
+ break;
default:
printk(BIOS_ERR, "Unknown device type: %d\n", path1->type);
break;
diff --git a/src/include/device/device.h b/src/include/device/device.h
index 47509f7..e21384b 100644
--- a/src/include/device/device.h
+++ b/src/include/device/device.h
@@ -23,6 +23,7 @@ struct pci_bus_operations;
struct i2c_bus_operations;
struct smbus_bus_operations;
struct pnp_mode_ops;
+struct spi_bus_operations;
/* Chip operations */
struct chip_operations {
@@ -64,6 +65,7 @@ struct device_operations {
#endif
const struct pci_operations *ops_pci;
const struct i2c_bus_operations *ops_i2c_bus;
+ const struct spi_bus_operations *ops_spi_bus;
const struct smbus_bus_operations *ops_smbus_bus;
const struct pci_bus_operations * (*ops_pci_bus)(device_t dev);
const struct pnp_mode_ops *ops_pnp_mode;
diff --git a/src/include/device/path.h b/src/include/device/path.h
index 9d7fb38..849b579 100644
--- a/src/include/device/path.h
+++ b/src/include/device/path.h
@@ -14,6 +14,7 @@ enum device_path_type {
DEVICE_PATH_CPU_BUS,
DEVICE_PATH_IOAPIC,
DEVICE_PATH_GENERIC,
+ DEVICE_PATH_SPI,
/*
* When adding path types to this table, please also update the
@@ -33,7 +34,8 @@ enum device_path_type {
"DEVICE_PATH_CPU", \
"DEVICE_PATH_CPU_BUS", \
"DEVICE_PATH_IOAPIC", \
- "DEVICE_PATH_GENERIC" \
+ "DEVICE_PATH_GENERIC", \
+ "DEVICE_PATH_SPI", \
}
struct domain_path
@@ -58,6 +60,11 @@ struct i2c_path
unsigned mode_10bit;
};
+struct spi_path
+{
+ unsigned cs;
+};
+
struct apic_path
{
unsigned apic_id;
@@ -107,6 +114,7 @@ struct device_path {
struct cpu_path cpu;
struct cpu_bus_path cpu_bus;
struct generic_path generic;
+ struct spi_path spi;
};
};
diff --git a/src/include/device/spi.h b/src/include/device/spi.h
new file mode 100644
index 0000000..4315ebc
--- /dev/null
+++ b/src/include/device/spi.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Google Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __DEVICE_SPI_H__
+#define __DEVICE_SPI_H__
+
+struct device;
+struct spi_bus_operations {
+ /*
+ * This is a SoC-specific method that can be provided to translate the
+ * 'struct device' for a SPI controller into a unique SPI bus
+ * number. Returns -1 if the bus number for this bus cannot be
+ * determined.
+ */
+ int (*dev_to_bus)(struct device *dev);
+};
+
+#endif /* __DEVICE_SPI_H__ */
the following patch was just integrated into master:
commit a4b11e5c90a51dadc9b02ec080c0fb192cac3997
Author: Subrata Banik <subrata.banik(a)intel.com>
Date: Fri Feb 3 18:57:49 2017 +0530
soc/intel/skylake: Perform CPU MP Init before FSP-S Init
As per BWG, CPU MP Init (loading ucode) should be done prior
to BIOS_RESET_CPL. Hence, pull MP Init to BS_DEV_INIT_CHIPS Entry
(before FSP-S call).
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Boot to OS with all threads enabled.
Change-Id: Ia6f83d466fb27e1290da84abe7832dc814b5273a
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-on: https://review.coreboot.org/18287
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18287 for details.
-gerrit
the following patch was just integrated into master:
commit 408fda799a55c4d104178dfa733b4ade2ad454cf
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Dec 15 16:04:55 2016 -0700
src/Kconfig: Move bootblock behavior to arch/x86 as TODO suggested
The four options are only used in X86:
- BOOTBLOCK_SIMPLE
- BOOTBLOCK_NORMAL
- BOOTBLOCK_SOURCE
- SKIP_MAX_REBOOT_CNT_CLEAR
Move them all into src/arch/x86/Kconfig - this puts them in the chipset
menu instead of general setup.
Verified that this makes no significant changes to any config file.
Change-Id: I2798ef67a8c6aed5afac34322be15fdf0c794059
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/17909
Reviewed-by: Kyösti Mälkki <kyosti.malkki(a)gmail.com>
Reviewed-by: Marshall Dawson <marshalldawson3rd(a)gmail.com>
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/17909 for details.
-gerrit
the following patch was just integrated into master:
commit c8d16f49331fc3cfd3aebc7b2f47bad632fd665e
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Dec 15 15:35:12 2016 -0700
src/Kconfig: Remove 'default n' statements from early in Kconfig
For boolean types, 'n' is the default default value - it doesn't
NEED to be set. If it IS set, it prevents a later default from
being set. So by removing the 'default n' statements from the
early symbols, they can be overridden other places in the tree.
Verified that this makes no significant changes to any config file.
Change-Id: I1b5b66bd8a3df8154a348b5272c56c88829b3ab4
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/17908
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi(a)google.com>
See https://review.coreboot.org/17908 for details.
-gerrit