Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18368
-gerrit
commit fba2e33b53edb45f0beb8103fc0f77d7f081ed0e
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Tue Feb 14 23:00:57 2017 -0600
google/slippy: consolidate variants' common mainboard.asl code
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/mainboard/google/slippy/acpi/mainboard.asl | 39 ++++++++++++++++++++++
src/mainboard/google/slippy/dsdt.asl | 2 +-
.../falco/include/variant/acpi/mainboard.asl | 20 -----------
.../leon/include/variant/acpi/mainboard.asl | 24 -------------
.../peppy/include/variant/acpi/mainboard.asl | 20 -----------
.../wolf/include/variant/acpi/mainboard.asl | 24 -------------
6 files changed, 40 insertions(+), 89 deletions(-)
diff --git a/src/mainboard/google/slippy/acpi/mainboard.asl b/src/mainboard/google/slippy/acpi/mainboard.asl
new file mode 100644
index 0000000..35bc1b4
--- /dev/null
+++ b/src/mainboard/google/slippy/acpi/mainboard.asl
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License as
+ * published by the Free Software Foundation; version 2 of
+ * the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <onboard.h>
+
+Scope (\_SB)
+{
+ Device (LID0)
+ {
+ Name(_HID, EisaId("PNP0C0D"))
+ Method(_LID, 0)
+ {
+ Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
+ Return (\LIDS)
+ }
+
+ // There is no GPIO for LID, the EC pulses WAKE# pin instead.
+ // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
+ Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
+ }
+
+ Device (PWRB)
+ {
+ Name(_HID, EisaId("PNP0C0C"))
+ }
+}
+
+#include <variant/acpi/mainboard.asl>
diff --git a/src/mainboard/google/slippy/dsdt.asl b/src/mainboard/google/slippy/dsdt.asl
index 56771c2..7d41f9a 100644
--- a/src/mainboard/google/slippy/dsdt.asl
+++ b/src/mainboard/google/slippy/dsdt.asl
@@ -54,7 +54,7 @@ DefinitionBlock(
}
// Mainboard specific
- #include <variant/acpi/mainboard.asl>
+ #include "acpi/mainboard.asl"
// Thermal handler
#include "acpi/thermal.asl"
diff --git a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl
index 417dbfe..acf8a03 100644
--- a/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/slippy/variants/falco/include/variant/acpi/mainboard.asl
@@ -14,26 +14,6 @@
* GNU General Public License for more details.
*/
-#include <onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
Scope (\_SB.PCI0.I2C0)
{
Device (CTPA)
diff --git a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl
index 4afe310..8542f97 100644
--- a/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/slippy/variants/leon/include/variant/acpi/mainboard.asl
@@ -14,30 +14,6 @@
* GNU General Public License for more details.
*/
-#include <onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
-
- // There is no GPIO for LID, the EC pulses WAKE# pin instead.
- // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
- Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
Scope (\_SB.PCI0.I2C0)
{
Device (CTPA)
diff --git a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
index cc0c688..9a92135 100644
--- a/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/slippy/variants/peppy/include/variant/acpi/mainboard.asl
@@ -14,26 +14,6 @@
* GNU General Public License for more details.
*/
-#include <onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
Scope (\_SB.PCI0.I2C0)
{
Device (ETPA)
diff --git a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
index 335077c..764eac9 100644
--- a/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
+++ b/src/mainboard/google/slippy/variants/wolf/include/variant/acpi/mainboard.asl
@@ -14,30 +14,6 @@
* GNU General Public License for more details.
*/
-#include <onboard.h>
-
-Scope (\_SB)
-{
- Device (LID0)
- {
- Name(_HID, EisaId("PNP0C0D"))
- Method(_LID, 0)
- {
- Store (\_SB.PCI0.LPCB.EC0.LIDS, \LIDS)
- Return (\LIDS)
- }
-
- // There is no GPIO for LID, the EC pulses WAKE# pin instead.
- // There is no GPE for WAKE#, so fake it with PCI_EXP_WAKE
- Name (_PRW, Package(){ 0x69, 5 }) // PCI_EXP
- }
-
- Device (PWRB)
- {
- Name(_HID, EisaId("PNP0C0C"))
- }
-}
-
Scope (\_SB.PCI0.I2C0)
{
Device (CTPA)
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18367
-gerrit
commit b30efaba623814bebdaeded50b589e2b8e768324
Author: Paul Menzel <pmenzel(a)molgen.mpg.de>
Date: Fri Jan 20 17:30:00 2017 +0100
grub: Build module `boottime`
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.
Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
payloads/external/GRUB2/Makefile | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile
index c257f0e..137fec2 100644
--- a/payloads/external/GRUB2/Makefile
+++ b/payloads/external/GRUB2/Makefile
@@ -40,7 +40,8 @@ config: checkout
cd grub2 && ./autogen.sh
cd grub2/build && ../configure BUILD_CC="$(HOSTCC)" CC="$(HOSTCC)" \
TARGET_CC="$(CC)" \
- TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" CFLAGS=-O2 TARGET_CFLAGS=-Os --with-platform=coreboot
+ TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" CFLAGS=-O2 TARGET_CFLAGS=-Os --with-platform=coreboot \
+ --enable-boot-time
grub2: config
echo " MAKE GRUB2 $(NAME-y)"
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18367
-gerrit
commit ede95a4975cf25f54884b6fac1557ee7bd0e5b4e
Author: Paul Menzel <pmenzel(a)molgen.mpg.de>
Date: Fri Jan 20 17:30:00 2017 +0100
grub: Build module `boottime`
Configure GRUB to build with boot time statistics. That allows users to
add that module to GRUB by adding `boottime` to the list of extra modules.
Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
---
payloads/external/GRUB2/Makefile | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/payloads/external/GRUB2/Makefile b/payloads/external/GRUB2/Makefile
index c257f0e..137fec2 100644
--- a/payloads/external/GRUB2/Makefile
+++ b/payloads/external/GRUB2/Makefile
@@ -40,7 +40,8 @@ config: checkout
cd grub2 && ./autogen.sh
cd grub2/build && ../configure BUILD_CC="$(HOSTCC)" CC="$(HOSTCC)" \
TARGET_CC="$(CC)" \
- TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" CFLAGS=-O2 TARGET_CFLAGS=-Os --with-platform=coreboot
+ TARGET_OBJCOPY="$(OBJCOPY)" TARGET_STRIP="$(STRIP)" CFLAGS=-O2 TARGET_CFLAGS=-Os --with-platform=coreboot \
+ --enable-boot-time
grub2: config
echo " MAKE GRUB2 $(NAME-y)"
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18366
-gerrit
commit 9385a66ae9a0ddc4271e2ebd5163dac2023ceaa5
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Tue Feb 14 15:12:17 2017 -0800
intel/skylake: add function is_secondary_thread()
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/soc/intel/skylake/cpu.c | 8 ++++++++
src/soc/intel/skylake/include/soc/cpu.h | 1 +
2 files changed, 9 insertions(+)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index fd726c8..6e0ad1b 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -431,6 +431,14 @@ static int adjust_apic_id(int index, int apic_id)
return index;
}
+int is_secondary_thread(void)
+{
+ int apic_id;
+ apic_id = lapicid();
+
+ return (!ht_disabled) & (apic_id & 1);
+}
+
static void per_cpu_smm_trigger(void)
{
/* Relocate the SMM handler. */
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index ecb9833..bf720e6 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -63,5 +63,6 @@ int cpu_config_tdp_levels(void);
u32 cpu_family_model(void);
u32 cpu_stepping(void);
int cpu_is_ult(void);
+int is_secondary_thread(void);
#endif
the following patch was just integrated into master:
commit d0966d86d68795b64d3cf54af909339b74be1b6e
Author: YH Lin <yueherngl(a)google.com>
Date: Fri Feb 10 08:33:01 2017 -0800
mainboard/google/reef: add sand variant
Create the initial Sand variant which refers to the Reef.
Sand is APL board that derives from reference board Reef.
BRANCH=master
BUG=chrome-os-partner:62200
TEST=Build (as initial setup)
Signed-off-by: YH Lin <yueherngl(a)chromium.org>
Change-Id: Iba8c5653b6176676c759d2b48063f0c0c6cde625
Reviewed-on: https://review.coreboot.org/18324
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18324 for details.
-gerrit