the following patch was just integrated into master:
commit 901efea8abbb3131685fd69fd4ad7c5093c8cb3c
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Tue Feb 7 19:47:16 2017 +0100
libpayload: x86/exec - fix return value passing
The pointer to write the return value to is in %ecx, not %eax. Writing
to (%eax) leads to memory corruptions as %eax holds the return value,
e.g. would write zero to address zero for a "successful" returning
payload.
Change-Id: I82df27ae89a9e3d25f479ebdda2b50ea57565459
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: https://review.coreboot.org/18332
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18332 for details.
-gerrit
the following patch was just integrated into master:
commit d42c38b93cbfd93426a7789af6a0e03479c692e8
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Tue Feb 7 18:59:27 2017 +0100
libpayload: x86/exec - fix libpayload API magic value
According to coreboot’s payload API [1] the magic value passed to the
payload should be 0x12345678, not 12345678. Fix that.
[1] https://www.coreboot.org/Payload_API
Change-Id: I10a7f7b1a4aec100416c5e7e4ba7f8add10ef5c5
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: https://review.coreboot.org/18331
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18331 for details.
-gerrit
the following patch was just integrated into master:
commit 6abdbcd4dc19f3fc2344ffcd9e3790e2a708d6b2
Author: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Date: Mon Feb 6 13:03:52 2017 +0100
siemens/mc_apl1: Make basic settings for booting the mainboard
This commit makes a basic adjustment for GPIOs, device tree, flash map and
MRC settings. With these basic settings the mainboard boots into
Linux lubuntu 4.8.0-22-generic using SeaBIOS. More adjustments will follow.
Change-Id: Ia920d236814f2e6a9b777dd1e4b4feef0ddf7721
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Reviewed-on: https://review.coreboot.org/18292
Tested-by: build bot (Jenkins)
Reviewed-by: Werner Zeh <werner.zeh(a)siemens.com>
See https://review.coreboot.org/18292 for details.
-gerrit
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18366
-gerrit
commit 87d6fa08af73d2b9c5cf940b2baba4896d62362c
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Tue Feb 14 15:12:17 2017 -0800
intel/skylake: add function is_secondary_thread()
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/soc/intel/skylake/cpu.c | 11 +++++++++++
src/soc/intel/skylake/include/soc/cpu.h | 1 +
2 files changed, 12 insertions(+)
diff --git a/src/soc/intel/skylake/cpu.c b/src/soc/intel/skylake/cpu.c
index fd726c8..4784889 100644
--- a/src/soc/intel/skylake/cpu.c
+++ b/src/soc/intel/skylake/cpu.c
@@ -431,6 +431,17 @@ static int adjust_apic_id(int index, int apic_id)
return index;
}
+/* Check whether the current CPU is the sibling hyperthread. */
+int is_secondary_thread(void)
+{
+ int apic_id;
+ apic_id = lapicid();
+
+ if (!ht_disabled && (apic_id & 1))
+ return 1;
+ return 0;
+}
+
static void per_cpu_smm_trigger(void)
{
/* Relocate the SMM handler. */
diff --git a/src/soc/intel/skylake/include/soc/cpu.h b/src/soc/intel/skylake/include/soc/cpu.h
index ecb9833..bf720e6 100644
--- a/src/soc/intel/skylake/include/soc/cpu.h
+++ b/src/soc/intel/skylake/include/soc/cpu.h
@@ -63,5 +63,6 @@ int cpu_config_tdp_levels(void);
u32 cpu_family_model(void);
u32 cpu_stepping(void);
int cpu_is_ult(void);
+int is_secondary_thread(void);
#endif
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18347
-gerrit
commit ec3e4cee8460237c827bababeb813257086347bd
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sun Feb 12 12:54:42 2017 +0100
libpayload: Enable SSE on x86 by default
Enable SSE on x86 by default.
Turns on SSE instructions when present and allows
to use SSE optimized memcpy.
Change-Id: I8799f356622489f2386241f7a9053e9ac5b0c2d1
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
payloads/libpayload/Makefile | 3 +++
1 file changed, 3 insertions(+)
diff --git a/payloads/libpayload/Makefile b/payloads/libpayload/Makefile
index 429bf05..3828928 100644
--- a/payloads/libpayload/Makefile
+++ b/payloads/libpayload/Makefile
@@ -147,6 +147,9 @@ READELF := $(READELF_$(ARCH-y))
STRIP := $(STRIP_$(ARCH-y))
AR := $(AR_$(ARCH-y))
+# Enable SSE on x86
+CFLAGS_x86_32 += -msse
+
CFLAGS += $(CFLAGS_$(ARCH-y))
ifneq ($(INNER_SCANBUILD),y)
Patrick Rudolph (siro(a)das-labor.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18345
-gerrit
commit ac75e44df87f23c98123767ef7e62dd749748d43
Author: Patrick Rudolph <siro(a)das-labor.org>
Date: Sun Jan 15 10:49:48 2017 +0100
libpayload: Enable SSE and FPU when present
Use cpuid feature bits to detect and enable FPU and
SSE instructions.
Allows to use SSE and floating point in payloads without digging to
much into x86 assembly code.
Required for x86 SSE memcpy.
Change-Id: I4a5fc633f158de421b70435a8bfdc0dcaa504c72
Signed-off-by: Patrick Rudolph <siro(a)das-labor.org>
---
payloads/libpayload/arch/x86/main.c | 29 +++++++++++++++++++++++++++++
1 file changed, 29 insertions(+)
diff --git a/payloads/libpayload/arch/x86/main.c b/payloads/libpayload/arch/x86/main.c
index fbd4dc4..9376264 100644
--- a/payloads/libpayload/arch/x86/main.c
+++ b/payloads/libpayload/arch/x86/main.c
@@ -29,6 +29,7 @@
#include <exception.h>
#include <libpayload.h>
+#include <arch/cpuid.h>
unsigned long loader_eax; /**< The value of EAX passed from the loader */
unsigned long loader_ebx; /**< The value of EBX passed from the loader */
@@ -47,6 +48,34 @@ void start_main(void)
{
extern int main(int argc, char **argv);
+#if IS_ENABLED(CONFIG_LP_GPL)
+ /* Optionally set up cpuid */
+ get_cpuid();
+
+ /* Enable floating point processing */
+ if (cpu_id.fid.bits.fpu)
+ __asm__ __volatile__ (
+ "fninit\n\t"
+ "movl %%cr0, %%eax\n\t"
+ "andl $0xFFFFFFFB, %%eax\n\t" /* clear EM */
+ "orl $0x00000022, %%eax\n\t" /* set MP, NE */
+ "movl %%eax, %%cr0\n\t"
+ : :
+ : "ax"
+ );
+#ifdef __SSE__
+ /* Enable SSE instructions */
+ if (cpu_id.fid.bits.sse)
+ __asm__ __volatile__ (
+ "movl %%cr4, %%eax\n\t"
+ "orl $0x00000600, %%eax\n\t" /* set OSFXSR, OSXMMEXCPT */
+ "movl %%eax, %%cr4\n\t"
+ : :
+ : "ax"
+ );
+#endif
+#endif
+
/* Gather system information. */
lib_get_sysinfo();