Subrata Banik (subrata.banik(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18221
-gerrit
commit 9e4bcb9823a93c2297d0be6f8363a86c88ce2bb3
Author: Subrata Banik <subrata.banik(a)intel.com>
Date: Thu Feb 16 16:08:49 2017 +0530
soc/intel/common/block: Add Intel XHCI driver support
Create sample model for common Intel XHCI driver.
Change-Id: I81f57bc713900c96d998bae924fc4d38a9024fe3
Signed-off-by: Subrata Banik <subrata.banik(a)intel.com>
---
.../intel/common/block/include/intelblocks/xhci.h | 22 +++++++++++
src/soc/intel/common/block/xhci/Kconfig | 4 ++
src/soc/intel/common/block/xhci/Makefile.inc | 7 ++++
src/soc/intel/common/block/xhci/xhci.c | 44 ++++++++++++++++++++++
4 files changed, 77 insertions(+)
diff --git a/src/soc/intel/common/block/include/intelblocks/xhci.h b/src/soc/intel/common/block/include/intelblocks/xhci.h
new file mode 100644
index 0000000..9ea2312
--- /dev/null
+++ b/src/soc/intel/common/block/include/intelblocks/xhci.h
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef SOC_INTEL_XHCI_H
+#define SOC_INTEL_XHCI_H
+
+void xhci_init(struct device *dev);
+
+#endif /* SOC_INTEL_XHCI_H */
+
diff --git a/src/soc/intel/common/block/xhci/Kconfig b/src/soc/intel/common/block/xhci/Kconfig
new file mode 100644
index 0000000..7070dd3
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/Kconfig
@@ -0,0 +1,4 @@
+config SOC_INTEL_XHCI_DRIVER
+ bool
+ help
+ Intel Processor XHCI Driver support
diff --git a/src/soc/intel/common/block/xhci/Makefile.inc b/src/soc/intel/common/block/xhci/Makefile.inc
new file mode 100644
index 0000000..826f3da
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/Makefile.inc
@@ -0,0 +1,7 @@
+ifeq ($(CONFIG_SOC_INTEL_XHCI_DRIVER),y)
+
+ramstage-y += xhci.c
+
+CPPFLAGS_common += -I$(src)/soc/intel/common/block/include
+
+endif
diff --git a/src/soc/intel/common/block/xhci/xhci.c b/src/soc/intel/common/block/xhci/xhci.c
new file mode 100644
index 0000000..ca90376
--- /dev/null
+++ b/src/soc/intel/common/block/xhci/xhci.c
@@ -0,0 +1,44 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2014 Google Inc.
+ * Copyright (C) 2015 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <console/console.h>
+#include <device/device.h>
+#include <device/pci.h>
+#include <device/pci_ids.h>
+#include <arch/io.h>
+#include <intelblocks/xhci.h>
+
+__attribute__((weak)) void xhci_init(struct device *dev) { /* no-op */ }
+
+static struct device_operations usb_xhci_ops = {
+ .read_resources = &pci_dev_read_resources,
+ .set_resources = &pci_dev_set_resources,
+ .enable_resources = &pci_dev_enable_resources,
+ .init = xhci_init,
+};
+
+static const unsigned short pci_device_ids[] = {
+ 0x5aa8, /* ApolloLake */
+ 0x31a8, /* GLK */
+ 0x9d2f, /* SunRisePoint LP */
+ 0
+};
+
+static const struct pci_driver pch_usb_xhci __pci_driver = {
+ .ops = &usb_xhci_ops,
+ .vendor = PCI_VENDOR_ID_INTEL,
+ .devices = pci_device_ids,
+};
Mathias Krause (minipli(a)googlemail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18333
-gerrit
commit 43221466f74a4972c7b5851953d594e10d238e1e
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 22:34:46 2017 +0100
libpayload: x86/exec - fix argc/argv value passing
According to coreboot’s payload API [1] the argc value should be passed
at stack offset 0x10, so we need to push a dummy value to comply to the
API.
[1] https://www.coreboot.org/Payload_API
Change-Id: Id20424185a5bf7e4d94de1886a2cece3f3968371
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
---
payloads/libpayload/arch/x86/exec.S | 7 ++++++-
1 file changed, 6 insertions(+), 1 deletion(-)
diff --git a/payloads/libpayload/arch/x86/exec.S b/payloads/libpayload/arch/x86/exec.S
index 7d89cc0..54c83f6 100644
--- a/payloads/libpayload/arch/x86/exec.S
+++ b/payloads/libpayload/arch/x86/exec.S
@@ -53,12 +53,17 @@ i386_do_exec:
pushl %ecx
pushl %ebp
- /* Push the argc and argv pointers on to the stack */
+ /* Push argc and argv on to the stack.
+ *
+ * We need to put a dummy value inbetween, as argc should be at offset
+ * 0x10, according to the payload API.
+ */
movl 12(%ebp), %esi
movl 16(%ebp), %ecx
pushl %esi
+ pushl $0
pushl %ecx
/* Move a "magic" number on the stack - the other
the following patch was just integrated into master:
commit 231c198e2ce56741c945149a6c553b1f4e81a4e2
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Sat Feb 11 12:02:40 2017 -0800
mainboard/google/eve: Generate FPC device using SPI SSDT generator
Use the newly added SPI SSDT generator for adding FPC device.
BUG=chrome-os-partner:59832
BRANCH=None
TEST=Compiles successfully. Verified that the SSDT entry matches the
entry in mainboard.asl
Change-Id: I1b3c33f2b4337735a9725dd4eb6193b2455962d7
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18343
Tested-by: build bot (Jenkins)
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/18343 for details.
-gerrit