Rizwan Qureshi (rizwan.qureshi(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18312
-gerrit
commit 8a52085f8343daa29ab62ea04f1a2e0a7443f450
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Thu Feb 9 15:57:45 2017 +0530
soc/intel/skylake: Add config option for Kabylake
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
---
src/soc/intel/skylake/Kconfig | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/src/soc/intel/skylake/Kconfig b/src/soc/intel/skylake/Kconfig
index 090fa2a..9dcafe6 100644
--- a/src/soc/intel/skylake/Kconfig
+++ b/src/soc/intel/skylake/Kconfig
@@ -3,6 +3,13 @@ config SOC_INTEL_SKYLAKE
help
Intel Skylake support
+config SOC_INTEL_KABYLAKE
+ bool
+ default n
+ select SOC_INTEL_SKYLAKE
+ help
+ Intel Kabylake support
+
if SOC_INTEL_SKYLAKE
config CPU_SPECIFIC_OPTIONS
the following patch was just integrated into master:
commit c57c48bd36c69bfb5e783281c7c5aba8ba5b4bee
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Wed Feb 15 09:53:50 2017 -0800
mainboard/google/poppy: Generate digitizer node in SSDT
Add support for generating digitizer node in SSDT using wacom i2c
driver.
BUG=None
BRANCH=None
TEST=Verified that the node shows up in SSDT.
Change-Id: If7e1e2463778c2ff7263eff995def149457edcde
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18373
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18373 for details.
-gerrit
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18362
-gerrit
commit a90add7a69852826e376116ff19c099b4a778c0e
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 13:44:14 2017 -0800
arch/x86: add functions to generate random numbers
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/arch/x86/Makefile.inc | 1 +
src/arch/x86/rdrand.c | 83 +++++++++++++++++++++++++++++++++++++++++++++++
src/include/random.h | 27 +++++++++++++++
3 files changed, 111 insertions(+)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index c4bb1cc..332e8ec 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -334,6 +334,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
+ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
ramstage-y += tables.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
new file mode 100644
index 0000000..dc7ed60
--- /dev/null
+++ b/src/arch/x86/rdrand.c
@@ -0,0 +1,83 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <random.h>
+#include <rules.h>
+
+/*
+ * Intel recommends that applications attempt 10 retries in a tight loop
+ * in the unlikely event that the RDRAND instruction does not successfully
+ * return a random number. The odds of ten failures in a row would in fact
+ * be an indication of a larger CPU issue.
+ */
+#define RDRAND_RETRY_LOOPS 10
+
+/*
+ * Generate a 32-bit random number through RDRAND instruction.
+ * Carry flag is set on RDRAND success and 0 on failure.
+ */
+static inline uint8_t rdrand_32(uint32_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+/*
+ * Generate a 64-bit random number through RDRAND instruction.
+ * Carry flag is set on RDRAND success and 0 on failure.
+ */
+static inline uint8_t rdrand_64(uint64_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+int get_random_number_32(uint32_t *rand)
+{
+ int i;
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (rdrand_32(rand))
+ return 0;
+ }
+ return -1;
+}
+
+int get_random_number_64(uint64_t *rand)
+{
+ int i;
+ uint32_t rand_high, rand_low;
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (ENV_X86_64 && rdrand_64(rand))
+ return 0;
+ else if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) {
+ *rand = ((uint64_t)rand_high << 32) |
+ (uint64_t)rand_low;
+ return 0;
+ }
+ }
+ return -1;
+}
diff --git a/src/include/random.h b/src/include/random.h
new file mode 100644
index 0000000..cdb4415
--- /dev/null
+++ b/src/include/random.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _RANDOM_H_
+#define _RANDOM_H_
+
+#include <stdint.h>
+
+/*
+ * Generates a 32/64 bit random number respectively.
+ * return 0 on success and -1 on error.
+ */
+int get_random_number_32(uint32_t *rand);
+int get_random_number_64(uint64_t *rand);
+
+#endif /* _RANDOM_H_ */
Denis 'GNUtoo' Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/6660
-gerrit
commit fac54b1abd8d4a577dcfa5bc54573cae4377fd18
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Thu Aug 14 11:58:04 2014 +0200
board-status: Add README
It explains the prerequisites to run the script, some
background on how to setup the computer running the script,
and the board it gathers the information from.
That information is too long to fit inside the script's
help.
Change-Id: Iecba7310ff1583149c02728e955716775bcbbdc4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
util/board_status/README | 50 ++++++++++++++++++++++++++++++++++++++++++++++++
1 file changed, 50 insertions(+)
diff --git a/util/board_status/README b/util/board_status/README
new file mode 100644
index 0000000..2337826
--- /dev/null
+++ b/util/board_status/README
@@ -0,0 +1,50 @@
+General information on boot logs
+================================
+To gather good boot logs, you must set the debug level to Spew.
+
+If your board uses CMOS configuration[1], you can do it like this:
+nvramtool -w debug_level=Spew
+
+Else you will need to have to set the default log level at compile
+time, to do that go in "Console --->" in make menuconfig, then set
+"Default console log level" to SPEW
+
+Rereference:
+------------
+[1] in make menuconfig you should have: [*] Use CMOS for configuration values
+ This option is also known as CONFIG_USE_OPTION_TABLE in Kconfig.
+Information trough SSH
+======================
+board_status.sh can gather information trough ssh with the -r
+option.
+
+When using "-r <host>", The script will attempt to log into
+root@<host>.
+In order for "-r <host>" to work, the script has to be able
+to log into the remote host's root account, without having
+to provide a password.
+That can be achieved with the use of SSH keys and ssh-agent.
+
+board_status.sh expects the remote host to have the following
+programs in its path: cbmem, dmesg
+
+Boot log gathering trough a serial port
+=======================================
+When using -s </dev/xxx>, board_status.sh starts by retrieving the
+boot log trough the serial port.
+
+To produce such logs, power off the board, run board_status.sh
+with the right arguments, power on the board.
+At that point the logs will be displayed by board_status.sh as they
+are produced by the board.
+
+Enter will have to be pressed once the board has booted and is in a
+state where the script is able to log into that board.
+
+Publishing
+==========
+The -u switch will publish the results: It will make a git patch out
+of the status information, that will be directly pushed in the
+board-status repository.
+It expects the user to already have an account in coreboot's gerrit
+instance.
Robbie Zhang (robbie.zhang(a)intel.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18362
-gerrit
commit 10dd5a6332364b41abe0732e5b094cc5f925545b
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 13:44:14 2017 -0800
arch/x86: add functions to generate random numbers
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
---
src/arch/x86/Makefile.inc | 1 +
src/arch/x86/rdrand.c | 85 +++++++++++++++++++++++++++++++++++++++++++++++
src/include/rdrand.h | 27 +++++++++++++++
3 files changed, 113 insertions(+)
diff --git a/src/arch/x86/Makefile.inc b/src/arch/x86/Makefile.inc
index c4bb1cc..332e8ec 100644
--- a/src/arch/x86/Makefile.inc
+++ b/src/arch/x86/Makefile.inc
@@ -334,6 +334,7 @@ ramstage-$(CONFIG_GENERATE_MP_TABLE) += mpspec.c
ramstage-y += pci_ops_conf1.c
ramstage-$(CONFIG_MMCONF_SUPPORT) += pci_ops_mmconf.c
ramstage-$(CONFIG_GENERATE_PIRQ_TABLE) += pirq_routing.c
+ramstage-y += rdrand.c
ramstage-$(CONFIG_GENERATE_SMBIOS_TABLES) += smbios.c
ramstage-y += tables.c
ramstage-$(CONFIG_COOP_MULTITASKING) += thread.c
diff --git a/src/arch/x86/rdrand.c b/src/arch/x86/rdrand.c
new file mode 100644
index 0000000..693aa6c
--- /dev/null
+++ b/src/arch/x86/rdrand.c
@@ -0,0 +1,85 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+
+#include <rdrand.h>
+#include <rules.h>
+
+/*
+ * Intel recommends that applications attempt 10 retries in a tight loop
+ * in the unlikely event that the RDRAND instruction does not successfully
+ * return a random number. The odds of ten failures in a row would in fact
+ * be an indication of a larger CPU issue.
+ */
+#define RDRAND_RETRY_LOOPS 10
+
+/*
+ * Generate a 32-bit random number through RDRAND instruction.
+ * Carry flag is set on RDRAND success and 0 on failure.
+ */
+static inline uint8_t rdrand_32(uint32_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+/*
+ * Generate a 64-bit random number through RDRAND instruction.
+ * Carry flag is set on RDRAND success and 0 on failure.
+ */
+static inline uint8_t rdrand_64(uint64_t *rand)
+{
+ uint8_t carry;
+
+ __asm__ __volatile__(
+ ".byte 0x48; .byte 0x0f; .byte 0xc7; .byte 0xf0; setc %1"
+ : "=a" (*rand), "=qm" (carry));
+ return carry;
+}
+
+int get_random_number_32(uint32_t *rand)
+{
+ int i;
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (rdrand_32(rand))
+ return 0;
+ }
+ return -1;
+}
+
+int get_random_number_64(uint64_t *rand)
+{
+ int i;
+#if !defined(__x86_64__)
+ uint32_t rand_high, rand_low;
+#endif
+
+ /* Perform a loop call until RDRAND succeeds or returns failure. */
+ for (i = 0; i < RDRAND_RETRY_LOOPS; i++) {
+ if (ENV_X86_64 && rdrand_64(rand))
+ return 0;
+ else if (rdrand_32(&rand_high) && rdrand_32(&rand_low)) {
+ *rand = ((uint64_t)rand_high << 32) |
+ (uint64_t)rand_low;
+ return 0;
+ }
+ }
+ return -1;
+}
diff --git a/src/include/rdrand.h b/src/include/rdrand.h
new file mode 100644
index 0000000..93036a9
--- /dev/null
+++ b/src/include/rdrand.h
@@ -0,0 +1,27 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright 2017 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ */
+#ifndef _RDRAND_H_
+#define _RDRAND_H_
+
+#include <stdint.h>
+
+/*
+ * Generates a 32/64 bit random number respectively.
+ * return 0 on success and -1 on error.
+ */
+int get_random_number_32(uint32_t *rand);
+int get_random_number_64(uint64_t *rand);
+
+#endif /* _RDRAND_H_ */
Denis 'GNUtoo' Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12709
-gerrit
commit ec942d88f6cd245868379b7208e7b9068520085a
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Thu Dec 10 21:58:52 2015 +0100
GDB_WAIT: Clarify Kconfig description
The user has to know in which stage gdb is waiting to be able to
use symbolic debugging.
Change-Id: Ia992e7a2077b92c45546ae56c5fb648775f8f63b
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
src/Kconfig | 5 +++--
1 file changed, 3 insertions(+), 2 deletions(-)
diff --git a/src/Kconfig b/src/Kconfig
index 74b892e..cdc0a44 100644
--- a/src/Kconfig
+++ b/src/Kconfig
@@ -673,11 +673,12 @@ config GDB_STUB
See src/arch/x86/lib/c_start.S for details.
config GDB_WAIT
- bool "Wait for a GDB connection"
+ bool "Wait for a GDB connection in the ramstage"
default n
depends on GDB_STUB
help
- If enabled, coreboot will wait for a GDB connection.
+ If enabled, coreboot will wait for a GDB connection in the ramstage.
+
config FATAL_ASSERTS
bool "Halt when hitting a BUG() or assertion error"
Denis 'GNUtoo' Carikli (GNUtoo(a)no-log.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/11889
-gerrit
commit 4be450a83dea8212bc761a9bea5baa16b0c1e905
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Tue Feb 14 17:31:26 2017 +0100
boardstatus: wiki: Update XiVO's coreboot fork source address
This company doesn't do custom hardware anymore and doesn't
host the sources anymore. We therefore point to the archived
sources instead.
Change-Id: I5ce4f6a468b852fc1d0947fe2b28a5297f14c437
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
---
util/board_status/to-wiki/foreword.wiki | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/util/board_status/to-wiki/foreword.wiki b/util/board_status/to-wiki/foreword.wiki
index 631cca4..1774f15 100644
--- a/util/board_status/to-wiki/foreword.wiki
+++ b/util/board_status/to-wiki/foreword.wiki
@@ -35,5 +35,5 @@ code for boards that are not yet merged.
= Vendor trees =
Some vendors have their own coreboot trees/fork, like for instance:
-* [http://git.xivo.fr/?p=official/xioh/coreboot.git;a=summary xivo's tree]
+* [http://mirror.wazo.community/iso/archives/git/xioh/coreboot.git.tar.bz2 xivo's tree]
* [http://git.chromium.org/gitweb/?p=chromiumos/third_party/coreboot.git;a=sum… chrome/chromium's tree]