Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18385
-gerrit
commit c3622a5f162e37a532b02eac2aec809920627be8
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Feb 16 11:36:16 2017 -0600
lynxpoint/broadwell: fix PCH power optimizer
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/soc/intel/broadwell/lpc.c | 2 +-
src/southbridge/intel/lynxpoint/lpc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index c1600c5..610b977 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -262,7 +262,7 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
/* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00000080),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 04cb0bd..d295c88 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -347,7 +347,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
- RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
+ RCBA_RMW_REG_32(0x33c8, ~0, 0x00000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
the following patch was just integrated into master:
commit 7c7b1761691864158c51d6a99f74e2e4a3e9ca0e
Author: Paul Menzel <pmenzel(a)molgen.mpg.de>
Date: Fri Jan 20 17:30:00 2017 +0100
grub: Build module `boottime`
Configure GRUB to build with boot time statistics. That allows users
to add that module to GRUB by adding `boottime` to the list of extra
modules.
Change-Id: I76a07e49aecb37652fe8c7d6a9421fd464424287
Signed-off-by: Paul Menzel <pmenzel(a)molgen.mpg.de>
Reviewed-on: https://review.coreboot.org/18367
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Rudolph <siro(a)das-labor.org>
See https://review.coreboot.org/18367 for details.
-gerrit
the following patch was just integrated into master:
commit 898de6111ad79519afe04794df8e09c41500807d
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sun Feb 12 13:50:48 2017 +0100
libpayload: multiboot - support meminfo flag
Some simple implementation of the MultiBoot protocol may not pass a
memory map (MULTIBOOT_FLAGS_MMAP missing in the flags) but just the two
values for low and high memory, indicated by the MULTIBOOT_FLAGS_MEMINFO
flag.
Support those kind of boot loaders too, instead of falling back to the
hard-coded values in lib_get_sysinfo().
Tested with a multiboot enhanced version of FILO.
Change-Id: I22cf9e3ec0075aff040390bd177c5cd22d439b81
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: https://review.coreboot.org/18350
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18350 for details.
-gerrit
Paul Menzel (paulepanter(a)users.sourceforge.net) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/5957
-gerrit
commit 2e6273fa17078d53e68cf6ab913ab1330f0684b4
Author: Paul Menzel <paulepanter(a)users.sourceforge.net>
Date: Sat Jun 7 21:50:21 2014 +0200
device/Kconfig: Select native graphics init by default
We want to always build-test native VGA init, and encourage
people to use it instead of VBIOS.
Change-Id: I47ed328ce8ce3516ad3997978a01d2359d9b1ca8
Signed-off-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Signed-off-by: Francis Rowe <info(a)gluglug.org.uk>
---
src/device/Kconfig | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 4036a3d..48aa6e4 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -34,7 +34,7 @@ config MAINBOARD_HAS_NATIVE_VGA_INIT_TEXTMODECFG
config MAINBOARD_DO_NATIVE_VGA_INIT
bool "Use native graphics initialization"
depends on MAINBOARD_HAS_NATIVE_VGA_INIT
- default n
+ default y
help
Some mainboards, such as the Google Link, allow initializing the display
without the need of a binary only VGA OPROM. Enabling this option may be
the following patch was just integrated into master:
commit 2b194d97411bd86303e0fec3a2edae2a718466bc
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Tue Feb 14 15:12:17 2017 -0800
intel/skylake: add function is_secondary_thread()
There are MSRs that are programmable per-core not per-thread, so add
a function to check whether current executing CPU is a primary core
or a "hyperthreaded"/secondary core. For instance when trying to
program Core PRMRR MSRs(per-core) with mp_init, cpu exception is thrown
from the secondary thread. This function was used to avoid that.
Potentially this function can be put to common code or arch/x86 or cpu/x86.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified core PRMRR MSRs get programmed only on primary
thread avoiding exeception.
Change-Id: Ic9648351fadf912164a39206788859baf3e5c173
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Reviewed-on: https://review.coreboot.org/18366
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18366 for details.
-gerrit
the following patch was just integrated into master:
commit d2f16cac749065e373b0558c850a8d9d2254c700
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 22:47:04 2017 +0100
libpayload: x86/head - implement argc/argv handling
Implement the argc/argv passing as described in coreboot’s payload API:
http://www.coreboot.org/Payload_API
While at it, give the code some love by not needlessly trashing register
values.
Change-Id: Ib830f2c67b631b7216843203cefd55d9bb780d83
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: https://review.coreboot.org/18336
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/18336 for details.
-gerrit
the following patch was just integrated into master:
commit 57dc93c967f45167f09e7817266ebb4f3dbda62a
Author: Mathias Krause <minipli(a)googlemail.com>
Date: Sat Feb 11 21:02:08 2017 +0100
libpayload: x86/exec - simplify and robustify the code
Simplify the code by directly using the arguments on the stack as base
pointer relative memory references, instead of loading them into
intermediate registers first.
Make it more robust by preserving all callee saved registers mandated by
the C calling convention (and only those), namely EBP, EBX, ESI and EDI.
Don't assume anything about the register state when the called function
returns -- beside the segment registers and the stack pointer to be
still the same as before the call.
Change-Id: I383d6ccefc5b3d5cca37a1c9b638c231bbc48aa8
Signed-off-by: Mathias Krause <minipli(a)googlemail.com>
Reviewed-on: https://review.coreboot.org/18335
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
Tested-by: build bot (Jenkins)
See https://review.coreboot.org/18335 for details.
-gerrit