the following patch was just integrated into master:
commit 97e13d84c30c308c3b2bc629b38e6bcc9565dc3a
Author: Arthur Heymans <arthur(a)aheymans.xyz>
Date: Wed Nov 30 18:40:38 2016 +0100
nb/intel/x4x: Fix raminit on reset path
Previously the raminit failed on hot reset and to work around this
issue it unconditionally did a cold reset.
This has the following issues:
* it's slow;
* when the OS issues a hot reset some disk drives expect their 5V
power supply to remain on, which gets cut off by a cold reset,
causing data corruption.
To fix this some steps in raminit must be ommited on the reset path.
This includes receive enable calibration.
To achieve this it stores receive enable results in RTC nvram for them
to be rewritten on the resume path.
Note: The same thing needs to be done on the S3 resume path.
Calling a hot reset after raminit "outb(0x6, 0cf9)" works.
Change-Id: I6601dd90aebd071a0de7cec070487b0f9845bc30
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Reviewed-on: https://review.coreboot.org/18009
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18009 for details.
-gerrit
the following patch was just integrated into master:
commit 17335fab175ed1a16f61729b03c1fbeeec366f37
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Sat Jan 14 06:08:21 2017 +0530
soc/intel/skylake: Add Maxim 98927 and Realtek 5663 NHLT blob support
Add APIs and required parameters for creating Maxim 98927
and Realtek 5336 SSP endpoints in NHLT table.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=check that NHLT table created is created properly
Change-Id: Ica302aab05c5364faf4923dc5327be8e8eaae8b4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Signed-off-by: M Naveen <naveen.m(a)intel.com>
Reviewed-on: https://review.coreboot.org/18213
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18213 for details.
-gerrit
the following patch was just integrated into master:
commit 4979d7610e74b83f7b41b10ac30b4fb619b4e26d
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Fri Jan 13 22:17:01 2017 +0530
driver/i2c/max98927: add i2c driver for Maxim 98927 codec
Maxim 98927 kernel driver requires entries in the ACPI SSDT table,
add a SSDT generator as part of this driver.
BUG=chrome-os-partner:62051
BRANCH=None
TEST=After boot, dump and verify that the generated SSDT ACPI table has the
required entries.
Change-Id: Ic2d4d8449288bc00d085852220b2e1e7a208e9ef
Signed-off-by: Naresh G Solanki <naresh.solanki(a)intel.com>
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Signed-off-by: M Naveen <naveen.m(a)intel.com>
Signed-off-by: Dylan Reid <dgreid(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18211
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18211 for details.
-gerrit
the following patch was just integrated into master:
commit ceccb6ba53fbf42dd923759e888b84eb4e01b570
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Thu Feb 9 16:34:08 2017 +0530
mainboard/eve: select SOC_INTEL_KABYLAKE
eve is based on Kabylake SoC hence select the appropriate
config.
Change-Id: I756dda5a1924e83a02ac1cebb1907884f436a13f
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/18314
Tested-by: build bot (Jenkins)
Reviewed-by: Subrata Banik <subrata.banik(a)intel.com>
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18314 for details.
-gerrit
the following patch was just integrated into master:
commit b2b98f7ae1e75b9e7e35425741684385767cdfa5
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Thu Feb 9 16:32:20 2017 +0530
mainboard/poppy: select SOC_INTEL_KABYLAKE
poppy is based on Kabylake SoC hence select the appropriate
config.
Change-Id: Ie339a3991eeccb8a7dba983a2b5ab5d1c996ce9d
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/18313
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18313 for details.
-gerrit
the following patch was just integrated into master:
commit 0700dca96994b9657307486f5bea8d007f70864c
Author: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Date: Thu Feb 9 15:57:45 2017 +0530
soc/intel/skylake: Add config option for Kabylake
Currently there is no distinction between mainboards using
Skylake or Kabylake SoC, Add a config option for Kabylake
SoC to allow mainboards to explicitly select if they are
using it.
Change-Id: Ie7960bd81f88a223894afe3115ddc0bc637e4be4
Signed-off-by: Rizwan Qureshi <rizwan.qureshi(a)intel.com>
Reviewed-on: https://review.coreboot.org/18312
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18312 for details.
-gerrit