the following patch was just integrated into master:
commit e65affa2ed5d4fea584532c5cf27bf51ed1f56eb
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 12:07:53 2017 -0800
soc/intel/skylake: add PrmrrSize to chip config
Prmrr configuration is supported by Kabylake FSP-M with UPD provided.
It is required as one of the SGX initialization steps in BIOS.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve, verified uncore PRMRR MSRs get programmed to set
size and boot.
Change-Id: I2b3dc7c92487505165ee429bd1a37bd60ceac8f3
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Reviewed-on: https://review.coreboot.org/18361
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter(a)users.sourceforge.net>
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18361 for details.
-gerrit
Furquan Shaikh (furquan(a)google.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18399
-gerrit
commit 397430619599005a999430c8bcd8f34706a321d1
Author: Furquan Shaikh <furquan(a)chromium.org>
Date: Fri Feb 17 21:03:26 2017 -0800
mainboard/google/reef: Remove config DRIVERS_GENERIC_GPIO_REGULATOR
Since we are not using gpio regulators on reef anymore, remove the
selection from Kconfig as well.
BUG=None
BRANCH=None
TEST=Compiles successfully.
Change-Id: Iae7d88dec3ac476d65b292f97a6ba3add71ce07a
Signed-off-by: Furquan Shaikh <furquan(a)chromium.org>
---
src/mainboard/google/reef/Kconfig | 3 ---
1 file changed, 3 deletions(-)
diff --git a/src/mainboard/google/reef/Kconfig b/src/mainboard/google/reef/Kconfig
index 856dd84..077cb7c 100644
--- a/src/mainboard/google/reef/Kconfig
+++ b/src/mainboard/google/reef/Kconfig
@@ -53,9 +53,6 @@ config DRIVERS_I2C_WACOM
config DRIVERS_PS2_KEYBOARD
default y
-config DRIVERS_GENERIC_GPIO_REGULATOR
- default y
-
config MAINBOARD_DIR
string
default google/reef
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18397
-gerrit
commit 6e3a9c43f9f8cada386b7cafeff26335efe9a9d2
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:27:51 2017 -0800
google/eve: Set touchscreen I2C bus speed to 1MHz
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 9d46915..e5744e3 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -210,6 +210,7 @@ chip soc/intel/skylake
register "generic.cid" = "PNP0C50_CID"
register "generic.desc" = "WCOM_DT_DESC"
register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.speed" = "I2C_SPEED_FAST_PLUS"
register "hid_desc_reg_offset" = "0x1"
device i2c 0a on end
end
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18397
-gerrit
commit 01c088cafdc7a0260bb477cc8f636500886ff337
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:27:51 2017 -0800
google/eve: Set touchscreen I2C bus speed to 1MHz
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 9d46915..e5744e3 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -210,6 +210,7 @@ chip soc/intel/skylake
register "generic.cid" = "PNP0C50_CID"
register "generic.desc" = "WCOM_DT_DESC"
register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.speed" = "I2C_SPEED_FAST_PLUS"
register "hid_desc_reg_offset" = "0x1"
device i2c 0a on end
end