the following patch was just integrated into master:
commit 18792314d7b8dde596a9c378b2d47516cbd871f4
Author: Robbie Zhang <robbie.zhang(a)intel.com>
Date: Mon Feb 13 13:44:14 2017 -0800
arch/x86: add functions to generate random numbers
Using x86 RDRAND instruction, two functions are supplied to
generate a 32bit or 64bit number.
One potential usage is the sealing key generation for SGX.
BUG=chrome-os-partner:62438
BRANCH=NONE
TEST=Tested on Eve to generate a 64bit random number.
Change-Id: I50cbeda4de17ccf2fc5efc1fe04f6b1a31ec268c
Signed-off-by: Robbie Zhang <robbie.zhang(a)intel.com>
Reviewed-on: https://review.coreboot.org/18362
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18362 for details.
-gerrit
the following patch was just integrated into master:
commit f296ce91b90ba845b1ff5ca35e98e52e884694cf
Author: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
Date: Tue Feb 14 22:16:58 2017 +0800
soc/intel/skylake: Expand USB OC pins definition to support PCH-H
Currently the USB OC pins definition only being defined up to OC3.
For PCH-H, OC4 and OC5 are needed, so add both into OC pin enum.
Changes is being verified and booted to Yocto with Saddle Brook.
Change-Id: Idaed6fa7dcddb9c688966e8bc59f656aec2b26eb
Signed-off-by: Teo Boon Tiong <boon.tiong.teo(a)intel.com>
Reviewed-on: https://review.coreboot.org/18364
Tested-by: build bot (Jenkins)
Reviewed-by: Aaron Durbin <adurbin(a)chromium.org>
See https://review.coreboot.org/18364 for details.
-gerrit
the following patch was just integrated into master:
commit c97e042a9bda9994409869369e1cbda551dc65cf
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Feb 16 11:36:16 2017 -0600
lynxpoint/broadwell: fix PCH power optimizer
Setting both bits 27 and 7 of PCH register PMSYNC_CFG (PMSYNC
Configuration; offset 0x33c8) causes pre-OS display init to fail
on HSW-U/Lynxpoint and BDW-U ChromeOS devices when the VBIOS/GOP
driver is run after the register is set. A re-examination of
Intel's reference code reveals that bit 7 should be set for the
LP PCH, and bit 27 for non-LP, but not both simultaneously.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 27 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/18385
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
Reviewed-by: Duncan Laurie <dlaurie(a)chromium.org>
See https://review.coreboot.org/18385 for details.
-gerrit
the following patch was just integrated into master:
commit ee6a612eb2edb32a55ee92c6fdfcdc474c6b21f1
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Feb 16 11:45:19 2017 -0600
Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.
Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/18384
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18384 for details.
-gerrit
the following patch was just integrated into master:
commit efd9dee646629948a54f68eca21b6ee922c55e10
Author: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Date: Thu Aug 14 11:58:04 2014 +0200
board-status: Add README
It explains the prerequisites to run the script, some
background on how to setup the computer running the script,
and the board it gathers the information from.
That information is too long to fit inside the script's
help.
Change-Id: Iecba7310ff1583149c02728e955716775bcbbdc4
Signed-off-by: Denis 'GNUtoo' Carikli <GNUtoo(a)no-log.org>
Reviewed-on: https://review.coreboot.org/6660
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/6660 for details.
-gerrit
the following patch was just integrated into master:
commit 4b8252ed76ef516678746dc4e10dca262d9ae55c
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Tue Feb 14 23:00:57 2017 -0600
google/slippy: consolidate variants' common mainboard.asl code
Move code common code from each variant's mainboard.asl into
common ACPI code for all variants (like google/auron). This also
adds the _PRW method for the LID0 device for falco and peppy, which
omitted the function when they were originally upstreamed.
See Chromium commit c8b41f7, falco: Add _PRW for LID0 ACPI Device
Change-Id: I7f5129340249a986f5996af37c01ccbde8d374e8
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
Reviewed-on: https://review.coreboot.org/18368
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth(a)google.com>
See https://review.coreboot.org/18368 for details.
-gerrit
the following patch was just integrated into master:
commit 75da1fb2baca8ce5c54d4a1ad4eb9f411844cbaa
Author: Elyes HAOUAS <ehaouas(a)noos.fr>
Date: Thu Feb 16 18:59:13 2017 +0100
nb/i945/raminit: sdram_set_channel_mode Test if DIMM slot 3 is populated
Add a test in case we have a DIMM2 not populated but DIMM3 is.
Change-Id: I14f82afe03884740570838e7b2771233356c518d
Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr>
Reviewed-on: https://review.coreboot.org/18386
Tested-by: build bot (Jenkins)
Reviewed-by: Nico Huber <nico.h(a)gmx.de>
See https://review.coreboot.org/18386 for details.
-gerrit
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18397
-gerrit
commit 6d5f2ef92bb5f54e802fb618c891f19e36b6f7bc
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:27:51 2017 -0800
google/eve: Set touchscreen I2C bus speed to 1MHz
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 9d46915..e5744e3 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -210,6 +210,7 @@ chip soc/intel/skylake
register "generic.cid" = "PNP0C50_CID"
register "generic.desc" = "WCOM_DT_DESC"
register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.speed" = "I2C_SPEED_FAST_PLUS"
register "hid_desc_reg_offset" = "0x1"
device i2c 0a on end
end
the following patch was just integrated into master:
commit f797a1ac6a72a571ba76bff8b7c451cc090778a9
Author: Martin Roth <martinroth(a)google.com>
Date: Thu Jan 26 15:37:10 2017 -0700
riscv: Suppress invalid coverity errors
Coverity is detecting 'sp' as a variable which has not been initialized.
This is obviously not correct, so this patch *TRIES* to mark it as false
I'm not positive that this will work because the annotation needs to go
on the line above the error, but this error is inside of a # define.
Does the whole #define count as one line? Can it go on the line
above the #define in the .h file? Does it have to precede every line
where the #define is used? The documentation doesn't make this clear.
Should suppress coverity issues: 1368525 & 1368527
uninit_use: Using uninitialized value sp.
Change-Id: Ibae5e206c4ff47991ea8a11b6b59972b24b71796
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/18247
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
See https://review.coreboot.org/18247 for details.
-gerrit