the following patch was just integrated into master:
commit 98641b92e7840f42cef36a3a44b3118d25c5b2f7
Author: Martin Roth <martinroth(a)google.com>
Date: Wed Feb 15 10:09:03 2017 -0700
src/drivers/pc80: Update vga_font_8x16.c to be non-binary
Previously, the file -i command identified vga_font_8x16.c as
application/octet-stream; charset=binary
Now it identifies as:
text/x-c; charset=us-ascii
- Remove non-ascii characters
Change-Id: I6b513e6457a31828a6e94c954a7e2e7ee18fd4d6
Signed-off-by: Martin Roth <martinroth(a)google.com>
Reviewed-on: https://review.coreboot.org/18372
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer(a)gmx.net>
See https://review.coreboot.org/18372 for details.
-gerrit
Duncan Laurie (dlaurie(a)chromium.org) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18397
-gerrit
commit 9bcf59913b4920fd1ad4c121df29550fc8cdb3b3
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:27:51 2017 -0800
google/eve: Set touchscreen I2C bus speed to 1MHz
Enable Fast-Plus speed for the touchscreen device so it can
be used at 1MHz instead of 400KHz.
BUG=chrome-os-partner:61277
TEST=manual testing on Eve P1, needs backported kernel patches
to actually make use of any I2C speed other than 400KHz
Change-Id: I3f44ff4a02a02a7b05e69ad54d4c6d60e5878393
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
src/mainboard/google/eve/devicetree.cb | 1 +
1 file changed, 1 insertion(+)
diff --git a/src/mainboard/google/eve/devicetree.cb b/src/mainboard/google/eve/devicetree.cb
index 9d46915..e5744e3 100644
--- a/src/mainboard/google/eve/devicetree.cb
+++ b/src/mainboard/google/eve/devicetree.cb
@@ -210,6 +210,7 @@ chip soc/intel/skylake
register "generic.cid" = "PNP0C50_CID"
register "generic.desc" = "WCOM_DT_DESC"
register "generic.irq" = "IRQ_LEVEL_LOW(GPP_E7_IRQ)"
+ register "generic.speed" = "I2C_SPEED_FAST_PLUS"
register "hid_desc_reg_offset" = "0x1"
device i2c 0a on end
end
the following patch was just integrated into master:
commit c86fa6d97584ce941d847c1eabf388a226ba2638
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:26:04 2017 -0800
google/eve: Set rise/fall timing values for I2C bus 1
Apply the measured rise and fall times for I2C bus 1 on Eve
so it can be tuned properly for 400KHz operation.
BUG=chrome-os-partner:63020
TEST=verify I2C1 bus speed with a scope
Change-Id: I32b5aa460ea35aadca7f3d52324a64880764919f
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18396
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18396 for details.
-gerrit
the following patch was just integrated into master:
commit 6c8238521eaf2216c9a41502be1cb2703a0d6f3e
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:24:12 2017 -0800
google/eve: Fix FPC support
Currently UART0 GPIOs are being put into native mode during FSP-S
stage, so have ramstage re-configure them back to regular GPIO mode.
GPP_C8 does not seem to be functioning properly when routed to the
APIC, possibly due to the UART0 being enabled even though it is unused,
which is required because UART0 is PCI 1e.0 and so must be present for
other 1e.x functions to be enumerated. Instead, use this pin as a GPIO
interrupt so it will be routed through the GPIO controller at IRQ 14.
GPP_C9 was inverted and was only working because the pin was being
re-configured in FSP-S.
Also export the reset gpio as a device property so it can be used by
the kernel driver, which will stop it from complaining at boot.
BUG=chrome-os-partner:61233
TEST=verify that the interrupt and device is functional in the OS
Change-Id: Iaf9efbf50a13a981c6a9bbd507475777837e9c12
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18395
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18395 for details.
-gerrit
Tobias Diedrich (ranma+coreboot(a)tdiedrich.de) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/12796
-gerrit
commit 2f2c221c24d2dd198bd31ea848ada4c2701604ef
Author: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
Date: Wed Dec 23 23:27:06 2015 +0100
pcengines/apu1: Support TPM modules on the LPC connector
Since the APU1 has an LPC connector it is possible to
connect a TPM. I'm using mine mostly for the HWRNG which the
APU1 lacks.
This takes care of setting up the TPM interrupt.
Interrupt 5 was chosen since it is not otherwise used on the APU1,
Alternatively 1, 7, 10-11 and 14-15 should be available as well.
It may also be possible to share the ACPI interrupt (9).
Previously I was getting frequent
"genirq: Flags mismatch irq 4. 00000000 (serial) vs. 00000080 (tpm0)"
errors.
With this I also no longer need to use "tpm_tis.force=1" on
the kernel commandline since the TPM is now declared in the
ACPI DSDT.
See also https://plus.google.com/+TobiasDiedrich/posts/cRv9MwrCdEa
and https://plus.google.com/+TobiasDiedrich/posts/BDnJLGFMW8o
Change-Id: Ie732228471f6c40d77e17cbed34726961b1fcddd
Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>
---
src/mainboard/pcengines/apu1/Kconfig | 1 +
src/mainboard/pcengines/apu1/devicetree.cb | 5 +++++
2 files changed, 6 insertions(+)
diff --git a/src/mainboard/pcengines/apu1/Kconfig b/src/mainboard/pcengines/apu1/Kconfig
index 5e927cc..7693627 100644
--- a/src/mainboard/pcengines/apu1/Kconfig
+++ b/src/mainboard/pcengines/apu1/Kconfig
@@ -29,6 +29,7 @@ config BOARD_SPECIFIC_OPTIONS # dummy
select HAVE_OPTION_TABLE
select HAVE_CMOS_DEFAULT
select BOARD_ROMSIZE_KB_2048
+ select MAINBOARD_HAS_LPC_TPM
config MAINBOARD_DIR
string
diff --git a/src/mainboard/pcengines/apu1/devicetree.cb b/src/mainboard/pcengines/apu1/devicetree.cb
index 72e89c0..097b921 100644
--- a/src/mainboard/pcengines/apu1/devicetree.cb
+++ b/src/mainboard/pcengines/apu1/devicetree.cb
@@ -43,6 +43,11 @@ chip northbridge/amd/agesa/family14/root_complex
device pci 14.1 off end # IDE 0x439c
device pci 14.2 off end # HDA 0x4383
device pci 14.3 on # LPC 0x439d
+ chip drivers/pc80/tpm # Optional TPM on the LPC header.
+ device pnp 0c31.0 on
+ irq 0x70 = 5
+ end
+ end
chip superio/nuvoton/nct5104d
register "irq_trigger_type" = "0"
device pnp 2e.0 off end
the following patch was just integrated into master:
commit 25c7d9342b8bdee61710a516440e4b9c4b83fb09
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:16:43 2017 -0800
soc/intel/skylake: Disable s0ix if not enabled in devicetree
There is an enable_s0ix config option in the devicetree that should
be used to disable it when not set:
- do not export C8/C9/C10 C-states in _CST
- do not enable SLP_S0 in FSP
BUG=chrome-os-partner:58666
TEST=test on eve board to ensure that OS only sees 3 ACPI C-states
instead of 6 and that it no longer attempts to enter C10
Change-Id: I90e4dc776d1d17d0b700cda63c8476786cd2e4ff
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18394
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18394 for details.
-gerrit
the following patch was just integrated into master:
commit c9db384ea47b8b705ddeaf0319fd53b5c513f423
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:14:35 2017 -0800
drivers/spi/acpi: Add additional generic ACPI support
Add support for more ACPI features in the generic SPI ACPI
driver so it can be flexible enough to support more devices,
or devices in different configurations.
- add a wake pin
- add support for using IRQ GPIO instead of PIRQ
- add power resource support with enable and reset gpios
BUG=chrome-os-partner:61233
TEST=ensure existing SSDT generation is unchanged,
and test that new features generate expected code
Change-Id: Ibe37cc87e488004baa2c08a369f73c86e6cd6dce
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18393
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18393 for details.
-gerrit
the following patch was just integrated into master:
commit 4f31d5c2ced908a1d18b14670149c8f2e12fe804
Author: Duncan Laurie <dlaurie(a)chromium.org>
Date: Fri Feb 17 17:07:23 2017 -0800
acpi_device: Add macros for GPIO interrupts
Add individual macros for the various interrupt types so
they can be used in devicetree.
BUG=chrome-os-partner:58666
TEST=nothing uses this yet, will be used in an upcoming commit
Change-Id: I2a569f60fcc0815835615656b09670987036b848
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
Reviewed-on: https://review.coreboot.org/18392
Tested-by: build bot (Jenkins)
Reviewed-by: Furquan Shaikh <furquan(a)google.com>
See https://review.coreboot.org/18392 for details.
-gerrit