Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18385
-gerrit
commit 81f9f477cb9ef38712b41d7c214ccd320c66675e
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Feb 16 11:36:16 2017 -0600
lynxpoint/broadwell: fix PCH power optimizer
Setting bit 7 of PCH register PMSYNC_CFG (PMSYNC Configuration;
offset 0x33c8) causes pre-OS display init to fail on HSW-U/Lynxpoint
and BDW-U ChromeOS devices when the VBIOS/GOP driver is run after the
register is set. As this bit falls into the reserved/undocumented
range, there is no way of telling its function, but unsetting it
appears to have no ill effect.
The previous workaround was to disable the entire power optimizer
section via a Kconfig option, which isn't ideal.
Test: unset bit 7 of PMSYNC_CFG and boot google/lulu,
observe functional pre-OS video output
Change-Id: I446e169d23dd446710a1648f0a9b9599568b80aa
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/soc/intel/broadwell/lpc.c | 2 +-
src/southbridge/intel/lynxpoint/lpc.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index c1600c5..b9a7567 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -262,7 +262,7 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
/* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
- REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
+ REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000000),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b10, 0x0000883c),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b14, 0x1e0a4616),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x2b24, 0x40000005),
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index 04cb0bd..148425b 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -347,7 +347,7 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
- RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
+ RCBA_RMW_REG_32(0x33c8, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b14, 0, 0x1e0a4616), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
Matt DeVillier (matt.devillier(a)gmail.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18384
-gerrit
commit 7bb3dbb39b3c8a809b9f85400b1f95c405cf5e47
Author: Matt DeVillier <matt.devillier(a)gmail.com>
Date: Thu Feb 16 11:45:19 2017 -0600
Revert "intel/lynxpoint,broadwell: Fix eDP display in Windows, SeaBios & Tiano"
We've been able to narrow down the problem to a single register/
single bit, so revert this commit and address the problem in a
follow-on commit.
This reverts commit 0f2025da0fd4dce6b951b4c4b97c9370ca7d66db.
Change-Id: I780f9ea2976dd223aaa3e060aef6e1af8012c346
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
src/soc/intel/broadwell/Kconfig | 9 ---------
src/soc/intel/broadwell/lpc.c | 2 --
src/southbridge/intel/lynxpoint/Kconfig | 9 ---------
src/southbridge/intel/lynxpoint/lpc.c | 2 --
4 files changed, 22 deletions(-)
diff --git a/src/soc/intel/broadwell/Kconfig b/src/soc/intel/broadwell/Kconfig
index 01bcaf1..0cbd9e4 100644
--- a/src/soc/intel/broadwell/Kconfig
+++ b/src/soc/intel/broadwell/Kconfig
@@ -208,13 +208,4 @@ config CHIPSET_BOOTBLOCK_INCLUDE
string
default "soc/intel/broadwell/bootblock/timestamp.inc"
-config BROADWELL_POWER_OPTIMIZER
- bool "Enable Power Optimizer"
- default y if CHROMEOS
- help
- Enable the power optimizer for the High Speed I/O
- Power Control (HSIOPC). This can break graphics
- under Windows, but can improve battery life under
- 'mostly idle' conditions.
-
endif
diff --git a/src/soc/intel/broadwell/lpc.c b/src/soc/intel/broadwell/lpc.c
index e4db498..c1600c5 100644
--- a/src/soc/intel/broadwell/lpc.c
+++ b/src/soc/intel/broadwell/lpc.c
@@ -260,7 +260,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x33b4, 0x00007001),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3350, 0x022ddfff),
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3354, 0x00000001),
-#if IS_ENABLED(CONFIG_BROADWELL_POWER_OPTIMIZER)
/* Power Optimizer */
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x08000000),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x08000080),
@@ -272,7 +271,6 @@ static const struct reg_script pch_pm_init_script[] = {
REG_MMIO_WRITE32(RCBA_BASE_ADDRESS + 0x3a84, 0x00001005),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33d4, 0x2fff2fb1),
REG_MMIO_OR32(RCBA_BASE_ADDRESS + 0x33c8, 0x00008000),
-#endif
REG_SCRIPT_END
};
diff --git a/src/southbridge/intel/lynxpoint/Kconfig b/src/southbridge/intel/lynxpoint/Kconfig
index 31a7db3..742f95c 100644
--- a/src/southbridge/intel/lynxpoint/Kconfig
+++ b/src/southbridge/intel/lynxpoint/Kconfig
@@ -97,13 +97,4 @@ config LOCK_MANAGEMENT_ENGINE
bool
default n
-config LYNXPOINT_POWER_OPTIMIZER
- bool "Enable Power Optimizer"
- default y if CHROMEOS
- help
- Enable the power optimizer for the High Speed I/O
- Power Control (HSIOPC). This can break graphics
- under Windows, but can improve battery life under
- 'mostly idle' conditions.
-
endif
diff --git a/src/southbridge/intel/lynxpoint/lpc.c b/src/southbridge/intel/lynxpoint/lpc.c
index a399eb3..04cb0bd 100644
--- a/src/southbridge/intel/lynxpoint/lpc.c
+++ b/src/southbridge/intel/lynxpoint/lpc.c
@@ -346,7 +346,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x33b4, 0, 0x00007001),
RCBA_RMW_REG_32(0x3350, 0, 0x022ddfff),
RCBA_RMW_REG_32(0x3354, 0, 0x00000001),
-#if IS_ENABLED(CONFIG_LYNXPOINT_POWER_OPTIMIZER)
RCBA_RMW_REG_32(0x33d4, ~0, 0x08000000), /* Power Optimizer */
RCBA_RMW_REG_32(0x33c8, ~0, 0x08000080), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b10, 0, 0x0000883c), /* Power Optimizer */
@@ -354,7 +353,6 @@ const struct rcba_config_instruction lpt_lp_pm_rcba[] = {
RCBA_RMW_REG_32(0x2b24, 0, 0x40000005), /* Power Optimizer */
RCBA_RMW_REG_32(0x2b20, 0, 0x0005db01), /* Power Optimizer */
RCBA_RMW_REG_32(0x3a80, 0, 0x05145005),
-#endif
RCBA_END_CONFIG
};
Mario Scheithauer (mario.scheithauer(a)siemens.com) just uploaded a new patch set to gerrit, which you can find at https://review.coreboot.org/18380
-gerrit
commit f9c2d7f774b554bf62109c484b010126c7ea45e7
Author: Mario Scheithauer <mario.scheithauer(a)siemens.com>
Date: Thu Feb 16 13:39:16 2017 +0100
siemens/mc_apl1: Set MAC address for all available i210 MACs
This mainboard uses two i210 Ethernet controller. Therfore we enable the
usage of the i210 driver and have to provide a function to search for a
valid MAC address for all i210 devices by using Siemens hwilib.
Change-Id: I36246cdef987fcece15a297ebb2f41561fca1f69
Signed-off-by: Mario Scheithauer <mario.scheithauer(a)siemens.com>
---
src/mainboard/siemens/mc_apl1/Kconfig | 2 +
src/mainboard/siemens/mc_apl1/mainboard.c | 81 +++++++++++++++++++++++++++++++
2 files changed, 83 insertions(+)
diff --git a/src/mainboard/siemens/mc_apl1/Kconfig b/src/mainboard/siemens/mc_apl1/Kconfig
index 6201ed3..ef9d021 100644
--- a/src/mainboard/siemens/mc_apl1/Kconfig
+++ b/src/mainboard/siemens/mc_apl1/Kconfig
@@ -5,6 +5,8 @@ config BOARD_SPECIFIC_OPTIONS
select SOC_INTEL_APOLLOLAKE
select BOARD_ROMSIZE_KB_16384
select HAVE_ACPI_TABLES
+ select DRIVER_INTEL_I210
+ select USE_SIEMENS_HWILIB
config MAINBOARD_DIR
string
diff --git a/src/mainboard/siemens/mc_apl1/mainboard.c b/src/mainboard/siemens/mc_apl1/mainboard.c
index f7a2ef1..9517d11 100644
--- a/src/mainboard/siemens/mc_apl1/mainboard.c
+++ b/src/mainboard/siemens/mc_apl1/mainboard.c
@@ -2,6 +2,7 @@
* This file is part of the coreboot project.
*
* Copyright 2016 Google Inc.
+ * Copyright (C) 2017 Siemens AG
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
@@ -14,6 +15,86 @@
*/
#include <device/device.h>
+#include <console/console.h>
+#include <string.h>
+#include <hwilib.h>
+#include <i210.h>
+
+#define MAX_PATH_DEPTH 12
+#define MAX_NUM_MAPPINGS 10
+
+/** \brief This function can decide if a given MAC address is valid or not.
+ * Currently, addresses filled with 0xff or 0x00 are not valid.
+ * @param mac Buffer to the MAC address to check
+ * @return 0 if address is not valid, otherwise 1
+ */
+static uint8_t is_mac_adr_valid(uint8_t mac[6])
+{
+ uint8_t buf[6];
+
+ memset(buf, 0, sizeof(buf));
+ if (!memcmp(buf, mac, sizeof(buf)))
+ return 0;
+ memset(buf, 0xff, sizeof(buf));
+ if (!memcmp(buf, mac, sizeof(buf)))
+ return 0;
+ return 1;
+}
+
+/** \brief This function will search for a MAC address which can be assigned
+ * to a MACPHY.
+ * @param dev pointer to PCI device
+ * @param mac buffer where to store the MAC address
+ * @return cb_err CB_ERR or CB_SUCCESS
+ */
+enum cb_err mainboard_get_mac_address(struct device *dev, uint8_t mac[6])
+{
+ struct bus *parent = dev->bus;
+ uint8_t buf[16], mapping[16], i = 0, chain_len = 0;
+
+ memset(buf, 0, sizeof(buf));
+ memset(mapping, 0, sizeof(mapping));
+
+ /* The first entry in the tree is the device itself. */
+ buf[0] = dev->path.pci.devfn;
+ chain_len = 1;
+ for (i = 1; i < MAX_PATH_DEPTH && parent->dev->bus->subordinate; i++) {
+ buf[i] = parent->dev->path.pci.devfn;
+ chain_len++;
+ parent = parent->dev->bus;
+ }
+ if (i == MAX_PATH_DEPTH) {
+ /* The path is deeper than MAX_PATH_DEPTH devices, error. */
+ printk(BIOS_ERR, "Too many bridges for %s\n", dev_path(dev));
+ return CB_ERR;
+ }
+ /* Now construct the mapping based on the device chain starting from */
+ /* root bridge device to the device itself. */
+ mapping[0] = 1;
+ mapping[1] = chain_len;
+ for (i = 0; i < chain_len; i++)
+ mapping[i + 4] = buf[chain_len - i - 1];
+
+ /* Open main hwinfo block */
+ if (hwilib_find_blocks("hwinfo.hex") != CB_SUCCESS)
+ return CB_ERR;
+ /* Now try to find a valid MAC address in hwinfo for this mapping.*/
+ for (i = 0; i < MAX_NUM_MAPPINGS; i++) {
+ if ((hwilib_get_field(XMac1Mapping + i, buf, 16) == 16) &&
+ !(memcmp(buf, mapping, chain_len + 4))) {
+ /* There is a matching mapping available, get MAC address. */
+ if ((hwilib_get_field(XMac1 + i, mac, 6) == 6) &&
+ (is_mac_adr_valid(mac))) {
+ return CB_SUCCESS;
+ } else {
+ return CB_ERR;
+ }
+ } else
+ continue;
+ }
+ /* No MAC address found for */
+ return CB_ERR;
+}
static void mainboard_init(void *chip_info)
{