Duncan Laurie has uploaded a new patch set (#2). ( https://review.coreboot.org/22854 )
Change subject: drivers/pc80/tpm: Remove unused ACPI opregion
......................................................................
drivers/pc80/tpm: Remove unused ACPI opregion
The opregion and fields are left over from when ACPI ASL code was
reading registers to determine the current setup. Now that the
ACPI device is generated with the correct information already this
code is not used at all and can be removed from the tree.
Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
M src/drivers/pc80/tpm/tpm.c
1 file changed, 0 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22854/2
--
To view, visit https://review.coreboot.org/22854
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newpatchset
Gerrit-Change-Id: If89d90cc7105ed21e2134ac99224f6f8214cc8ad
Gerrit-Change-Number: 22854
Gerrit-PatchSet: 2
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/22855
Change subject: drivers/spi: Enable flashconsole in verstage
......................................................................
drivers/spi: Enable flashconsole in verstage
Enable the flashconsole driver in verstage so it can be used
with VBOOT enabled. This was tested on a VBOOT enabled system
using flashconsole to store the boot log.
Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
M src/drivers/spi/Makefile.inc
1 file changed, 1 insertion(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/22855/1
diff --git a/src/drivers/spi/Makefile.inc b/src/drivers/spi/Makefile.inc
index f8cff5a..3f68541 100644
--- a/src/drivers/spi/Makefile.inc
+++ b/src/drivers/spi/Makefile.inc
@@ -9,6 +9,7 @@
ifeq ($(CONFIG_CONSOLE_SPI_FLASH),y)
bootblock-y += flashconsole.c
+verstage-y += flashconsole.c
romstage-y += flashconsole.c
ramstage-y += flashconsole.c
postcar-y += flashconsole.c
--
To view, visit https://review.coreboot.org/22855
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Icd8a82dc962ece85b9fb3d2f5654369e821922eb
Gerrit-Change-Number: 22855
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>
Duncan Laurie has uploaded this change for review. ( https://review.coreboot.org/22856
Change subject: soc/intel/skylake: Add integrated LAN config parameters
......................................................................
soc/intel/skylake: Add integrated LAN config parameters
Add parameters to configure the integrated LAN via FSP. Since
this takes over a PCI CLKREQ# pin it needs to know which pin
it should use, and there are additional parameters for LTR and
a "K1 power save" feature.
This was tested on a KBL-R board with integrated LAN, verifying
that the device is functional under Linux with the e1000e driver.
Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Signed-off-by: Duncan Laurie <dlaurie(a)chromium.org>
---
M src/soc/intel/skylake/chip.h
M src/soc/intel/skylake/chip_fsp20.c
2 files changed, 10 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22856/1
diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h
index a7804af..8540e21 100644
--- a/src/soc/intel/skylake/chip.h
+++ b/src/soc/intel/skylake/chip.h
@@ -135,6 +135,10 @@
/* Lan */
u8 EnableLan;
+ u8 EnableLanLtr;
+ u8 EnableLanK1Off;
+ u8 LanClkReqSupported;
+ u8 LanClkReqNumber;
/* SATA related */
u8 EnableSata;
diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c
index 2df013f..96c3b60 100644
--- a/src/soc/intel/skylake/chip_fsp20.c
+++ b/src/soc/intel/skylake/chip_fsp20.c
@@ -186,6 +186,12 @@
params->PchPmLanWakeFromDeepSx = config->WakeConfigPcieWakeFromDeepSx;
params->PchLanEnable = config->EnableLan;
+ if (config->EnableLan) {
+ params->PchLanLtrEnable = config->EnableLanLtr;
+ params->PchLanK1OffEnable = config->EnableLanK1Off;
+ params->PchLanClkReqSupported = config->LanClkReqSupported;
+ params->PchLanClkReqNumber = config->LanClkReqNumber;
+ }
params->SataSalpSupport = config->SataSalpSupport;
params->SsicPortEnable = config->SsicPortEnable;
params->ScsEmmcEnabled = config->ScsEmmcEnabled;
--
To view, visit https://review.coreboot.org/22856
To unsubscribe, visit https://review.coreboot.org/settings
Gerrit-Project: coreboot
Gerrit-Branch: master
Gerrit-MessageType: newchange
Gerrit-Change-Id: Idb200cec90a3c0d4d9c914bae9983a3bcdafcd06
Gerrit-Change-Number: 22856
Gerrit-PatchSet: 1
Gerrit-Owner: Duncan Laurie <dlaurie(a)chromium.org>