coreboot-gerrit December 2017

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Change in coreboot[master]: mb/google/poppy: Enable speaker and codec for nami
by Gaggery Tsai (Code Review) 14 Dec '17

14 Dec '17

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/22861 Change subject: mb/google/poppy: Enable speaker and codec for nami ...................................................................... mb/google/poppy: Enable speaker and codec for nami Nami uses MAX98357A speaker amplifier and DA7219 codec. This patch adds max98357a and da7219 under I2C #3 in devicetree and add SPK DMIC nhlt support for 4CH DMIC. Besides, according to schematic, revise speaker enabling from A22 to A23 pin. Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/variants/nami/Makefile.inc M src/mainboard/google/poppy/variants/nami/devicetree.cb M src/mainboard/google/poppy/variants/nami/gpio.c A src/mainboard/google/poppy/variants/nami/nhlt.c 5 files changed, 72 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/22861/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 72103af..9315d96 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -55,6 +55,12 @@ select NHLT_DMIC_4CH select NHLT_MAX98357 +config INCLUDE_NHLT_BLOBS_NAMI + bool "Include blobs for nami audio." + select NHLT_DA7219 + select NHLT_DMIC_4CH + select NHLT_MAX98357 + config MAINBOARD_DIR string default "google/poppy" @@ -118,6 +124,8 @@ config VARIANT_SPECIFIC_OPTIONS_NAMI def_bool n + select DRIVERS_GENERIC_MAX98357A + select DRIVERS_I2C_DA7219 select DRIVERS_PS2_KEYBOARD select DRIVERS_SPI_ACPI select EXCLUDE_NATIVE_SD_INTERFACE diff --git a/src/mainboard/google/poppy/variants/nami/Makefile.inc b/src/mainboard/google/poppy/variants/nami/Makefile.inc index 06f9801..818418d 100644 --- a/src/mainboard/google/poppy/variants/nami/Makefile.inc +++ b/src/mainboard/google/poppy/variants/nami/Makefile.inc @@ -9,3 +9,4 @@ ramstage-y += gpio.c ramstage-y += pl2.c +ramstage-y += nhlt.c diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 401e137..d84e00d 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -246,7 +246,30 @@ device pci 15.0 on end # I2C #0 device pci 15.1 on end # I2C #1 device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 on + chip drivers/generic/max98357a + register "sdmode_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A23)" + register "sdmode_delay" = "5" + device generic 0 on end + end + chip drivers/i2c/da7219 + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_D9_IRQ)" + register "btn_cfg" = "50" + register "mic_det_thr" = "500" + register "jack_ins_deb" = "20" + register "jack_det_rate" = ""32ms_64ms"" + register "jack_rem_deb" = "1" + register "a_d_btn_thr" = "0xa" + register "d_b_btn_thr" = "0x16" + register "b_c_btn_thr" = "0x21" + register "c_mic_btn_thr" = "0x3e" + register "btn_avg" = "4" + register "adc_1bit_rpt" = "1" + register "micbias_lvl" = "2600" + register "mic_amp_in_sel" = ""diff"" + device i2c 1A on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/poppy/variants/nami/gpio.c b/src/mainboard/google/poppy/variants/nami/gpio.c index 81fb129..e9e46c3 100644 --- a/src/mainboard/google/poppy/variants/nami/gpio.c +++ b/src/mainboard/google/poppy/variants/nami/gpio.c @@ -57,10 +57,10 @@ PAD_CFG_NC(GPP_A20), /* A21 : ISH_GP3 ==> NC */ PAD_CFG_NC(GPP_A21), - /* A22 : ISH_GP4 ==> PCH_SPK_EN */ - PAD_CFG_GPO(GPP_A22, 1, DEEP), - /* A23 : ISH_GP5 ==> NC */ - PAD_CFG_NC(GPP_A23), + /* A22 : ISH_GP4 ==> NC */ + PAD_CFG_NC(GPP_A22), + /* A23 : ISH_GP5 ==> PCH_SPK_EN */ + PAD_CFG_GPO(GPP_A23, 1, DEEP), /* B0 : CORE_VID0 ==> NC(T3) */ PAD_CFG_NC(GPP_B0), diff --git a/src/mainboard/google/poppy/variants/nami/nhlt.c b/src/mainboard/google/poppy/variants/nami/nhlt.c new file mode 100644 index 0000000..690fed5 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nami/nhlt.c @@ -0,0 +1,35 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <baseboard/variants.h> +#include <console/console.h> +#include <nhlt.h> +#include <soc/nhlt.h> + +void variant_nhlt_init(struct nhlt *nhlt) +{ + /* 4 Channel DMIC array. */ + if (nhlt_soc_add_dmic_array(nhlt, 4)) + printk(BIOS_ERR, "Couldn't add 4CH DMIC array.\n"); + + /* Dialog DA7219 Headset codec. */ + if (nhlt_soc_add_da7219(nhlt, AUDIO_LINK_SSP1)) + printk(BIOS_ERR, "Couldn't add Dialog DA7219.\n"); + + /* MAXIM Smart Amps for left and right speakers. */ + if (nhlt_soc_add_max98357(nhlt, AUDIO_LINK_SSP0)) + printk(BIOS_ERR, "Couldn't add Maxim_98357 codec.\n"); + +} -- To view, visit https://review.coreboot.org/22861 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Iecf4059f8ea3d5e34f33f0be227897a8cca636fa Gerrit-Change-Number: 22861 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.corp-partner.google.com>

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Change in coreboot[master]: mainboard/google/kahlee: Update overcurrent pins
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22860 ) Change subject: mainboard/google/kahlee: Update overcurrent pins ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19292/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64497/ : SUCCESS -- To view, visit https://review.coreboot.org/22860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Gerrit-Change-Number: 22860 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Daniel Kurtz <djkurtz(a)google.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 03:25:19 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mainboard/google/kahlee: Update overcurrent pins
by Martin Roth (Code Review) 14 Dec '17

14 Dec '17

Martin Roth has uploaded this change for review. ( https://review.coreboot.org/22860 Change subject: mainboard/google/kahlee: Update overcurrent pins ...................................................................... mainboard/google/kahlee: Update overcurrent pins The overcurrent pins on kahlee weren't mapped correctly, causing the USB-A port to stop working. None of the EHCI only ports are used for external connectors, so all of the overcurrent pins should go to the XHCI connections. This is also true of the Grunt board. On Grunt, this also means that we don't need OC3, as it doesn't map to anything in the XHCI controller, as it's coming from an internal hub. BUG=b:70636233 TEST=Build & boot Kahlee, verify USB-A port is working again. Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Signed-off-by: Martin Roth <martinroth(a)google.com> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/kahlee/gpio.c 2 files changed, 8 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/60/22860/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index c2ec65f..250fcc1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -324,18 +324,15 @@ int __attribute__((weak)) variant_get_xhci_oc_map(uint16_t *map) { - *map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */ - *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */ - *map |= USB_OC_DISABLE << OC_PORT2_SHIFT; + *map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0/4 = OC0 */ + *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC1 */ + *map |= USB_OC2 << OC_PORT2_SHIFT; /* USB-A HUB Port2/6 = OC2 */ *map |= USB_OC_DISABLE << OC_PORT3_SHIFT; return 0; } int __attribute__((weak)) variant_get_ehci_oc_map(uint16_t *map) { - *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */ - *map |= USB_OC3 << OC_PORT1_SHIFT; /* USB-A Port1 = OC3 */ - *map |= USB_OC_DISABLE << OC_PORT2_SHIFT; - *map |= USB_OC_DISABLE << OC_PORT3_SHIFT; + *map = USB_OC_DISABLE_ALL; return 0; } diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 14424b7..e5e15e6 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -151,18 +151,15 @@ int variant_get_xhci_oc_map(uint16_t *map) { - *map = USB_OC0 << OC_PORT0_SHIFT; /* USB-C Port0 = OC0 */ - *map |= USB_OC1 << OC_PORT1_SHIFT; /* USB-C Port1 = OC1 */ - *map |= USB_OC_DISABLE << OC_PORT2_SHIFT; + *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0/4 = OC2 */ + *map |= USB_OC0 << OC_PORT1_SHIFT; /* USB-C Port1/5 = OC0 */ + *map |= USB_OC1 << OC_PORT2_SHIFT; /* USB-C Port2/6 = OC1 */ *map |= USB_OC_DISABLE << OC_PORT3_SHIFT; return 0; } int variant_get_ehci_oc_map(uint16_t *map) { - *map = USB_OC2 << OC_PORT0_SHIFT; /* USB-A Port0 = OC2 */ - *map |= USB_OC_DISABLE << OC_PORT1_SHIFT; - *map |= USB_OC_DISABLE << OC_PORT2_SHIFT; - *map |= USB_OC_DISABLE << OC_PORT3_SHIFT; + *map = USB_OC_DISABLE_ALL; return 0; } -- To view, visit https://review.coreboot.org/22860 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I53336a18a26bd9be27c7265fddbcd780632656bf Gerrit-Change-Number: 22860 Gerrit-PatchSet: 1 Gerrit-Owner: Martin Roth <martinroth(a)google.com>

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Change in coreboot[master]: mainboard/intel/saddlebrook: add support for Saddle Brook
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21436 ) Change subject: mainboard/intel/saddlebrook: add support for Saddle Brook ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19291/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64496/ : SUCCESS -- To view, visit https://review.coreboot.org/21436 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie221eb58e8ab8ff15e9ef19c1d145a5eb2921b4e Gerrit-Change-Number: 21436 Gerrit-PatchSet: 8 Gerrit-Owner: Anuj Mittal <anujx.mittal(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anuj Mittal <anujx.mittal(a)intel.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh(a)intel.com> Gerrit-Reviewer: Stefan Reinauer <stefan.reinauer(a)coreboot.org> Gerrit-Reviewer: Teo Boon Tiong <boon.tiong.teo(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 02:23:47 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: Snappy: add reset pin for Melfas touch controller
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22858 ) Change subject: Snappy: add reset pin for Melfas touch controller ...................................................................... Patch Set 3: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64495/ : SUCCESS -- To view, visit https://review.coreboot.org/22858 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icf0451ff0c3df97cb2474e30542a2f46ba67d82a Gerrit-Change-Number: 22858 Gerrit-PatchSet: 3 Gerrit-Owner: Kevin Chiu <Kevin.Chiu(a)quantatw.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Keith Tzeng <keith.tzeng(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 02:01:30 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Use generated ACPI PIRQ
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22859 ) Change subject: intel/bd82x6x: Use generated ACPI PIRQ ...................................................................... Patch Set 2: Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64494/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19290/ : SUCCESS -- To view, visit https://review.coreboot.org/22859 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Gerrit-Change-Number: 22859 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 00:24:27 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/common: Automatically generate ACPI PIRQ
by build bot (Jenkins) (Code Review) 14 Dec '17

14 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22810 ) Change subject: sb/intel/common: Automatically generate ACPI PIRQ ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19289/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64493/ : SUCCESS -- To view, visit https://review.coreboot.org/22810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Gerrit-Change-Number: 22810 Gerrit-PatchSet: 4 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 14 Dec 2017 00:20:00 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Use generated ACPI PIRQ
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22859 ) Change subject: intel/bd82x6x: Use generated ACPI PIRQ ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64492/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19288/ : SUCCESS -- To view, visit https://review.coreboot.org/22859 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Gerrit-Change-Number: 22859 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 23:58:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: sb/intel/common: Automatically generate ACPI PIRQ
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22810 ) Change subject: sb/intel/common: Automatically generate ACPI PIRQ ...................................................................... Patch Set 3: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64491/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19287/ : SUCCESS -- To view, visit https://review.coreboot.org/22810 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic6b8ce4a9db50211a9c26221ca10105c5a0829a0 Gerrit-Change-Number: 22810 Gerrit-PatchSet: 3 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 23:58:49 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/bd82x6x: Use generated ACPI PIRQ
by Tobias Diedrich (Code Review) 13 Dec '17

13 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22859 Change subject: intel/bd82x6x: Use generated ACPI PIRQ ...................................................................... intel/bd82x6x: Use generated ACPI PIRQ Enable https://review.coreboot.org/#/c/22810/ for BD82X6X. This generates the main ACPI _PRT table automatically based on the chipset registers. Tested on Intel NUC DCP847SKE with Linux 4.13.14: $ cat /proc/interrupts CPU0 CPU1 0: 23 0 IO-APIC 2-edge timer 8: 1 0 IO-APIC 8-edge rtc0 9: 0 0 IO-APIC 9-fasteoi acpi 19: 86 0 IO-APIC 19-fasteoi ehci_hcd:usb1 23: 0 0 IO-APIC 23-fasteoi i801_smbus [...MSI and other interrupts skipped...] Log messages: ACPI_PIRQ_GEN PCI: 00:02.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1b.0: pin=1 pirq=1 ACPI_PIRQ_GEN PCI: 00:1c.0: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1c.1: pin=2 pirq=6 ACPI_PIRQ_GEN PCI: 00:1c.2: pin=3 pirq=4 ACPI_PIRQ_GEN PCI: 00:1d.0: pin=1 pirq=4 ACPI_PIRQ_GEN PCI: 00:1f.2: pin=1 pirq=2 ACPI_PIRQ_GEN PCI: 00:1f.3: pin=2 pirq=8 ACPI_PIRQ_GEN PCI: 00:04.0: pin=1 pirq=1 Generated _PRT: Scope (\_SB.PCI0) { Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table { If (PICM) { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001BFFFF, 0x00000000, 0x00000000, 0x00000010 }, Package (0x04) { 0x001CFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001CFFFF, 0x00000001, 0x00000000, 0x00000015 }, Package (0x04) { 0x001CFFFF, 0x00000002, 0x00000000, 0x00000013 }, Package (0x04) { 0x001DFFFF, 0x00000000, 0x00000000, 0x00000013 }, Package (0x04) { 0x001FFFFF, 0x00000000, 0x00000000, 0x00000011 }, Package (0x04) { 0x001FFFFF, 0x00000001, 0x00000000, 0x00000017 }, Package (0x04) { 0x0004FFFF, 0x00000000, 0x00000000, 0x00000010 } }) } Else { Return (Package (0x09) { Package (0x04) { 0x0002FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001BFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKF, 0x00000000 }, Package (0x04) { 0x001CFFFF, 0x00000002, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001DFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKD, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000000, \_SB.PCI0.LPCB.LNKB, 0x00000000 }, Package (0x04) { 0x001FFFFF, 0x00000001, \_SB.PCI0.LPCB.LNKH, 0x00000000 }, Package (0x04) { 0x0004FFFF, 0x00000000, \_SB.PCI0.LPCB.LNKA, 0x00000000 } }) } } } Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/apple/macbookair4_2/dsdt.asl M src/mainboard/asrock/b75pro3-m/dsdt.asl M src/mainboard/compulab/intense_pc/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl M src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl D src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl M src/mainboard/google/butterfly/dsdt.asl D src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl M src/mainboard/google/link/dsdt.asl D src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl M src/mainboard/google/parrot/dsdt.asl D src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl M src/mainboard/google/stout/dsdt.asl M src/mainboard/hp/2570p/dsdt.asl M src/mainboard/hp/2760p/dsdt.asl M src/mainboard/hp/8460p/dsdt.asl M src/mainboard/hp/8470p/dsdt.asl M src/mainboard/intel/emeraldlake2/dsdt.asl M src/mainboard/kontron/ktqm77/dsdt.asl M src/mainboard/lenovo/l520/dsdt.asl M src/mainboard/lenovo/s230u/dsdt.asl M src/mainboard/lenovo/t420/dsdt.asl M src/mainboard/lenovo/t420s/dsdt.asl M src/mainboard/lenovo/t430/dsdt.asl M src/mainboard/lenovo/t430s/dsdt.asl M src/mainboard/lenovo/t520/dsdt.asl M src/mainboard/lenovo/t530/dsdt.asl M src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl M src/mainboard/lenovo/x201/dsdt.asl M src/mainboard/lenovo/x220/dsdt.asl M src/mainboard/lenovo/x230/dsdt.asl M src/mainboard/packardbell/ms2290/dsdt.asl M src/mainboard/roda/rv11/dsdt.asl D src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl M src/mainboard/samsung/lumpy/dsdt.asl D src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl M src/mainboard/samsung/stumpy/dsdt.asl M src/mainboard/sapphire/pureplatinumh61/dsdt.asl M src/southbridge/intel/bd82x6x/Kconfig D src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl M src/southbridge/intel/bd82x6x/lpc.c 41 files changed, 3 insertions(+), 494 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/22859/1 diff --git a/src/mainboard/apple/macbookair4_2/dsdt.asl b/src/mainboard/apple/macbookair4_2/dsdt.asl index 924fb74..b8573c2 100644 --- a/src/mainboard/apple/macbookair4_2/dsdt.asl +++ b/src/mainboard/apple/macbookair4_2/dsdt.asl @@ -1,4 +1,3 @@ -/* * This file is part of the coreboot project. * * This program is free software; you can redistribute it and/or modify @@ -36,7 +35,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/asrock/b75pro3-m/dsdt.asl b/src/mainboard/asrock/b75pro3-m/dsdt.asl index 454ee3d..f01afa2 100644 --- a/src/mainboard/asrock/b75pro3-m/dsdt.asl +++ b/src/mainboard/asrock/b75pro3-m/dsdt.asl @@ -40,7 +40,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include "acpi/pci.asl" } } diff --git a/src/mainboard/compulab/intense_pc/dsdt.asl b/src/mainboard/compulab/intense_pc/dsdt.asl index 486ad43..a3fa256 100644 --- a/src/mainboard/compulab/intense_pc/dsdt.asl +++ b/src/mainboard/compulab/intense_pc/dsdt.asl @@ -40,7 +40,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl index 10faccd..a22fa5c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3h/dsdt.asl @@ -21,7 +21,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl index 10faccd..a22fa5c 100644 --- a/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl +++ b/src/mainboard/gigabyte/ga-b75m-d3v/dsdt.asl @@ -21,7 +21,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index b837442..0000000 --- a/src/mainboard/google/butterfly/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,60 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 },// GFX INTA -> PIRQA (MSI) - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 },// D27IP_ZIP HDA INTA -> PIRQA (MSI) - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 },// D28IP_P1IP WLAN INTA -> PIRQB - Package() { 0x001cffff, 1, 0, 21 },// D28IP_P2IP ETH0 INTB -> PIRQF - Package() { 0x001cffff, 2, 0, 19 },// D28IP_P3IP SDCARD INTC -> PIRQD - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 },// D29IP_E1P EHCI1 INTA -> PIRQD - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 },// D26IP_E2P EHCI2 INTA -> PIRQF - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, // D31IP_SIP SATA INTA -> PIRQB (MSI) - Package() { 0x001fffff, 1, 0, 23 }, // D31IP_SMIP SMBUS INTB -> PIRQH - Package() { 0x001fffff, 2, 0, 16 }, // D31IP_TTIP THRT INTC -> PIRQA - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/google/butterfly/dsdt.asl b/src/mainboard/google/butterfly/dsdt.asl index 3e13a41..c1ea0e6 100644 --- a/src/mainboard/google/butterfly/dsdt.asl +++ b/src/mainboard/google/butterfly/dsdt.asl @@ -44,7 +44,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6aebd13..0000000 --- a/src/mainboard/google/link/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 19 }, - Package() { 0x001cffff, 1, 0, 20 }, - Package() { 0x001cffff, 2, 0, 17 }, - Package() { 0x001cffff, 3, 0, 18 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, - Package() { 0x001fffff, 1, 0, 23 }, - Package() { 0x001fffff, 2, 0, 16 }, - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/mainboard/google/link/dsdt.asl b/src/mainboard/google/link/dsdt.asl index da4587d..82fb3f6 100644 --- a/src/mainboard/google/link/dsdt.asl +++ b/src/mainboard/google/link/dsdt.asl @@ -44,7 +44,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 6aebd13..0000000 --- a/src/mainboard/google/parrot/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 19 }, - Package() { 0x001cffff, 1, 0, 20 }, - Package() { 0x001cffff, 2, 0, 17 }, - Package() { 0x001cffff, 3, 0, 18 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, - Package() { 0x001fffff, 1, 0, 23 }, - Package() { 0x001fffff, 2, 0, 16 }, - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/mainboard/google/parrot/dsdt.asl b/src/mainboard/google/parrot/dsdt.asl index d179dea..4f2f986 100644 --- a/src/mainboard/google/parrot/dsdt.asl +++ b/src/mainboard/google/parrot/dsdt.asl @@ -43,7 +43,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl b/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 64ec07f..0000000 --- a/src/mainboard/google/stout/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,68 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, 0, 19 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 19 }, - Package() { 0x001cffff, 1, 0, 20 }, - Package() { 0x001cffff, 2, 0, 17 }, - Package() { 0x001cffff, 3, 0, 18 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 21 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 17 }, - Package() { 0x001fffff, 1, 0, 23 }, - Package() { 0x001fffff, 2, 0, 16 }, - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // XHCI 0:14.0 - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/mainboard/google/stout/dsdt.asl b/src/mainboard/google/stout/dsdt.asl index 3a822ed..b12c963 100644 --- a/src/mainboard/google/stout/dsdt.asl +++ b/src/mainboard/google/stout/dsdt.asl @@ -44,7 +44,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/hp/2570p/dsdt.asl b/src/mainboard/hp/2570p/dsdt.asl index d4fab7a..51934c7 100644 --- a/src/mainboard/hp/2570p/dsdt.asl +++ b/src/mainboard/hp/2570p/dsdt.asl @@ -39,7 +39,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/hp/2760p/dsdt.asl b/src/mainboard/hp/2760p/dsdt.asl index d4fab7a..51934c7 100644 --- a/src/mainboard/hp/2760p/dsdt.asl +++ b/src/mainboard/hp/2760p/dsdt.asl @@ -39,7 +39,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/hp/8460p/dsdt.asl b/src/mainboard/hp/8460p/dsdt.asl index d4fab7a..51934c7 100644 --- a/src/mainboard/hp/8460p/dsdt.asl +++ b/src/mainboard/hp/8460p/dsdt.asl @@ -39,7 +39,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/hp/8470p/dsdt.asl b/src/mainboard/hp/8470p/dsdt.asl index d4fab7a..51934c7 100644 --- a/src/mainboard/hp/8470p/dsdt.asl +++ b/src/mainboard/hp/8470p/dsdt.asl @@ -39,7 +39,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/intel/emeraldlake2/dsdt.asl b/src/mainboard/intel/emeraldlake2/dsdt.asl index a31c415..4adc457 100644 --- a/src/mainboard/intel/emeraldlake2/dsdt.asl +++ b/src/mainboard/intel/emeraldlake2/dsdt.asl @@ -43,7 +43,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/kontron/ktqm77/dsdt.asl b/src/mainboard/kontron/ktqm77/dsdt.asl index a5fd359..1b26ed0 100644 --- a/src/mainboard/kontron/ktqm77/dsdt.asl +++ b/src/mainboard/kontron/ktqm77/dsdt.asl @@ -44,7 +44,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/l520/dsdt.asl b/src/mainboard/lenovo/l520/dsdt.asl index 98afb23..5191c07 100644 --- a/src/mainboard/lenovo/l520/dsdt.asl +++ b/src/mainboard/lenovo/l520/dsdt.asl @@ -26,7 +26,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/lenovo/s230u/dsdt.asl b/src/mainboard/lenovo/s230u/dsdt.asl index 6cf26fd..19818a2 100644 --- a/src/mainboard/lenovo/s230u/dsdt.asl +++ b/src/mainboard/lenovo/s230u/dsdt.asl @@ -24,7 +24,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } } diff --git a/src/mainboard/lenovo/t420/dsdt.asl b/src/mainboard/lenovo/t420/dsdt.asl index 365fd0d..7db8344 100644 --- a/src/mainboard/lenovo/t420/dsdt.asl +++ b/src/mainboard/lenovo/t420/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/t420s/dsdt.asl b/src/mainboard/lenovo/t420s/dsdt.asl index f0c56c1..c549988 100644 --- a/src/mainboard/lenovo/t420s/dsdt.asl +++ b/src/mainboard/lenovo/t420s/dsdt.asl @@ -46,7 +46,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/t430/dsdt.asl b/src/mainboard/lenovo/t430/dsdt.asl index 638592d..dff8dcd 100644 --- a/src/mainboard/lenovo/t430/dsdt.asl +++ b/src/mainboard/lenovo/t430/dsdt.asl @@ -38,7 +38,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/mainboard/lenovo/t430s/dsdt.asl b/src/mainboard/lenovo/t430s/dsdt.asl index f0c56c1..c549988 100644 --- a/src/mainboard/lenovo/t430s/dsdt.asl +++ b/src/mainboard/lenovo/t430s/dsdt.asl @@ -46,7 +46,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/t520/dsdt.asl b/src/mainboard/lenovo/t520/dsdt.asl index 365fd0d..7db8344 100644 --- a/src/mainboard/lenovo/t520/dsdt.asl +++ b/src/mainboard/lenovo/t520/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/t530/dsdt.asl b/src/mainboard/lenovo/t530/dsdt.asl index 365fd0d..7db8344 100644 --- a/src/mainboard/lenovo/t530/dsdt.asl +++ b/src/mainboard/lenovo/t530/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl index 8ad7ace..bb576f5 100644 --- a/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl +++ b/src/mainboard/lenovo/x1_carbon_gen1/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/x201/dsdt.asl b/src/mainboard/lenovo/x201/dsdt.asl index 92bc55a..b59c215 100644 --- a/src/mainboard/lenovo/x201/dsdt.asl +++ b/src/mainboard/lenovo/x201/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/nehalem/acpi/nehalem.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/x220/dsdt.asl b/src/mainboard/lenovo/x220/dsdt.asl index 365fd0d..7db8344 100644 --- a/src/mainboard/lenovo/x220/dsdt.asl +++ b/src/mainboard/lenovo/x220/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/lenovo/x230/dsdt.asl b/src/mainboard/lenovo/x230/dsdt.asl index 365fd0d..7db8344 100644 --- a/src/mainboard/lenovo/x230/dsdt.asl +++ b/src/mainboard/lenovo/x230/dsdt.asl @@ -45,7 +45,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/packardbell/ms2290/dsdt.asl b/src/mainboard/packardbell/ms2290/dsdt.asl index 36234b1..338ecca 100644 --- a/src/mainboard/packardbell/ms2290/dsdt.asl +++ b/src/mainboard/packardbell/ms2290/dsdt.asl @@ -39,7 +39,6 @@ { #include <northbridge/intel/nehalem/acpi/nehalem.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/roda/rv11/dsdt.asl b/src/mainboard/roda/rv11/dsdt.asl index 18fb1ca..4934eed 100644 --- a/src/mainboard/roda/rv11/dsdt.asl +++ b/src/mainboard/roda/rv11/dsdt.asl @@ -42,7 +42,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> #include <acpi/brightness_levels.asl> } diff --git a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index 0b93cd6..0000000 --- a/src/mainboard/samsung/lumpy/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 16 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 17 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, - Package() { 0x001fffff, 3, 0, 17 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKB, 0 }, - }) - } -} diff --git a/src/mainboard/samsung/lumpy/dsdt.asl b/src/mainboard/samsung/lumpy/dsdt.asl index 135919e..f42bec6 100644 --- a/src/mainboard/samsung/lumpy/dsdt.asl +++ b/src/mainboard/samsung/lumpy/dsdt.asl @@ -43,7 +43,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl b/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl deleted file mode 100644 index fb9d5ad..0000000 --- a/src/mainboard/samsung/stumpy/acpi/sandybridge_pci_irqs.asl +++ /dev/null @@ -1,64 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for Sandybridge */ - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 22 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 17 }, - Package() { 0x001cffff, 1, 0, 18 }, - Package() { 0x001cffff, 2, 0, 19 }, - Package() { 0x001cffff, 3, 0, 20 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, 0, 19 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, 0, 20 }, - // LPC devices 0:1f.0 - Package() { 0x001fffff, 0, 0, 21 }, - Package() { 0x001fffff, 1, 0, 22 }, - Package() { 0x001fffff, 2, 0, 23 }, - Package() { 0x001fffff, 3, 0, 16 }, - }) - } Else { - Return (Package() { - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - // EHCI #1 0:1d.0 - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - // EHCI #2 0:1a.0 - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKG, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKA, 0 }, - }) - } -} diff --git a/src/mainboard/samsung/stumpy/dsdt.asl b/src/mainboard/samsung/stumpy/dsdt.asl index 3e13a41..c1ea0e6 100644 --- a/src/mainboard/samsung/stumpy/dsdt.asl +++ b/src/mainboard/samsung/stumpy/dsdt.asl @@ -44,7 +44,6 @@ { #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include "acpi/sandybridge_pci_irqs.asl" #include <drivers/intel/gma/acpi/default_brightness_levels.asl> } diff --git a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl index eb98bb2..6247fe3 100644 --- a/src/mainboard/sapphire/pureplatinumh61/dsdt.asl +++ b/src/mainboard/sapphire/pureplatinumh61/dsdt.asl @@ -40,7 +40,6 @@ #include <northbridge/intel/sandybridge/acpi/sandybridge.asl> #include <drivers/intel/gma/acpi/default_brightness_levels.asl> #include <southbridge/intel/bd82x6x/acpi/pch.asl> - #include <southbridge/intel/bd82x6x/acpi/default_irq_route.asl> } } } diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index fe1ca34..ed2b979 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -25,6 +25,7 @@ def_bool y select ACPI_INTEL_HARDWARE_SLEEP_VALUES select SOUTHBRIDGE_INTEL_COMMON + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select SOUTHBRIDGE_INTEL_COMMON_SMBUS select SOUTHBRIDGE_INTEL_COMMON_SPI select IOAPIC diff --git a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl b/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl deleted file mode 100644 index 0e6f960..0000000 --- a/src/southbridge/intel/bd82x6x/acpi/default_irq_route.asl +++ /dev/null @@ -1,77 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* PCI Interrupt Routing */ -Method(_PRT) -{ - If (PICM) { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, 0, 16 },/* GFX INTA -> PIRQA (MSI) */ - /* PCI Express Graphics (PEG) 0:1.0 */ - Package() { 0x0001ffff, 0, 0, 16 },/* GFX PCIe INTA -> PIRQA (MSI) */ - Package() { 0x0001ffff, 0, 0, 17 },/* GFX PCIe INTB -> PIRQB (MSI) */ - Package() { 0x0001ffff, 0, 0, 18 },/* GFX PCIe INTC -> PIRQC (MSI) */ - Package() { 0x0001ffff, 0, 0, 19 },/* GFX PCIe INTD -> PIRQD (MSI) */ - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, 0, 19 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, 0, 16 },/* D27IP_ZIP HDA INTA -> PIRQA (MSI) */ - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, 0, 17 },/* D28IP_P1IP PCIe INTA -> PIRQB */ - Package() { 0x001cffff, 1, 0, 21 },/* D28IP_P2IP PCIe INTB -> PIRQF */ - Package() { 0x001cffff, 2, 0, 19 },/* D28IP_P3IP PCIe INTC -> PIRQD */ - Package() { 0x001cffff, 3, 0, 20 },/* D28IP_P3IP PCIe INTD -> PIRQE */ - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, 0, 19 },/* D29IP_E1P EHCI1 INTA -> PIRQD */ - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, 0, 21 },/* D26IP_E2P EHCI2 INTA -> PIRQF */ - /* LPC devices 0:1f.0 */ - Package() { 0x001fffff, 0, 0, 17 }, /* D31IP_SIP SATA INTA -> PIRQB (MSI) */ - Package() { 0x001fffff, 1, 0, 23 }, /* D31IP_SMIP SMBUS INTB -> PIRQH */ - Package() { 0x001fffff, 2, 0, 16 }, /* D31IP_TTIP THRT INTC -> PIRQA */ - Package() { 0x001fffff, 3, 0, 18 }, - }) - } Else { - Return (Package() { - /* Onboard graphics (IGD) 0:2.0 */ - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCI Express Graphics (PEG) 0:1.0 */ - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* XHCI 0:14.0 (ivy only) */ - Package() { 0x0014ffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* High Definition Audio 0:1b.0 */ - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - /* PCIe Root Ports 0:1c.x */ - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKF, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKD, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKE, 0 }, - /* EHCI #1 0:1d.0 */ - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKD, 0 }, - /* EHCI #2 0:1a.0 */ - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKF, 0 }, - /* LPC device 0:1f.0 */ - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKH, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 3, \_SB.PCI0.LPCB.LNKC, 0 }, - }) - } -} diff --git a/src/southbridge/intel/bd82x6x/lpc.c b/src/southbridge/intel/bd82x6x/lpc.c index 2bfc1e3..7f61669 100644 --- a/src/southbridge/intel/bd82x6x/lpc.c +++ b/src/southbridge/intel/bd82x6x/lpc.c @@ -35,6 +35,7 @@ #include "pch.h" #include "nvs.h" #include <southbridge/intel/common/pciehp.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #define NMI_OFF 0 @@ -821,6 +822,7 @@ config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(dev); } static void lpc_final(struct device *dev) -- To view, visit https://review.coreboot.org/22859 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I832a86925283d61b64b8268246d9e6f11994c120 Gerrit-Change-Number: 22859 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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coreboot-gerrit December 2017