coreboot-gerrit December 2017

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Change in coreboot[master]: amd/common/psp: Enable PSP command register once
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22846 ) Change subject: amd/common/psp: Enable PSP command register once ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19273/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64474/ : SUCCESS -- To view, visit https://review.coreboot.org/22846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Gerrit-Change-Number: 22846 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 19:28:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: inlcude/cpu/x86: Add clflush inline function
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22848 ) Change subject: inlcude/cpu/x86: Add clflush inline function ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19275/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64476/ : SUCCESS -- To view, visit https://review.coreboot.org/22848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Gerrit-Change-Number: 22848 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 19:28:55 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: amd/common/psp: Flush buffer before commands
by Marshall Dawson (Code Review) 13 Dec '17

13 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22849 Change subject: amd/common/psp: Flush buffer before commands ...................................................................... amd/common/psp: Flush buffer before commands The PSP and x86 caches are not coherent. Although the PSP can read information from the x86 cache, its updates to the command-response buffer go to DRAM. Flush the cacheline(s) containing the command-response buffer prior to issuing the command, and ensure it is accurately read after the completion. BUG=b:67309243 Change-Id: I2aa7bbddcb2197aeb9f92683465d014ec97ac64c Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 26 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/49/22849/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 8035a61..e9f9da8 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -15,6 +15,8 @@ #include <arch/io.h> #include <arch/early_variables.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/cache.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> @@ -173,6 +175,28 @@ } /* + * The PSP's cache is not fully coherent with the x86's and PSP writes to the + * buffer go to DRAM. This flushes the buffer so that once the x86 reads the + * buffer again, it refills modified values from DRAM. + * + * This function should be called on an as-needed basis depending on the + * command. Some commands do not use a buffer. + */ +static void flush_buffer(void *buffer, size_t sz) +{ + int i; + u8 *b = (u8 *)buffer; + int lines = ALIGN_UP((uintptr_t)buffer + sz, CACHELINE_SIZE) + - ALIGN_DOWN((uintptr_t)buffer, CACHELINE_SIZE); + lines /= CACHELINE_SIZE; + + for (i = 0 ; i < lines ; i++) { + mfence(); + clflush(b + i * 64); + } +} + +/* * Notify the PSP that DRAM is present. Upon receiving this command, the PSP * will load its OS into fenced DRAM that is not accessible to the x86 cores. */ @@ -187,6 +211,7 @@ printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); + flush_buffer(&buffer, sizeof(buffer)); cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); /* buffer's status shouldn't change but report it if it does */ @@ -217,6 +242,7 @@ printk(BIOS_DEBUG, "PSP: Notify that POST is finishing... "); + flush_buffer(&buffer, sizeof(buffer)); cmd_status = send_psp_command(MBOX_BIOS_CMD_BOOT_DONE, &buffer); /* buffer's status shouldn't change but report it if it does */ -- To view, visit https://review.coreboot.org/22849 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2aa7bbddcb2197aeb9f92683465d014ec97ac64c Gerrit-Change-Number: 22849 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: inlcude/cpu/x86: Add clflush inline function
by Marshall Dawson (Code Review) 13 Dec '17

13 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22848 Change subject: inlcude/cpu/x86: Add clflush inline function ...................................................................... inlcude/cpu/x86: Add clflush inline function Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/include/cpu/x86/cache.h 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22848/1 diff --git a/src/include/cpu/x86/cache.h b/src/include/cpu/x86/cache.h index 2c8c44b..e0a3359 100644 --- a/src/include/cpu/x86/cache.h +++ b/src/include/cpu/x86/cache.h @@ -50,6 +50,11 @@ asm volatile("invd" ::: "memory"); } +static inline void clflush(void *addr) +{ + asm volatile ("clflush (%0)"::"r" (addr)); +} + /* The following functions require the always_inline due to AMD * function STOP_CAR_AND_CPU that disables cache as * RAM, the cache as RAM stack can no longer be used. Called -- To view, visit https://review.coreboot.org/22848 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I74c5cc22f02302314ba010bc599051c1495a13cb Gerrit-Change-Number: 22848 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/common/psp: Convert structure init to C99
by Marshall Dawson (Code Review) 13 Dec '17

13 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22847 Change subject: amd/common/psp: Convert structure init to C99 ...................................................................... amd/common/psp: Convert structure init to C99 Use C99 designated initializers for the psp_notify_dram() buffer structure. Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 5 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22847/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index c1174bc..cfe95f0 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -177,13 +177,14 @@ */ int psp_notify_dram(void) { - struct mbox_default_buffer buffer; int cmd_status; + struct mbox_default_buffer buffer = { + .header = { + .size = sizeof(buffer) + } + }; printk(BIOS_DEBUG, "PSP: Notify that DRAM is available... "); - - buffer.header.size = sizeof(struct mbox_default_buffer); - buffer.header.status = 0; /* PSP does not report status for this cmd */ cmd_status = send_psp_command(MBOX_BIOS_CMD_DRAM_INFO, &buffer); -- To view, visit https://review.coreboot.org/22847 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2e18b3a2c19b8fb17d0f654b16def52517538957 Gerrit-Change-Number: 22847 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: amd/common/psp: Enable PSP command register once
by Marshall Dawson (Code Review) 13 Dec '17

13 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22846 Change subject: amd/common/psp: Enable PSP command register once ...................................................................... amd/common/psp: Enable PSP command register once Reduce the number of times the PSP's bus-mastering and memory access is enabled. Only write the command register once per stage and leave it enabled. Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/psp/psp.c 1 file changed, 32 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/22846/1 diff --git a/src/soc/amd/common/block/psp/psp.c b/src/soc/amd/common/block/psp/psp.c index 5aedfc1..c1174bc 100644 --- a/src/soc/amd/common/block/psp/psp.c +++ b/src/soc/amd/common/block/psp/psp.c @@ -14,6 +14,7 @@ */ #include <arch/io.h> +#include <arch/early_variables.h> #include <cbfs.h> #include <region_file.h> #include <timer.h> @@ -49,6 +50,20 @@ } } +static int master_enabled CAR_GLOBAL = 0; + +static void enable_master(void) +{ + u32 command_reg; + + if (!master_enabled) { + command_reg = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); + command_reg |= PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER; + pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg); + master_enabled = 1; + } +} + static struct psp_mbox *get_mbox_address(void) { UINT32 base; /* UINT32 for compatibility with PspBaseLib */ @@ -63,6 +78,7 @@ if (!bar3_status) return NULL; + enable_master(); baseptr = base; return (struct psp_mbox *)(baseptr + PSP_MAILBOX_BASE); } @@ -122,56 +138,37 @@ static int send_psp_command(u32 command, void *buffer) { - u32 command_reg; - int status = 0; - struct psp_mbox *mbox = get_mbox_address(); if (!mbox) return -PSPSTS_NOBASE; - command_reg = pci_read_config32(SOC_PSP_DEV, PCI_COMMAND); - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg | - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); - /* check for PSP error conditions */ - if (rd_mbox_sts(mbox) & STATUS_HALT) { - status = -PSPSTS_HALTED; - goto exit; - } - if (rd_mbox_sts(mbox) & STATUS_RECOVERY) { - status = -PSPSTS_RECOVERY; - goto exit; - } + if (rd_mbox_sts(mbox) & STATUS_HALT) + return -PSPSTS_HALTED; + + if (rd_mbox_sts(mbox) & STATUS_RECOVERY) + return -PSPSTS_RECOVERY; /* PSP must be finished with init and ready to accept a command */ - if (wait_initialized(mbox)) { - status = -PSPSTS_INIT_TIMEOUT; - goto exit; - } - if (wait_command(mbox)) { - status = -PSPSTS_CMD_TIMEOUT; - goto exit; - } + if (wait_initialized(mbox)) + return -PSPSTS_INIT_TIMEOUT; + + if (wait_command(mbox)) + return -PSPSTS_CMD_TIMEOUT; /* set address of command-response buffer and write command register */ wr_mbox_cmd_resp(mbox, buffer); wr_mbox_cmd(mbox, command); /* PSP clears command register when complete */ - if (wait_command(mbox)) { - status = -PSPSTS_CMD_TIMEOUT; - goto exit; - } + if (wait_command(mbox)) + return -PSPSTS_CMD_TIMEOUT; /* check delivery status */ - if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED)) { - status = -PSPSTS_SEND_ERROR; - goto exit; - } -exit: - /* restore command register to original value */ - pci_write_config32(SOC_PSP_DEV, PCI_COMMAND, command_reg); - return status; + if (rd_mbox_sts(mbox) & (STATUS_ERROR | STATUS_TERMINATED)) + return -PSPSTS_SEND_ERROR; + + return 0; } /* -- To view, visit https://review.coreboot.org/22846 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I7e29a3935df94d16de90b28ff78449d23fe01666 Gerrit-Change-Number: 22846 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_EN
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22844 ) Change subject: mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_EN ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64471/ : SUCCESS -- To view, visit https://review.coreboot.org/22844 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90d9c009369c53cfec47fe77356e181d5ecf7ad5 Gerrit-Change-Number: 22844 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 18:28:51 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22845 ) Change subject: mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19271/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64472/ : SUCCESS -- To view, visit https://review.coreboot.org/22845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Gerrit-Change-Number: 22845 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 18:26:41 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_EN
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22844 ) Change subject: mb/google/poppy/variants/nami: Fix GPIO config for PCH_SPK_EN ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64470/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19270/ : SUCCESS -- To view, visit https://review.coreboot.org/22844 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I90d9c009369c53cfec47fe77356e181d5ecf7ad5 Gerrit-Change-Number: 22844 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 18:12:04 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree
by Furquan Shaikh (Code Review) 13 Dec '17

13 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22845 Change subject: mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree ...................................................................... mb/google/poppy/variants/nami: Fix SataMode configuration in devicetree Similar to Fizz, SataMode on nami should be set to AHCI. This change fixes the configuration error done in 903472c (mb/google/poppy/variants/nami: Add support for nami board). BUG=b:70160119 Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/mainboard/google/poppy/variants/nami/devicetree.cb 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/45/22845/1 diff --git a/src/mainboard/google/poppy/variants/nami/devicetree.cb b/src/mainboard/google/poppy/variants/nami/devicetree.cb index 401e137..08bdda7 100644 --- a/src/mainboard/google/poppy/variants/nami/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nami/devicetree.cb @@ -27,7 +27,7 @@ # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "0" - register "EnableSata" = "1" + register "EnableSata" = "0" register "SataSalpSupport" = "1" register "SataMode" = "1" register "SataPortsEnable[1]" = "1" -- To view, visit https://review.coreboot.org/22845 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia88b56ae6bd9121f8447f7c1a2f5a10990fb8ed5 Gerrit-Change-Number: 22845 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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coreboot-gerrit December 2017