coreboot-gerrit December 2017

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Change in coreboot[master]: soc/intel/skylake: make tcc_offset take effect
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22818 ) Change subject: soc/intel/skylake: make tcc_offset take effect ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-gerrit/64461/ : SUCCESS -- To view, visit https://review.coreboot.org/22818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Gerrit-Change-Number: 22818 Gerrit-PatchSet: 5 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:45:13 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22839 ) Change subject: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19264/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64459/ : SUCCESS -- To view, visit https://review.coreboot.org/22839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Gerrit-Change-Number: 22839 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:45:11 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/common: Add API to restore power failure into PMC common code
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22838 ) Change subject: soc/intel/common: Add API to restore power failure into PMC common code ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19265/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64458/ : SUCCESS -- To view, visit https://review.coreboot.org/22838 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Gerrit-Change-Number: 22838 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:40:16 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22840 ) Change subject: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19266/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64460/ : SUCCESS -- To view, visit https://review.coreboot.org/22840 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19 Gerrit-Change-Number: 22840 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:39:03 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Make use of common SMM code for SKL
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22826 ) Change subject: soc/intel/skylake: Make use of common SMM code for SKL ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19263/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64457/ : SUCCESS -- To view, visit https://review.coreboot.org/22826 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8163dc7e18bb417e8c18a12628988959c128b3df Gerrit-Change-Number: 22826 Gerrit-PatchSet: 6 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Brandon Breitenstein <brandon.breitenstein(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:33:45 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: make tcc_offset take effect
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22818 ) Change subject: soc/intel/skylake: make tcc_offset take effect ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64456/ : ABORTED -- To view, visit https://review.coreboot.org/22818 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ibc6f33bea19a1d59bc7e407815210942b38f0702 Gerrit-Change-Number: 22818 Gerrit-PatchSet: 4 Gerrit-Owner: Marx Wang <marx.wang(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Duncan Laurie <dlaurie(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 06:22:48 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS
by Subrata Banik (Code Review) 13 Dec '17

13 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22839 Change subject: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS ...................................................................... soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS TEST=System is able to power on after reconnecting power system. Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/skylake/pmc.c 1 file changed, 42 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/22839/1 diff --git a/src/soc/intel/skylake/pmc.c b/src/soc/intel/skylake/pmc.c index 91b319c..5f3ef2b 100644 --- a/src/soc/intel/skylake/pmc.c +++ b/src/soc/intel/skylake/pmc.c @@ -15,6 +15,7 @@ * GNU General Public License for more details. */ +#include <bootstate.h> #include <chip.h> #include <console/console.h> #include <device/device.h> @@ -73,9 +74,24 @@ REG_SCRIPT_END }; +/* + * Determines what state to go to when power is reapplied + * after a power failure (G3 State) + */ +static void pmc_set_afterg3(struct device *dev, int s5pwr) +{ + uint8_t reg8; + + reg8 = pci_read_config8(PCH_DEV_PMC, GEN_PMCON_B); + if (s5pwr == MAINBOARD_POWER_ON) + reg8 &= ~1; + else + reg8 |= 1; + pci_write_config8(PCH_DEV_PMC, GEN_PMCON_B, reg8); +} + static void pch_power_options(struct device *dev) { - u16 reg16; const char *state; /* Get the chip configuration */ @@ -91,25 +107,20 @@ /*TODO: cmos_layout.bin need to verify; cause wrong CMOS setup*/ //get_option(&pwr_on, "power_on_after_fail"); pwr_on = MAINBOARD_POWER_ON; - reg16 = pci_read_config16(dev, GEN_PMCON_B); - reg16 &= 0xfffe; switch (pwr_on) { case MAINBOARD_POWER_OFF: - reg16 |= 1; state = "off"; break; case MAINBOARD_POWER_ON: - reg16 &= ~1; state = "on"; break; case MAINBOARD_POWER_KEEP: - reg16 &= ~1; state = "state keep"; break; default: state = "undefined"; } - pci_write_config16(dev, GEN_PMCON_B, reg16); + pmc_set_afterg3(dev, pwr_on); printk(BIOS_INFO, "Set power %s after power failure.\n", state); /* Set up GPE configuration. */ @@ -178,4 +189,28 @@ /* Clear registers that contain write-1-to-clear bits. */ reg_script_run_on_dev(dev, pmc_write1_to_clear_script); } + +/* + * Set PMC register to know which state system should be after + * power reapplied + */ +void pmc_soc_restore_power_failiure(void) +{ + pmc_set_afterg3(PCH_DEV_PMC, MAINBOARD_POWER_ON); +} + +static void pm1_enable_pwrbtn_smi(void *unused) +{ + /* + * Enable power button SMI only before jumping to payload. This ensures + * that: + * 1. Power button SMI is enabled only after coreboot is done. + * 2. On resume path, power button SMI is not enabled and thus avoids + * any shutdowns because of power button presses due to power button + * press in resume path. + */ + pmc_update_pm1_enable(PWRBTN_EN); +} + +BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_EXIT, pm1_enable_pwrbtn_smi, NULL); #endif -- To view, visit https://review.coreboot.org/22839 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Gerrit-Change-Number: 22839 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS
by Subrata Banik (Code Review) 13 Dec '17

13 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22840 Change subject: soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS ...................................................................... soc/intel/cannonlake: Implement pmc_soc_restore_power_failure as per EDS TEST=System is able to power on after reconnecting power system. Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/cannonlake/include/soc/pm.h M src/soc/intel/cannonlake/pmc.c 2 files changed, 30 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/22840/1 diff --git a/src/soc/intel/cannonlake/include/soc/pm.h b/src/soc/intel/cannonlake/include/soc/pm.h index 378fac9..d92d4f4 100644 --- a/src/soc/intel/cannonlake/include/soc/pm.h +++ b/src/soc/intel/cannonlake/include/soc/pm.h @@ -140,6 +140,10 @@ #define ENABLE_SMI_PARAMS \ (APMC_EN | SLP_SMI_EN | GBL_SMI_EN | ESPI_SMI_EN | EOS) +#define MAINBOARD_POWER_OFF 0 +#define MAINBOARD_POWER_ON 1 +#define MAINBOARD_POWER_KEEP 2 + #define PSS_RATIO_STEP 2 #define PSS_MAX_ENTRIES 8 #define PSS_LATENCY_TRANSITION 10 diff --git a/src/soc/intel/cannonlake/pmc.c b/src/soc/intel/cannonlake/pmc.c index 6ec4d38..68b2325 100644 --- a/src/soc/intel/cannonlake/pmc.c +++ b/src/soc/intel/cannonlake/pmc.c @@ -25,6 +25,32 @@ #include <soc/pci_devs.h> #include <soc/pm.h> +/* + * Determines what state to go to when power is reapplied + * after a power failure (G3 State) + */ +static void pmc_set_afterg3(int s5pwr) +{ + uint32_t reg32; + uint8_t *pmcbase = pmc_mmio_regs(); + + reg32 = read32(pmcbase + GEN_PMCON_A); + if (s5pwr == MAINBOARD_POWER_ON) + reg32 &= ~1; + else + reg32 |= 1; + write32(pmcbase + GEN_PMCON_A, reg32); +} + +/* + * Set PMC register to know which state system should be after + * power reapplied + */ +void pmc_soc_restore_power_failiure(void) +{ + pmc_set_afterg3(MAINBOARD_POWER_ON); +} + static void config_deep_sX(uint32_t offset, uint32_t mask, int sx, int enable) { uint32_t reg; -- To view, visit https://review.coreboot.org/22840 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I41e655fe79d958cce9e627ea2f2380185364ab19 Gerrit-Change-Number: 22840 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: soc/intel/common: Add API to restore power failure into PMC common code
by Subrata Banik (Code Review) 13 Dec '17

13 Dec '17

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/22838 Change subject: soc/intel/common: Add API to restore power failure into PMC common code ...................................................................... soc/intel/common: Add API to restore power failure into PMC common code PMC config register need to program to define which state system should be after reapplied power from G3 state. 0 = System will return to S0 state 1 = System will return to S5 state Refer to EDS for detailed programming sequence. Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Signed-off-by: Subrata Banik <subrata.banik(a)intel.com> --- M src/soc/intel/common/block/include/intelblocks/pmclib.h M src/soc/intel/common/block/pmc/pmclib.c 2 files changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/22838/1 diff --git a/src/soc/intel/common/block/include/intelblocks/pmclib.h b/src/soc/intel/common/block/include/intelblocks/pmclib.h index a045bbe..38169de 100644 --- a/src/soc/intel/common/block/include/intelblocks/pmclib.h +++ b/src/soc/intel/common/block/include/intelblocks/pmclib.h @@ -133,6 +133,12 @@ void pmc_clear_prsts(void); /* + * Set PMC register to know which state system should be after + * power reapplied + */ +void pmc_soc_restore_power_failiure(void); + +/* * Enable or disable global reset. If global reset is enabled, hard reset and * soft reset will trigger global reset, where both host and TXE are reset. * This is cleared on cold boot, hard reset, soft reset and Sx. diff --git a/src/soc/intel/common/block/pmc/pmclib.c b/src/soc/intel/common/block/pmc/pmclib.c index f653bf0..9c64ba2 100644 --- a/src/soc/intel/common/block/pmc/pmclib.c +++ b/src/soc/intel/common/block/pmc/pmclib.c @@ -80,6 +80,18 @@ return generic_sts; } +/* + * Set PMC register to know which state system should be after + * power reapplied + */ +__attribute__ ((weak)) void pmc_soc_restore_power_failiure(void) +{ + /* + * SoC code should set PMC config register in order to set + * MAINBOARD_POWER_ON bit as per EDS. + */ +} + static uint32_t pmc_reset_smi_status(void) { uint32_t smi_sts = inl(ACPI_BASE_ADDRESS + SMI_STS); -- To view, visit https://review.coreboot.org/22838 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Gerrit-Change-Number: 22838 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com>

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Change in coreboot[master]: mb/google/fizz: set SataMode to ahci mode
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22837 ) Change subject: mb/google/fizz: set SataMode to ahci mode ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19262/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64455/ : SUCCESS -- To view, visit https://review.coreboot.org/22837 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2a9aa2d6281a916c00ff4659a927f164ba0e0705 Gerrit-Change-Number: 22837 Gerrit-PatchSet: 3 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 04:19:59 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017