coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: intel/bd82x6x: Add GBE ACPI device
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22807 ) Change subject: intel/bd82x6x: Add GBE ACPI device ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19251/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64444/ : SUCCESS -- To view, visit https://review.coreboot.org/22807 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I02613169498eed3d6d9ea5963ea3c2c08a40ef99 Gerrit-Change-Number: 22807 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 00:53:20 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/sandybridge: Add RAM voltage hooks
by build bot (Jenkins) (Code Review) 13 Dec '17

13 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22806 ) Change subject: intel/sandybridge: Add RAM voltage hooks ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19254/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64447/ : SUCCESS -- To view, visit https://review.coreboot.org/22806 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic714c0717a66089dad4423d4eca5a0a29b7af817 Gerrit-Change-Number: 22806 Gerrit-PatchSet: 2 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 13 Dec 2017 00:50:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: intel/dcp847ske: Enable RAM voltage setting
by Tobias Diedrich (Code Review) 13 Dec '17

13 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22836 Change subject: intel/dcp847ske: Enable RAM voltage setting ...................................................................... intel/dcp847ske: Enable RAM voltage setting Use the hooks introduced in https://review.coreboot.org/#/c/22806/ to enable setting the RAM voltage before RAM training. Change-Id: Ib0e2b4e90b5eda2da14834f4721649fd77ec1025 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/intel/dcp847ske/romstage.c 1 file changed, 18 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/22836/1 diff --git a/src/mainboard/intel/dcp847ske/romstage.c b/src/mainboard/intel/dcp847ske/romstage.c index ad31bba..98bc6dd 100644 --- a/src/mainboard/intel/dcp847ske/romstage.c +++ b/src/mainboard/intel/dcp847ske/romstage.c @@ -16,7 +16,9 @@ * GNU General Public License for more details. */ +#include <console/console.h> #include <stdint.h> +#include <southbridge/intel/common/gpio.h> #include <northbridge/intel/sandybridge/sandybridge.h> #if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) #include <northbridge/intel/sandybridge/raminit_native.h> @@ -24,7 +26,22 @@ #include <northbridge/intel/sandybridge/raminit.h> #endif -#if !IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +#if IS_ENABLED(CONFIG_USE_NATIVE_RAMINIT) +void mainboard_supported_dram_voltage(dimm_voltage_t *voltage) +{ + voltage->min_millivolts = 1350; + voltage->max_millivolts = 1500; +} + +void mainboard_set_dram_voltage(const u16 voltage) +{ + if (voltage < 1500) { + // GPIO8 default from gpio.c is LOW (1.5V). + // Set to HIGH to lower ram voltage to 1.35V. + set_gpio(8, 1); + } +} +#else void mainboard_fill_pei_data(struct pei_data *pei_data) { struct pei_data pei_data_template = { -- To view, visit https://review.coreboot.org/22836 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ib0e2b4e90b5eda2da14834f4721649fd77ec1025 Gerrit-Change-Number: 22836 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: intel/dcp847ske: Enable GBE ACPI device DSM label
by Tobias Diedrich (Code Review) 13 Dec '17

13 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22834 Change subject: intel/dcp847ske: Enable GBE ACPI device DSM label ...................................................................... intel/dcp847ske: Enable GBE ACPI device DSM label Tested: systemd default network interface name changes from enp0s25 to eno1, which matches the Intel BIOS (though there it is due to SMBIOS data). Change-Id: I505d13c5644674da251db352c0bd622e85d5148f Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/intel/dcp847ske/Kconfig 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/22834/1 diff --git a/src/mainboard/intel/dcp847ske/Kconfig b/src/mainboard/intel/dcp847ske/Kconfig index 1fd3d8c..01c45de 100644 --- a/src/mainboard/intel/dcp847ske/Kconfig +++ b/src/mainboard/intel/dcp847ske/Kconfig @@ -11,6 +11,7 @@ select SOUTHBRIDGE_INTEL_C216 select SERIRQ_CONTINUOUS_MODE select INTEL_INT15 + select INTEL_GBE_ACPI_DEVICE_LABEL select MAINBOARD_HAS_LIBGFXINIT menu "Debugging" -- To view, visit https://review.coreboot.org/22834 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I505d13c5644674da251db352c0bd622e85d5148f Gerrit-Change-Number: 22834 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: intel/dcp847ske: Add superio ACPI declarations
by Tobias Diedrich (Code Review) 13 Dec '17

13 Dec '17

Tobias Diedrich has uploaded this change for review. ( https://review.coreboot.org/22835 Change subject: intel/dcp847ske: Add superio ACPI declarations ...................................................................... intel/dcp847ske: Add superio ACPI declarations Tested on Linux 4.13.14: SuperIO resources show up as reserved in /proc/ioports and friends. Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Signed-off-by: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> --- M src/mainboard/intel/dcp847ske/acpi/superio.asl 1 file changed, 28 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/22835/1 diff --git a/src/mainboard/intel/dcp847ske/acpi/superio.asl b/src/mainboard/intel/dcp847ske/acpi/superio.asl index 09f905e..aefb51d 100644 --- a/src/mainboard/intel/dcp847ske/acpi/superio.asl +++ b/src/mainboard/intel/dcp847ske/acpi/superio.asl @@ -1 +1,28 @@ -/* Dummy file required by pch.asl - No license necessary. */ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2016 secunet Security Networks AG + * Copyright (C) 2017 Tobias Diedrich <ranma+coreboot(a)tdiedrich.de> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#undef SUPERIO_DEV +#undef SUPERIO_PNP_BASE +#define SUPERIO_DEV SIO0 +#define SUPERIO_PNP_BASE 0x4e + +#if !IS_ENABLED(CONFIG_DISABLE_UART_ON_TESTPADS) +#define NCT6776_SHOW_SP1 1 +#endif +#define NCT6776_SHOW_HWM 1 +#define NCT6776_SHOW_GPIO 1 + +#include "superio/nuvoton/nct6776/acpi/superio.asl" -- To view, visit https://review.coreboot.org/22835 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I0363816fe048579413f1325dcfc9a6a8a9e48123 Gerrit-Change-Number: 22835 Gerrit-PatchSet: 1 Gerrit-Owner: Tobias Diedrich <ranma+coreboot(a)tdiedrich.de>

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Change in coreboot[master]: ic2/designware: Move Intel i2c logic to shared driver
by build bot (Jenkins) (Code Review) 12 Dec '17

12 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22822 ) Change subject: ic2/designware: Move Intel i2c logic to shared driver ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64442/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19249/ : SUCCESS -- To view, visit https://review.coreboot.org/22822 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Gerrit-Change-Number: 22822 Gerrit-PatchSet: 3 Gerrit-Owner: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Dec 2017 23:38:58 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: src/soc/intel/cannonlake: Add _PRW for CNVi
by build bot (Jenkins) (Code Review) 12 Dec '17

12 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22611 ) Change subject: src/soc/intel/cannonlake: Add _PRW for CNVi ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19248/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64441/ : SUCCESS -- To view, visit https://review.coreboot.org/22611 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id6689754d1c4100615e4e4ae5a7f9846f4bf785f Gerrit-Change-Number: 22611 Gerrit-PatchSet: 5 Gerrit-Owner: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Hima B Chilmakuru <hima.b.chilmakuru(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Dec 2017 22:30:57 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: soc/amd/common/block/pi: Format files to standards
by build bot (Jenkins) (Code Review) 12 Dec '17

12 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22823 ) Change subject: soc/amd/common/block/pi: Format files to standards ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19247/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64440/ : SUCCESS -- To view, visit https://review.coreboot.org/22823 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iefe741cd62bc41a7975c3dd10ac9355352de3abb Gerrit-Change-Number: 22823 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Dec 2017 20:34:31 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: [WIP]intel/cannonlake_rvp: Enable I2C port
by build bot (Jenkins) (Code Review) 12 Dec '17

12 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22812 ) Change subject: [WIP]intel/cannonlake_rvp: Enable I2C port ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19246/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64439/ : SUCCESS -- To view, visit https://review.coreboot.org/22812 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I2f4e220b760731a26450ef30c67e3cc00dd0d04c Gerrit-Change-Number: 22812 Gerrit-PatchSet: 2 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Chiranjeevi Rapolu <chiranjeevi.rapolu(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Dec 2017 19:47:28 +0000 Gerrit-HasComments: No

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Change in coreboot[master]: security/tpm: Setup generic TSPI
by build bot (Jenkins) (Code Review) 12 Dec '17

12 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22106 ) Change subject: security/tpm: Setup generic TSPI ...................................................................... Patch Set 33: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19240/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64433/ : SUCCESS -- To view, visit https://review.coreboot.org/22106 To unsubscribe, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I883c489801fce88e13952fe24b67315ab6bb1afb Gerrit-Change-Number: 22106 Gerrit-PatchSet: 33 Gerrit-Owner: Philipp Deppenwiese <zaolin.daisuki(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Randall Spangler <randall(a)spanglers.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 12 Dec 2017 19:14:42 +0000 Gerrit-HasComments: No

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coreboot-gerrit December 2017