coreboot-gerrit December 2017

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Change in coreboot[master]: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL
by Furquan Shaikh (Code Review) 20 Dec '17

20 Dec '17

Furquan Shaikh has uploaded a new patch set (#2). ( https://review.coreboot.org/22954 ) Change subject: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL ...................................................................... soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides and uses SoC-specific callbacks to identify the right bits to be used for polarity and state while programming the SPI_CS_CONTROL register. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/gspi.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/include/intelblocks/gspi.h M src/soc/intel/skylake/gspi.c 4 files changed, 102 insertions(+), 32 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22954/2 -- To view, visit https://review.coreboot.org/22954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Gerrit-Change-Number: 22954 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL
by Furquan Shaikh (Code Review) 20 Dec '17

20 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22954 Change subject: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL ...................................................................... soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL Even though kaby lake and cannon lake are using the same GSPI controller, bit meanings (for polarity and state) in SPI_CS_CONTROL register are significantly different. This change provides and uses SoC-specific callbacks to identify the right bits to be used for polarity and state while programming the SPI_CS_CONTROL register. BUG=b:70628116 Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/gspi.c M src/soc/intel/common/block/gspi/gspi.c M src/soc/intel/common/block/include/intelblocks/gspi.h M src/soc/intel/skylake/gspi.c 4 files changed, 91 insertions(+), 21 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/22954/1 diff --git a/src/soc/intel/cannonlake/gspi.c b/src/soc/intel/cannonlake/gspi.c index e4f682d..9755ac9 100644 --- a/src/soc/intel/cannonlake/gspi.c +++ b/src/soc/intel/cannonlake/gspi.c @@ -44,6 +44,30 @@ return EARLY_GSPI_BASE_ADDRESS; } +/* Polarity field in SPI_CS_CONTROL indicates inactive polarity. */ +enum { + CS_INACTIVE_POLARITY_LOW, + CS_INACTIVE_POLARITY_HIGH, +}; + +uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol) +{ + if (pol == SPI_POLARITY_LOW) + return CS_INACTIVE_POLARITY_HIGH; + else + return CS_INACTIVE_POLARITY_LOW; +} + +uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol, + enum cs_assert cs_assert) +{ + /* + * CS_STATE field in SPI_CS_CONTROL register indicates + * assert/de-assert. + */ + return cs_assert; +} + /* * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust * the bus # accordingly when referring to SPI / GSPI bus numbers. diff --git a/src/soc/intel/common/block/gspi/gspi.c b/src/soc/intel/common/block/gspi/gspi.c index 8e527ed..d6b303d 100644 --- a/src/soc/intel/common/block/gspi/gspi.c +++ b/src/soc/intel/common/block/gspi/gspi.c @@ -92,12 +92,11 @@ #define SSP_REG 0x220 /* SSP Reg */ #define DMA_FINISH_DISABLE (1 << 0) #define SPI_CS_CONTROL 0x224 /* SPI CS Control */ -#define CS_POLARITY_LOW (0 << 12) -#define CS_POLARITY_HIGH (1 << 12) +#define CS_0_POL_SHIFT (12) +#define CS_0_POL_MASK (1 << CS_0_POL_SHIFT) #define CS_0 (0 << 8) -#define CS_STATE_LOW (0 << 1) -#define CS_STATE_HIGH (1 << 1) -#define CS_STATE_MASK (1 << 1) +#define CS_STATE_SHIFT (1) +#define CS_STATE_MASK (1 << CS_STATE_SHIFT) #define CS_MODE_HW (0 << 0) #define CS_MODE_SW (1 << 0) @@ -260,25 +259,18 @@ return 0; } -enum cs_assert { - CS_ASSERT, - CS_DEASSERT, -}; - static void __gspi_cs_change(const struct gspi_ctrlr_params *p, enum cs_assert cs_assert) { - uint32_t cs_ctrl, state; + uint32_t cs_ctrl, pol; cs_ctrl = gspi_read_mmio_reg(p, SPI_CS_CONTROL); cs_ctrl &= ~CS_STATE_MASK; - if (cs_ctrl & CS_POLARITY_HIGH) - state = (cs_assert == CS_ASSERT) ? CS_STATE_HIGH : CS_STATE_LOW; - else - state = (cs_assert == CS_ASSERT) ? CS_STATE_LOW : CS_STATE_HIGH; + pol = !!(cs_ctrl & CS_0_POL_MASK); - cs_ctrl |= state; + cs_ctrl |= !!gspi_soc_csctrl_state(p->gspi_bus, pol, + cs_assert) << CS_STATE_SHIFT; gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); } @@ -330,7 +322,7 @@ static int gspi_ctrlr_setup(const struct spi_slave *dev) { struct spi_cfg cfg; - uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf; + uint32_t cs_ctrl, sscr0, sscr1, clocks, sitf, sirf, pol; struct gspi_ctrlr_params params, *p = &params; /* Only chip select 0 is supported. */ @@ -364,10 +356,10 @@ * - Do not assert CS. */ cs_ctrl = CS_MODE_SW | CS_0; - if (cfg.cs_polarity == SPI_POLARITY_LOW) - cs_ctrl |= CS_POLARITY_LOW | CS_STATE_HIGH; - else - cs_ctrl |= CS_POLARITY_HIGH | CS_STATE_LOW; + pol = !!gspi_soc_csctrl_polarity(p->gspi_bus, cfg.cs_polarity); + cs_ctrl |= pol << CS_0_POL_SHIFT; + cs_ctrl |= !!gspi_soc_csctrl_state(p->gspi_bus, pol, + CS_DEASSERT) << CS_STATE_SHIFT; gspi_write_mmio_reg(p, SPI_CS_CONTROL, cs_ctrl); /* Disable SPI controller. */ diff --git a/src/soc/intel/common/block/include/intelblocks/gspi.h b/src/soc/intel/common/block/include/intelblocks/gspi.h index 4e10e25..4b0f3cc 100644 --- a/src/soc/intel/common/block/include/intelblocks/gspi.h +++ b/src/soc/intel/common/block/include/intelblocks/gspi.h @@ -29,6 +29,11 @@ uint8_t early_init; }; +enum cs_assert { + CS_ASSERT, + CS_DEASSERT, +}; + /* GSPI controller APIs. */ void gspi_early_bar_init(void); @@ -65,4 +70,21 @@ */ int gspi_get_soc_spi_cfg(unsigned int bus, struct spi_cfg *cfg); +/* + * SoC callback to return the value of CS_0_POLARITY field in SPI_CS_CONTROL + * register based on the following input parameters: + * gspi_bus = GSPI bus number + * pol = Active polarity of chip-select to the SPI device + */ +uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol); + +/* + * SoC callback to return the value of CS_STATE field in SPI_CS_CONTROL register + * based on the following input parameters: + * gspi_bus = GSPI bus number + * cs_ctrl_pol = Value of polarity field in SPI_CS_CONTROL register + * cs_assert = Chip-select operation to be performed(assert/de-assert) + */ +uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol, + enum cs_assert cs_assert); #endif /* SOC_INTEL_COMMON_BLOCK_GSPI_H */ diff --git a/src/soc/intel/skylake/gspi.c b/src/soc/intel/skylake/gspi.c index 252be77..910f59f 100644 --- a/src/soc/intel/skylake/gspi.c +++ b/src/soc/intel/skylake/gspi.c @@ -43,6 +43,38 @@ return EARLY_GSPI_BASE_ADDRESS; } +/* Polarity field in SPI_CS_CONTROL indicates active polarity. */ +enum { + CS_ACTIVE_POLARITY_LOW, + CS_ACTIVE_POLARITY_HIGH, +}; + +enum { + CS_STATE_LOW, + CS_STATE_HIGH +}; + +uint32_t gspi_soc_csctrl_polarity(unsigned int gspi_bus, enum spi_polarity pol) +{ + if (pol == SPI_POLARITY_LOW) + return CS_ACTIVE_POLARITY_LOW; + else + return CS_ACTIVE_POLARITY_HIGH; +} + +uint32_t gspi_soc_csctrl_state(unsigned int gspi_bus, uint32_t cs_ctrl_pol, + enum cs_assert cs_assert) +{ + uint32_t state; + + if (cs_ctrl_pol == CS_ACTIVE_POLARITY_HIGH) + state = (cs_assert == CS_ASSERT) ? CS_STATE_HIGH : CS_STATE_LOW; + else + state = (cs_assert == CS_ASSERT) ? CS_STATE_LOW : CS_STATE_HIGH; + + return state; +} + /* * SPI Bus 0 is Fast SPI and GSPI starts from SPI bus # 1 onwards. Thus, adjust * the bus # accordingly when referring to SPI / GSPI bus numbers. -- To view, visit https://review.coreboot.org/22954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Gerrit-Change-Number: 22954 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: google/chromeec: Enable unified host event programming interface
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21085 ) Change subject: google/chromeec: Enable unified host event programming interface ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19616/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64840/ : SUCCESS -- To view, visit https://review.coreboot.org/21085 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4917a222c79b6aaecb71d7704ffde57bf3bc99d9 Gerrit-Change-Number: 21085 Gerrit-PatchSet: 9 Gerrit-Owner: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Jenny Tc <jenny.tc(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Shamile Khan <shamile.khan(a)intel.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 12:54:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19615/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64839/ : SUCCESS -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 6 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 10:43:47 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support ...................................................................... Patch Set 5: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64838/ : FAILURE -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 5 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 10:33:24 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19614/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64837/ : SUCCESS -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 4 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 10:29:09 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19613/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64836/ : SUCCESS -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 3 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 09:16:41 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel/skylake: Add PcieRpClkSrcNumber UPD configuartion support ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19612/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64835/ : SUCCESS -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 2 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Naresh Solanki <naresh.solanki(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 08:45:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22839 ) Change subject: soc/intel/skylake: Implement pmc_soc_restore_power_failure as per EDS ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19606/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64828/ : SUCCESS -- To view, visit https://review.coreboot.org/22839 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic707164a576ffb25418eb6553843cd8edc608800 Gerrit-Change-Number: 22839 Gerrit-PatchSet: 8 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Rizwan Qureshi <rizwan.qureshi(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 20 Dec 2017 08:07:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel/common: Add API to restore power failure into PMC common code
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22838 ) Change subject: soc/intel/common: Add API to restore power failure into PMC common code ...................................................................... Patch Set 9: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19611/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64834/ : SUCCESS -- To view, visit https://review.coreboot.org/22838 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0ce2cc77745d00a8cfe3eed7c6372af77e063d02 Gerrit-Change-Number: 22838 Gerrit-PatchSet: 9 Gerrit-Owner: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Barnali Sarkar <barnali.sarkar(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: dhaval v sharma <dhaval.v.sharma(a)intel.com> Gerrit-Comment-Date: Wed, 20 Dec 2017 08:06:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017