coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce
by Elyes HAOUAS (Code Review) 20 Dec '17

20 Dec '17

Elyes HAOUAS has uploaded this change for review. ( https://review.coreboot.org/22957 Change subject: nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce ...................................................................... nb/intel/fsp_rangeley: Use MSR_PLATFORM_INFO instead of 0xce Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Signed-off-by: Elyes HAOUAS <ehaouas(a)noos.fr> --- M src/include/cpu/x86/tsc.h M src/northbridge/intel/fsp_rangeley/udelay.c 2 files changed, 3 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/22957/1 diff --git a/src/include/cpu/x86/tsc.h b/src/include/cpu/x86/tsc.h index 4cf4fbc..35c8a82 100644 --- a/src/include/cpu/x86/tsc.h +++ b/src/include/cpu/x86/tsc.h @@ -11,6 +11,8 @@ #define TSC_SYNC #endif +#define MSR_PLATFORM_INFO 0xce + struct tsc_struct { unsigned int lo; unsigned int hi; diff --git a/src/northbridge/intel/fsp_rangeley/udelay.c b/src/northbridge/intel/fsp_rangeley/udelay.c index 5aca229..01989ab 100644 --- a/src/northbridge/intel/fsp_rangeley/udelay.c +++ b/src/northbridge/intel/fsp_rangeley/udelay.c @@ -43,7 +43,7 @@ u32 fsb = 100, divisor; u32 d; /* ticks per us */ - msr = rdmsr(0xce); + msr = rdmsr(MSR_PLATFORM_INFO); divisor = (msr.lo >> 8) & 0xff; d = fsb * divisor; -- To view, visit https://review.coreboot.org/22957 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ifb8aa43b6545482bc7fc136a90c4bbaa18d46089 Gerrit-Change-Number: 22957 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes HAOUAS <ehaouas(a)noos.fr>

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Change in coreboot[master]: soc/intel/cannonlake: Initialize DDI-A lane in Normal mode.
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22799 ) Change subject: soc/intel/cannonlake: Initialize DDI-A lane in Normal mode. ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64846/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19622/ : SUCCESS -- To view, visit https://review.coreboot.org/22799 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I6353020f892f2d7b75997eace88b3074adc32aef Gerrit-Change-Number: 22799 Gerrit-PatchSet: 3 Gerrit-Owner: Abhay Kumar <abhay.kumar(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 20:17:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22956 ) Change subject: soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64845/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19621/ : SUCCESS -- To view, visit https://review.coreboot.org/22956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Gerrit-Change-Number: 22956 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 19:31:49 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events
by Patrick Rudolph (Code Review) 20 Dec '17

20 Dec '17

Patrick Rudolph has posted comments on this change. ( https://review.coreboot.org/22931 ) Change subject: ec/h8: Store PWRS and notify CPU on AC power plug/unplug events ...................................................................... Patch Set 1: Code-Review+1 Looks good, but needs tests on Linux and Windows. -- To view, visit https://review.coreboot.org/22931 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0818d10474523fb14f7ba7cfbf61166b89442083 Gerrit-Change-Number: 22931 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Alexander Couzens <lynxis(a)fe80.eu> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 19:27:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22954 ) Change subject: soc/intel/common/block/gspi: Add SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 ...................................................................... Patch Set 3: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64844/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19620/ : SUCCESS -- To view, visit https://review.coreboot.org/22954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Gerrit-Change-Number: 22954 Gerrit-PatchSet: 3 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 19:21:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
by Furquan Shaikh (Code Review) 20 Dec '17

20 Dec '17

Furquan Shaikh has uploaded this change for review. ( https://review.coreboot.org/22956 Change subject: soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 ...................................................................... soc/intel/cannonlake: Select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 BUG=b:70628116 Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Signed-off-by: Furquan Shaikh <furquan(a)google.com> --- M src/soc/intel/cannonlake/Kconfig 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/22956/1 diff --git a/src/soc/intel/cannonlake/Kconfig b/src/soc/intel/cannonlake/Kconfig index beb812b..a7dfb22 100644 --- a/src/soc/intel/cannonlake/Kconfig +++ b/src/soc/intel/cannonlake/Kconfig @@ -52,7 +52,7 @@ select SOC_INTEL_COMMON_BLOCK_FAST_SPI select SOC_INTEL_COMMON_BLOCK_GPIO select SOC_INTEL_COMMON_BLOCK_GRAPHICS - select SOC_INTEL_COMMON_BLOCK_GSPI + select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2 select SOC_INTEL_COMMON_BLOCK_ITSS select SOC_INTEL_COMMON_BLOCK_I2C select SOC_INTEL_COMMON_BLOCK_LPC -- To view, visit https://review.coreboot.org/22956 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I40ebbb143b4618f83f454b9db2717589ba5ce99e Gerrit-Change-Number: 22956 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com>

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Change in coreboot[master]: mainboard/google/fizz: Enable S0ix
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22955 ) Change subject: mainboard/google/fizz: Enable S0ix ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19619/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64843/ : SUCCESS -- To view, visit https://review.coreboot.org/22955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Gerrit-Change-Number: 22955 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 18:57:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/fizz: Enable S0ix
by Shelley Chen (Code Review) 20 Dec '17

20 Dec '17

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/22955 Change subject: mainboard/google/fizz: Enable S0ix ...................................................................... mainboard/google/fizz: Enable S0ix Enable S0ix for fizz. BUG=b:67598361 BRANCH=None TEST=None. Need to be tested with EC and kernel as well. Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Signed-off-by: Shelley Chen <shchen(a)chromium.org> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/22955/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index 25eda89..6873d44 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -50,6 +50,9 @@ # Enable DPTF register "dptf_enable" = "1" + # Enable S0ix + register "s0ix_enable" = "1" + # FSP Configuration register "ProbelessTrace" = "0" register "EnableLan" = "1" -- To view, visit https://review.coreboot.org/22955 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I981d2cc7e969a44567b0f21f63f68c78e73f5cb5 Gerrit-Change-Number: 22955 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com>

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Change in coreboot[master]: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22954 ) Change subject: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19618/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64842/ : SUCCESS -- To view, visit https://review.coreboot.org/22954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Gerrit-Change-Number: 22954 Gerrit-PatchSet: 2 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 18:31:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22954 ) Change subject: soc/intel/gspi: Handle per-SoC differences in SPI_CS_CONTROL ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64841/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19617/ : SUCCESS -- To view, visit https://review.coreboot.org/22954 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic69321483a58bb29f939b0d8b37f33ca30eb53b8 Gerrit-Change-Number: 22954 Gerrit-PatchSet: 1 Gerrit-Owner: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 18:24:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017