coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: drivers/mrc_cache: Make bootstate for SPI writes variable
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22937 ) Change subject: drivers/mrc_cache: Make bootstate for SPI writes variable ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19599/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64822/ : SUCCESS -- To view, visit https://review.coreboot.org/22937 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie7ba9070829d98414ee788e14d1a768145d742ea Gerrit-Change-Number: 22937 Gerrit-PatchSet: 2 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 00:45:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: WIP soc/amd/common: Move LateInit earlier
by build bot (Jenkins) (Code Review) 20 Dec '17

20 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22952 ) Change subject: WIP soc/amd/common: Move LateInit earlier ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19600/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64823/ : SUCCESS -- To view, visit https://review.coreboot.org/22952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia00c7b53e010679f51bd7f78f67382941bac4b33 Gerrit-Change-Number: 22952 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 20 Dec 2017 00:33:22 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: intel/skylake: Perform lockdown in bootstate after MRC write
by Marshall Dawson (Code Review) 20 Dec '17

20 Dec '17

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/22939 ) Change subject: intel/skylake: Perform lockdown in bootstate after MRC write ...................................................................... Abandoned https://review.coreboot.org/#/c/coreboot/+/22937/ has been changed to do either early/late and the default is still early (unchanged). Since skylake doesn't select late, there is no point to adding more complexity to lockdown.c. -- To view, visit https://review.coreboot.org/22939 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: Ifa4eaba72defc403908fffe3d19dbd3e16e14622 Gerrit-Change-Number: 22939 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: intel/cannonlake: Perform lockdown in bootstate after MRC write
by Marshall Dawson (Code Review) 20 Dec '17

20 Dec '17

Marshall Dawson has abandoned this change. ( https://review.coreboot.org/22938 ) Change subject: intel/cannonlake: Perform lockdown in bootstate after MRC write ...................................................................... Abandoned https://review.coreboot.org/#/c/coreboot/+/22937/ has been changed to do either early/late and the default is still early (unchanged). Since cannonlake doesn't select late, there is no point to adding more complexity to lockdown.c. -- To view, visit https://review.coreboot.org/22938 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: abandon Gerrit-Change-Id: I7e8776e216e2be9ba54a97dbd79b840806e12469 Gerrit-Change-Number: 22938 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: WIP soc/amd/common: Move LateInit earlier
by Marshall Dawson (Code Review) 20 Dec '17

20 Dec '17

Marshall Dawson has posted comments on this change. ( https://review.coreboot.org/22952 ) Change subject: WIP soc/amd/common: Move LateInit earlier ...................................................................... Patch Set 1: (1 comment) https://review.coreboot.org/#/c/22952/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/22952/1//COMMIT_MSG@7 PS1, Line 7: WIP I'm not yet confident this is allowed or a solid idea. It moves the calls ahead of chip_ops.final() which calls southbridge_final() and fam15_finalize(). Perhaps another approach might be moving only the amdS3Save forward in time, but I don't know if there are any consequences to moving it ahead of amdinitlate. -- To view, visit https://review.coreboot.org/22952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ia00c7b53e010679f51bd7f78f67382941bac4b33 Gerrit-Change-Number: 22952 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Comment-Date: Wed, 20 Dec 2017 00:18:16 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: WIP soc/amd/common: Move LateInit earlier
by Marshall Dawson (Code Review) 20 Dec '17

20 Dec '17

Marshall Dawson has uploaded this change for review. ( https://review.coreboot.org/22952 Change subject: WIP soc/amd/common: Move LateInit earlier ...................................................................... WIP soc/amd/common: Move LateInit earlier Move agesawrapper_post_device() to the entry of BS_POST_DEVICE. A subsequent patch will use the new drivers/mrc_cache, and the latest it may write to flash is the exit of BS_POST_DEVICE. To ensure the S3 data is stashed in time, the calls are moved earlier. Change-Id: Ia00c7b53e010679f51bd7f78f67382941bac4b33 Signed-off-by: Marshall Dawson <marshalldawson3rd(a)gmail.com> --- M src/soc/amd/common/block/pi/amd_late_init.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/52/22952/1 diff --git a/src/soc/amd/common/block/pi/amd_late_init.c b/src/soc/amd/common/block/pi/amd_late_init.c index 3eb3674..5f4be93 100644 --- a/src/soc/amd/common/block/pi/amd_late_init.c +++ b/src/soc/amd/common/block/pi/amd_late_init.c @@ -36,5 +36,5 @@ do_agesawrapper(agesawrapper_amdS3Save, "amdS3Save"); } -BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_EXIT, +BOOT_STATE_INIT_ENTRY(BS_POST_DEVICE, BS_ON_ENTRY, agesawrapper_post_device, NULL); -- To view, visit https://review.coreboot.org/22952 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ia00c7b53e010679f51bd7f78f67382941bac4b33 Gerrit-Change-Number: 22952 Gerrit-PatchSet: 1 Gerrit-Owner: Marshall Dawson <marshalldawson3rd(a)gmail.com>

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Change in coreboot[master]: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS
by Arthur Heymans (Code Review) 19 Dec '17

19 Dec '17

Arthur Heymans has submitted this change and it was merged. ( https://review.coreboot.org/22929 ) Change subject: mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS ...................................................................... mb/hp/xxx0p: set ACPI and SLPT bit in _WAK and _PTS ACPI bit is not set after an S3 resume, so set it in _WAK. Setting SLPT bit can make the power LED blink in S3. Change-Id: I2badc69510275df57938cb8607b3c4e0df50f028 Signed-off-by: Iru Cai <mytbk920423(a)gmail.com> Reviewed-on: https://review.coreboot.org/22929 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/hp/2570p/acpi/platform.asl M src/mainboard/hp/2760p/acpi/platform.asl M src/mainboard/hp/8460p/acpi/platform.asl M src/mainboard/hp/8470p/acpi/platform.asl 4 files changed, 16 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Arthur Heymans: Looks good to me, approved diff --git a/src/mainboard/hp/2570p/acpi/platform.asl b/src/mainboard/hp/2570p/acpi/platform.asl index 79eddcb..fe0f936 100644 --- a/src/mainboard/hp/2570p/acpi/platform.asl +++ b/src/mainboard/hp/2570p/acpi/platform.asl @@ -15,9 +15,13 @@ Method(_WAK,1) { + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + Return(Package(){0,0}) } Method(_PTS,1) { + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 } diff --git a/src/mainboard/hp/2760p/acpi/platform.asl b/src/mainboard/hp/2760p/acpi/platform.asl index 79eddcb..fe0f936 100644 --- a/src/mainboard/hp/2760p/acpi/platform.asl +++ b/src/mainboard/hp/2760p/acpi/platform.asl @@ -15,9 +15,13 @@ Method(_WAK,1) { + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + Return(Package(){0,0}) } Method(_PTS,1) { + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 } diff --git a/src/mainboard/hp/8460p/acpi/platform.asl b/src/mainboard/hp/8460p/acpi/platform.asl index 79eddcb..fe0f936 100644 --- a/src/mainboard/hp/8460p/acpi/platform.asl +++ b/src/mainboard/hp/8460p/acpi/platform.asl @@ -15,9 +15,13 @@ Method(_WAK,1) { + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + Return(Package(){0,0}) } Method(_PTS,1) { + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 } diff --git a/src/mainboard/hp/8470p/acpi/platform.asl b/src/mainboard/hp/8470p/acpi/platform.asl index 79eddcb..fe0f936 100644 --- a/src/mainboard/hp/8470p/acpi/platform.asl +++ b/src/mainboard/hp/8470p/acpi/platform.asl @@ -15,9 +15,13 @@ Method(_WAK,1) { + \_SB.PCI0.LPCB.EC0.ACPI = 1 + \_SB.PCI0.LPCB.EC0.SLPT = 0 + Return(Package(){0,0}) } Method(_PTS,1) { + \_SB.PCI0.LPCB.EC0.SLPT = Arg0 } -- To view, visit https://review.coreboot.org/22929 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: merged Gerrit-Change-Id: I2badc69510275df57938cb8607b3c4e0df50f028 Gerrit-Change-Number: 22929 Gerrit-PatchSet: 2 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: soc/intel: Treat time-out as failure in HECI
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22910 ) Change subject: soc/intel: Treat time-out as failure in HECI ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19593/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64816/ : SUCCESS -- To view, visit https://review.coreboot.org/22910 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7c1655284d7027294d8ff5d6a5dbbebe4cbd0c47 Gerrit-Change-Number: 22910 Gerrit-PatchSet: 6 Gerrit-Owner: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Caveh Jalali <caveh(a)google.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.com> Gerrit-Reviewer: John Zhao <john.zhao(a)intel.corp-partner.google.com> Gerrit-Reviewer: Krzysztof M Sywula <krzysztof.m.sywula(a)intel.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 23:06:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel/cannonlake: provide LPDDR4 memory init
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22204 ) Change subject: soc/intel/cannonlake: provide LPDDR4 memory init ...................................................................... Patch Set 23: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64811/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19588/ : SUCCESS -- To view, visit https://review.coreboot.org/22204 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I4a43ea121e663b866eaca3930eca61f30bb52834 Gerrit-Change-Number: 22204 Gerrit-PatchSet: 23 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Anonymous Coward #1001775 Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Lijian Zhao <lijian.zhao(a)intel.com> Gerrit-Reviewer: Maximilian Schander <coreboot(a)mimoja.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 20:46:26 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/google/zoombini/variants/meowth: add new board
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22401 ) Change subject: mainboard/google/zoombini/variants/meowth: add new board ...................................................................... Patch Set 10: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64813/ : FAILURE https://qa.coreboot.org/job/coreboot-checkpatch/19590/ : SUCCESS -- To view, visit https://review.coreboot.org/22401 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ie6ed7ebb4a00a87fc93fc694d74c08a716380a54 Gerrit-Change-Number: 22401 Gerrit-PatchSet: 10 Gerrit-Owner: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)gmail.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 20:45:44 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017