coreboot-gerrit December 2017

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Change in coreboot[master]: soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init()
by Richard Spiegel (Code Review) 19 Dec '17

19 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22948 Change subject: soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init() ...................................................................... soc/amd/stoneyridge/chip.c: Move setup_bsp_ramtop to soc_init() Issue first reported at commit 1587dc8a2b, the call of functions setup_bsp_ramtop() and setup_uma_memory() should be moved from enable_dev() to soc_init(). The function setup_uma_memory() no longer exists, its functionality transfered to agesawrapper_amdinitpost. Move setup_bsp_ramtop() as required. BUG=b:62240756 TEST=Build and boot kahlee. Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/stoneyridge/chip.c 1 file changed, 7 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/48/22948/1 diff --git a/src/soc/amd/stoneyridge/chip.c b/src/soc/amd/stoneyridge/chip.c index 2602be5..87f3e15 100644 --- a/src/soc/amd/stoneyridge/chip.c +++ b/src/soc/amd/stoneyridge/chip.c @@ -45,13 +45,6 @@ static void enable_dev(device_t dev) { - static int done = 0; - - if (!done) { - setup_bsp_ramtop(); - done = 1; - } - /* Set the operations if it is a special bus type */ if (dev->path.type == DEVICE_PATH_DOMAIN) dev->ops = &pci_domain_ops; @@ -63,7 +56,14 @@ static void soc_init(void *chip_info) { + static int done = 0; + southbridge_init(chip_info); + if (!done) { + setup_bsp_ramtop(); + done = 1; + } + } static void soc_final(void *chip_info) -- To view, visit https://review.coreboot.org/22948 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I44e6cab17a8f7f364fc57657f41b211ec9d17641 Gerrit-Change-Number: 22948 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: ic2/designware: Move Intel i2c logic to shared driver
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22822 ) Change subject: ic2/designware: Move Intel i2c logic to shared driver ...................................................................... Patch Set 5: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64801/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19578/ : SUCCESS -- To view, visit https://review.coreboot.org/22822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Gerrit-Change-Number: 22822 Gerrit-PatchSet: 5 Gerrit-Owner: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 16:53:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ic2/designware: Move Intel i2c logic to shared driver
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22822 ) Change subject: ic2/designware: Move Intel i2c logic to shared driver ...................................................................... Patch Set 4: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64800/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19577/ : SUCCESS -- To view, visit https://review.coreboot.org/22822 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Idb453a4d2411163e6b4a8422310bf272eac5d379 Gerrit-Change-Number: 22822 Gerrit-PatchSet: 4 Gerrit-Owner: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Chris Ching <chingcodes(a)chromium.org> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 16:43:13 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/mrc_cache: only add mrc.cache when CACHE_MRC_SETTINGS is set
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22925 ) Change subject: drivers/mrc_cache: only add mrc.cache when CACHE_MRC_SETTINGS is set ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19575/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64798/ : SUCCESS -- To view, visit https://review.coreboot.org/22925 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iab3ac87e43408ef51f0158f319eb1c8ccfce8a55 Gerrit-Change-Number: 22925 Gerrit-PatchSet: 4 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Subrata Banik <subrata.banik(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 16:14:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update. ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19574/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64797/ : SUCCESS -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 1 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 15:13:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.
by Furquan Shaikh (Code Review) 19 Dec '17

19 Dec '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22947 ) Change subject: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update. ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/22947/1//COMMIT_MSG Commit Message: https://review.coreboot.org/#/c/22947/1//COMMIT_MSG@7 PS1, Line 7: soc/intel soc/intel/skylake https://review.coreboot.org/#/c/22947/1//COMMIT_MSG@14 PS1, Line 14: CL:22629,CL:22899 What CLs are these? I was not able to find anything relevant. https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip.h File src/soc/intel/skylake/chip.h: https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip.h@202 PS1, Line 202: u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; Can you please add a comment indicating what this config option does and what values it can be set to? https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip_fsp20.c File src/soc/intel/skylake/chip_fsp20.c: https://review.coreboot.org/#/c/22947/1/src/soc/intel/skylake/chip_fsp20.c@… PS1, Line 174: 0x1F What does this value mean? Can you please add a comment? -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 1 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Comment-Date: Tue, 19 Dec 2017 15:13:06 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update.
by Divya Chellappa (Code Review) 19 Dec '17

19 Dec '17

Divya Chellappa has uploaded this change for review. ( https://review.coreboot.org/22947 Change subject: soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update. ...................................................................... soc/intel: Update on KBL SoC w.r.t FSP V2.9.2 update. There is a new UPD PcieRpClkSrcNumber introduced in FSP V2.9.2 to configure clock source(s) of PCIe Root Ports. This UPD is used to disable clock source(s) of disabled PCIe Root Port which has active device connected. CQ-DEPEND=CL:22629,CL:22899 BUG=b:70252901 BRANCH=None TEST= Performed the following 1. Build and boot soraka 2. Verified PCIe devices list using lspci 3. FULL BAT on soraka Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Signed-off-by: Divya Chellap <divya.chellappa(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 10 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/47/22947/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 8540e21..64371ca 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -199,6 +199,8 @@ */ u8 PcieRpClkReqNumber[CONFIG_MAX_ROOT_PORTS]; + u8 PcieRpClkSrcNumber[CONFIG_MAX_ROOT_PORTS]; + /* * Enable/Disable AER (Advanced Error Reporting) for Root Port * 0: Disable AER diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 96c3b60..be60bfa 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -166,6 +166,14 @@ memcpy(params->PcieRpLtrEnable, config->PcieRpLtrEnable, sizeof(params->PcieRpLtrEnable)); + for (i = 0; i < CONFIG_MAX_ROOT_PORTS; i++) + { + if (config->PcieRpClkReqSupport[i]) + params->PcieRpClkSrcNumber[i] = config->PcieRpClkSrcNumber[i]; + else + params->PcieRpClkSrcNumber[i] = 0x1F; + } + /* disable Legacy PME */ memset(params->PcieRpPmSci, 0, sizeof(params->PcieRpPmSci)); -- To view, visit https://review.coreboot.org/22947 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I95ca0d893338100b7e4d7d0b76c076ed7e2b040e Gerrit-Change-Number: 22947 Gerrit-PatchSet: 1 Gerrit-Owner: Divya Chellappa <divya.chellappa(a)intel.com>

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Change in coreboot[master]: google/kahlee: Create mainboard_pirq_data
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22940 ) Change subject: google/kahlee: Create mainboard_pirq_data ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19572/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64795/ : SUCCESS -- To view, visit https://review.coreboot.org/22940 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: If07d2f54f06f6cf77566c43eddc8ee8a314e7a3a Gerrit-Change-Number: 22940 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 14:54:31 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add Dell Inspiron 660s
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22682 ) Change subject: mainboard: Add Dell Inspiron 660s ...................................................................... Patch Set 9: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64794/ : FAILURE -- To view, visit https://review.coreboot.org/22682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Gerrit-Change-Number: 22682 Gerrit-PatchSet: 9 Gerrit-Owner: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 12:01:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard: Add Dell Inspiron 660s
by build bot (Jenkins) (Code Review) 19 Dec '17

19 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22682 ) Change subject: mainboard: Add Dell Inspiron 660s ...................................................................... Patch Set 8: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64793/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19571/ : SUCCESS -- To view, visit https://review.coreboot.org/22682 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8dabb1e1d14e60957e8c8800b0c30921d6bb5d8e Gerrit-Change-Number: 22682 Gerrit-PatchSet: 8 Gerrit-Owner: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Jean Lucas <jean(a)4ray.co> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: Vladimir Serbinenko <phcoder(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 19 Dec 2017 12:01:00 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017