coreboot-gerrit December 2017

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Change in coreboot[master]: nb/intel/x4x: Add a convenient macro to loop over bytelanes
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22347 ) Change subject: nb/intel/x4x: Add a convenient macro to loop over bytelanes ...................................................................... Patch Set 4: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19744/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64986/ : SUCCESS -- To view, visit https://review.coreboot.org/22347 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ib9a30ffabaf5c845e962e3e79cf4a20faa1d9857 Gerrit-Change-Number: 22347 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 12:01:51 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Use SPI flash to cache raminit results
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/21677 ) Change subject: nb/intel/x4x: Use SPI flash to cache raminit results ...................................................................... Patch Set 15: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19743/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64985/ : SUCCESS -- To view, visit https://review.coreboot.org/21677 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I042dc5c52615d40781d9ef7ecd657ad0bf3ed08f Gerrit-Change-Number: 21677 Gerrit-PatchSet: 15 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Idwer Vollering <vidwer(a)gmail.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 11:59:42 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/lenovo/x200/dock.asl: Issue DOCK ACPI events based on Dock ID
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22919 ) Change subject: mb/lenovo/x200/dock.asl: Issue DOCK ACPI events based on Dock ID ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19740/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64982/ : SUCCESS -- To view, visit https://review.coreboot.org/22919 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1eef971d49508bcd94d5d1cf2b70395b7cd80b1c Gerrit-Change-Number: 22919 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 11:13:59 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22982 ) Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19739/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64981/ : SUCCESS -- To view, visit https://review.coreboot.org/22982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Gerrit-Change-Number: 22982 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 10:51:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22982 ) Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ...................................................................... Patch Set 2: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64980/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19738/ : SUCCESS -- To view, visit https://review.coreboot.org/22982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Gerrit-Change-Number: 22982 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 10:24:03 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22982 ) Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ...................................................................... Patch Set 1: Verified-1 Build Failed https://qa.coreboot.org/job/coreboot-gerrit/64979/ : ABORTED https://qa.coreboot.org/job/coreboot-checkpatch/19737/ : SUCCESS -- To view, visit https://review.coreboot.org/22982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Gerrit-Change-Number: 22982 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 09:53:01 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
by Arthur Heymans (Code Review) 24 Dec '17

24 Dec '17

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/22982 ) Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ...................................................................... [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c 3 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22982/2 -- To view, visit https://review.coreboot.org/22982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Gerrit-Change-Number: 22982 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions
by Arthur Heymans (Code Review) 24 Dec '17

24 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22982 Change subject: [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions ...................................................................... [UNTESTED]nb/intel/sandybridge: Use common mrc cache functions This uses the functions in include/mrc_cache.h instead of northbidge/intel/common/mrc_cache.h Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/sandybridge/Kconfig M src/northbridge/intel/sandybridge/Makefile.inc M src/northbridge/intel/sandybridge/raminit.c 3 files changed, 12 insertions(+), 20 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/82/22982/1 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index 043e8de..a1f21a2 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -16,7 +16,7 @@ config NORTHBRIDGE_INTEL_SANDYBRIDGE bool - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select CPU_INTEL_MODEL_206AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI @@ -24,7 +24,7 @@ config NORTHBRIDGE_INTEL_IVYBRIDGE bool - select NORTHBRIDGE_INTEL_COMMON_MRC_CACHE + select CACHE_MRC_SETTINGS select CPU_INTEL_MODEL_306AX select HAVE_DEBUG_RAM_SETUP select INTEL_GMA_ACPI diff --git a/src/northbridge/intel/sandybridge/Makefile.inc b/src/northbridge/intel/sandybridge/Makefile.inc index 846d31b..1470353 100644 --- a/src/northbridge/intel/sandybridge/Makefile.inc +++ b/src/northbridge/intel/sandybridge/Makefile.inc @@ -45,16 +45,4 @@ smm-$(CONFIG_HAVE_SMI_HANDLER) += finalize.c -ifneq ($(CONFIG_CHROMEOS),y) -$(obj)/mrc.cache: $(obj)/config.h - dd if=/dev/zero count=1 \ - bs=$(shell printf "%d" $(CONFIG_MRC_CACHE_SIZE) ) | \ - tr '\000' '\377' > $@ - -cbfs-files-y += mrc.cache -mrc.cache-file := $(obj)/mrc.cache -mrc.cache-align := 0x10000 -mrc.cache-type := mrc_cache -endif - endif diff --git a/src/northbridge/intel/sandybridge/raminit.c b/src/northbridge/intel/sandybridge/raminit.c index 12384b4..4ec1adf 100644 --- a/src/northbridge/intel/sandybridge/raminit.c +++ b/src/northbridge/intel/sandybridge/raminit.c @@ -23,7 +23,7 @@ #include <cbmem.h> #include <halt.h> #include <timestamp.h> -#include <northbridge/intel/common/mrc_cache.h> +#include <mrc_cache.h> #include <southbridge/intel/bd82x6x/me.h> #include <southbridge/intel/common/smbus.h> #include <cpu/x86/msr.h> @@ -35,6 +35,8 @@ #include "raminit_common.h" #include "sandybridge.h" +#define MRC_CACHE_VERSION 0 + /* FIXME: no ECC support. */ /* FIXME: no support for 3-channel chipsets. */ @@ -292,7 +294,8 @@ static void save_timings(ramctr_timing *ctrl) { /* Save the MRC S3 restore data to cbmem */ - store_current_mrc_cache(ctrl, sizeof(*ctrl)); + mrc_cache_stash_data(MRC_TRAINING_DATA, MRC_CACHE_VERSION, ctrl, + sizeof(*ctrl)); } static int try_init_dram_ddr3(ramctr_timing *ctrl, int fast_boot, @@ -311,7 +314,7 @@ ramctr_timing ctrl; int fast_boot; spd_raw_data spds[4]; - struct mrc_data_container *mrc_cache; + struct region_device rdev; ramctr_timing *ctrl_cached; struct cpuid_result cpures; int err; @@ -347,8 +350,9 @@ early_thermal_init(); /* try to find timings in MRC cache */ - mrc_cache = find_current_mrc_cache(); - if (!mrc_cache || (mrc_cache->mrc_data_size < sizeof(ctrl))) { + int cache_not_found = mrc_cache_get_current(MRC_TRAINING_DATA, MRC_CACHE_VERSION, + &rdev); + if (cache_not_found || (region_device_sz(&rdev) < sizeof(ctrl))) { if (s3resume) { /* Failed S3 resume, reset to come up cleanly */ outb(0x6, 0xcf9); @@ -356,7 +360,7 @@ } ctrl_cached = NULL; } else { - ctrl_cached = (ramctr_timing *)mrc_cache->mrc_data; + ctrl_cached = rdev_mmap_full(&rdev); } /* verify MRC cache for fast boot */ -- To view, visit https://review.coreboot.org/22982 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I46002c0b19a55d855286eb8b0ca934ef7ca7fe09 Gerrit-Change-Number: 22982 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: sb/intel/i82801{g, j}x: Automatically generate ACPI PIRQ tables
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22981 ) Change subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19736/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64978/ : SUCCESS -- To view, visit https://review.coreboot.org/22981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Gerrit-Change-Number: 22981 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 08:23:08 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: sb/intel/i82801{g, j}x: Automatically generate ACPI PIRQ tables
by Arthur Heymans (Code Review) 24 Dec '17

24 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22981 to look at the new patch set (#3). Change subject: sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables ...................................................................... sb/intel/i82801{g,j}x: Automatically generate ACPI PIRQ tables Both southbridges need to be done at once since this southbridge code is used for different northbridges, which fails to compile when done separately. This needs an acpi_name functions in the northbridge code to be defined. Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/apple/macbook21/acpi/i945_pci_irqs.asl D src/mainboard/asrock/g41c-gs/acpi/x4x_pci_irqs.asl D src/mainboard/asus/p5gc-mx/acpi/i945_pci_irqs.asl D src/mainboard/foxconn/g41s-k/acpi/x4x_pci_irqs.asl D src/mainboard/getac/p470/acpi/i945_pci_irqs.asl D src/mainboard/gigabyte/ga-945gcm-s2l/acpi/i945_pci_irqs.asl D src/mainboard/gigabyte/ga-g41m-es2l/acpi/x4x_pci_irqs.asl D src/mainboard/ibase/mb899/acpi/i945_pci_irqs.asl D src/mainboard/intel/d510mo/acpi/pineview_pci_irqs.asl D src/mainboard/intel/d945gclf/acpi/i945_pci_irqs.asl D src/mainboard/intel/dg43gt/acpi/x4x_pci_irqs.asl D src/mainboard/kontron/986lcd-m/acpi/i945_pci_irqs.asl D src/mainboard/lenovo/t60/acpi/i945_pci_irqs.asl D src/mainboard/lenovo/x60/acpi/i945_pci_irqs.asl D src/mainboard/lenovo/z61t/acpi/i945_pci_irqs.asl D src/mainboard/roda/rk886ex/acpi/i945_pci_irqs.asl M src/northbridge/intel/i945/acpi/hostbridge.asl M src/northbridge/intel/i945/northbridge.c M src/northbridge/intel/pineview/acpi/hostbridge.asl M src/northbridge/intel/pineview/northbridge.c M src/northbridge/intel/x4x/acpi/hostbridge.asl M src/northbridge/intel/x4x/northbridge.c M src/southbridge/intel/i82801gx/Kconfig M src/southbridge/intel/i82801gx/i82801gx.h M src/southbridge/intel/i82801gx/lpc.c M src/southbridge/intel/i82801jx/Kconfig M src/southbridge/intel/i82801jx/i82801jx.h M src/southbridge/intel/i82801jx/lpc.c 28 files changed, 86 insertions(+), 1,191 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/22981/3 -- To view, visit https://review.coreboot.org/22981 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I286d251ddf8fcae27dd07011a1cd62d8f4847683 Gerrit-Change-Number: 22981 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2017