coreboot-gerrit December 2017

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Change in coreboot[master]: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22989 Change subject: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset ...................................................................... google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/BiosCallOuts.c M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/stoneyridge/BiosCallOuts.c 3 files changed, 0 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/22989/1 diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index fafe0aa..2ed1843 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -19,10 +19,6 @@ #include <stdlib.h> #include <baseboard/variants.h> -void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) -{ -} - void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { /* SDHCI/MMC configuration */ diff --git a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h index 2302889..c8c5607 100644 --- a/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h +++ b/src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h @@ -59,7 +59,6 @@ AGESA_STATUS agesa_fch_initreset(UINT32 Func, UINTN FchData, VOID *ConfigPtr); AGESA_STATUS agesa_fch_initenv(UINT32 Func, UINTN FchData, VOID *ConfigPtr); -void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset); void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env); void oem_fan_control(FCH_DATA_BLOCK *FchParams); AGESA_STATUS platform_PcieSlotResetControl(UINT32 Func, UINTN Data, diff --git a/src/soc/amd/stoneyridge/BiosCallOuts.c b/src/soc/amd/stoneyridge/BiosCallOuts.c index f6ac187..5ec1449 100644 --- a/src/soc/amd/stoneyridge/BiosCallOuts.c +++ b/src/soc/amd/stoneyridge/BiosCallOuts.c @@ -38,9 +38,6 @@ FchParams_reset->FchReset.SataEnable = sb_sata_enable(); FchParams_reset->FchReset.IdeEnable = sb_ide_enable(); - /* Get platform specific configuration changes */ - platform_FchParams_reset(FchParams_reset); - printk(BIOS_DEBUG, "Done\n"); } -- To view, visit https://review.coreboot.org/22989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Gerrit-Change-Number: 22989 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO table
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22988 Change subject: google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO table ...................................................................... google/kahlee/variants/(kahlee/baseboard)/gpio.c: Convert GPIO table Fill up the dummy gpio_set_stage[] with data from agesa_board_gpios[], convert format and delete agesa_board_gpios[] and get_gpio_table(). Then remove the get_gpio_table() call from BiosCallOuts.c. Finally, remove get_gpio_table() from google/kahlee/variants/baseboard/include/baseboard/variants.h. BUG=b:64140392 TEST=Build grunt. Build and boot kahlee, recording serial output. Search for "Stage reset" and "Stage init late"; verify that GPIO are programmed at the correct stage. As only bits 23-17 are changed by the program, verify that occasionally some other bits are set, indicating that it's actually a register read back after being programed. Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/BiosCallOuts.c M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/kahlee/variants/kahlee/gpio.c 4 files changed, 95 insertions(+), 134 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/22988/1 diff --git a/src/mainboard/google/kahlee/BiosCallOuts.c b/src/mainboard/google/kahlee/BiosCallOuts.c index 1c0df4d..fafe0aa 100644 --- a/src/mainboard/google/kahlee/BiosCallOuts.c +++ b/src/mainboard/google/kahlee/BiosCallOuts.c @@ -21,13 +21,10 @@ void platform_FchParams_reset(FCH_RESET_DATA_BLOCK *FchParams_reset) { - FchParams_reset->EarlyOemGpioTable = (void *)get_gpio_table(); } void platform_FchParams_env(FCH_DATA_BLOCK *FchParams_env) { - FchParams_env->PostOemGpioTable = (void *)get_gpio_table(); - /* SDHCI/MMC configuration */ if (IS_ENABLED(CONFIG_BOARD_GOOGLE_KAHLEE)) FchParams_env->Sd.SdSlotType = 1; // EMMC diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 35b35d1..79de6eb 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -41,141 +41,132 @@ const static struct soc_amd_stoneyridge_gpio gpio_set_stage[] = { /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ - { GPIO_0, Function0, PULL_UP | INPUT, STAGE_RESET } -}; - -/* - * These settings were generated by a spreadsheet. If they need to be updated, - * update the spreadsheet shared with the Grunt development team. - */ -static const GPIO_CONTROL agesa_board_gpios[] = { - - /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ - { GPIO_0, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_0, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_1 - SYS_RST_ODL */ - { GPIO_1, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_1, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_2 - WLAN_PCIE_WAKE_3V3_ODL */ - { GPIO_2, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_2, Function0, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_3 - MEM_VOLT_SEL */ - { GPIO_3, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_3, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_4 - EN_PP3300_WLAN */ - { GPIO_4, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_4, Function0, OUTPUT_H, STAGE_INIT_LATE }, /* GPIO_5 - PCH_TRACKPAD_INT_3V3_ODL, SCI */ - { GPIO_5, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_5, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_6 - APU_RST_L / EC_SMI_ODL, SMI */ - { GPIO_6, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_6, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_7 - APU_PWROK_OD (currently not used) */ - { GPIO_7, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_7, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_8 - DDR_ALERT_3V3_L (currently not used) */ - { GPIO_8, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_8, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_9 - H1_PCH_INT_ODL, SCI */ - { GPIO_9, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_9, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_10 - SLP_S0_L (currently not used) */ - { GPIO_10, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_10, Function0, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_11 - TOUCHSCREEN_INT_3V3_ODL, SCI */ - { GPIO_11, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_11, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_12 - Unused (TP126) */ - { GPIO_12, Function2, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_12, Function2, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_13 - APU_PEN_PDCT_ODL (currently not used) */ - { GPIO_13, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_13, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_14 - APU_HP_INT_ODL, SCI */ - { GPIO_14, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_14, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_15 - EC_IN_RW_OD */ - { GPIO_15, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_15, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_16 - USB_C0_OC_L */ - { GPIO_16, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_16, Function0, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_17 - USB_C1_OC_L */ - { GPIO_17, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_17, Function0, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_18 - USB_A0_OC_ODL */ - { GPIO_18, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_18, Function0, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_19 - APU_I2C_SCL3 (Touchscreen) */ - { GPIO_19, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_19, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_20 - APU_I2C_SDA3 (Touchscreen) */ - { GPIO_20, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_20, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_21 - APU_PEN_INT_ODL, SCI */ - { GPIO_21, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_21, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_22 - EC_SCI_ODL, SCI */ - { GPIO_22, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_22, Function1, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_23 - ACOK_OD */ + /* GPIO_24 - USB_A1_OC_ODL */ - { GPIO_24, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_24, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_25 - SD_CD */ - { GPIO_25, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_25, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_26 - APU_PCIE_RST_L */ - { GPIO_26, Function0, }, + { GPIO_26, Function0, INPUT, STAGE_RESET }, /* GPIO_40 - EMMC_BRIDGE_RST_L */ - { GPIO_40, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_40, Function0, OUTPUT_H, STAGE_RESET }, /* GPIO_42 - S5_MUX_CTRL */ - { GPIO_42, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_42, Function0, OUTPUT_H, STAGE_RESET }, /* GPIO_67 - PEN_RESET */ - { GPIO_67, Function0, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_67, Function0, FCH_GPIO_OUTPUT_VALUE, STAGE_INIT_LATE }, /* GPIO_70 - WLAN_PE_RST_L */ - { GPIO_70, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_70, Function0, OUTPUT_H, STAGE_INIT_LATE }, /* GPIO_74 - LPC_CLK0_EC_R */ - { GPIO_74, Function0, FCH_GPIO_PULL_DOWN_ENABLE }, + { GPIO_74, Function0, PULL_DOWN | INPUT, STAGE_RESET }, /* GPIO_75 - Unused (strap) (R139/R130) */ - { GPIO_75, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_75, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_76 - EN_PP3300_TOUCHSCREEN */ - { GPIO_76, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_76, Function0, OUTPUT_H, STAGE_INIT_LATE }, /* GPIO_84 - HUB_RST (Active High) */ - { GPIO_84, Function1, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_84, Function1, FCH_GPIO_OUTPUT_VALUE, STAGE_RESET }, /* GPIO_85 - TOUCHSCREEN_RST (Active High) */ - { GPIO_85, Function1, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_85, Function1, FCH_GPIO_OUTPUT_VALUE, STAGE_RESET }, /* GPIO_86 - Unused (TP109) */ - { GPIO_86, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_86, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_87 - LPC_SERIRQ */ - { GPIO_87, Function0, }, + { GPIO_87, Function0, INPUT, STAGE_RESET }, /* GPIO_88 - LPC_CLKRUN_L */ - { GPIO_88, Function0, }, + { GPIO_88, Function0, INPUT, STAGE_RESET }, /* GPIO_90 - EN_PP3300_CAMERA */ - { GPIO_90, Function0, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_90, Function0, OUTPUT_H, STAGE_INIT_LATE }, /* GPIO_91 - EN_PP3300_TRACKPAD */ - { GPIO_91, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_91, Function1, OUTPUT_H, STAGE_INIT_LATE }, /* GPIO_92 - WLAN_PCIE_CLKREQ_3V3_ODL */ - { GPIO_92, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_92, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_93 - EMMC_RST_L */ - { GPIO_93, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_93, Function1, OUTPUT_H, STAGE_RESET }, /* GPIO_95 - SD_CLK */ /* GPIO_96 - SD_CMD */ @@ -185,105 +176,98 @@ /* GPIO_100 - SD_D3 */ /* GPIO_101 - SD_WP_L */ - { GPIO_101, Function0, FCH_GPIO_PULL_DOWN_ENABLE }, + { GPIO_101, Function0, PULL_DOWN | INPUT, STAGE_RESET }, /* GPIO_102 - EN_SD_SOCKET_PWR */ - { GPIO_102, Function0, FCH_GPIO_PULL_DOWN_ENABLE }, + { GPIO_102, Function0, PULL_DOWN | INPUT, STAGE_INIT_LATE }, /* GPIO_113 - APU_I2C_SCL2 (Pen & Trackpad) */ - { GPIO_113, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_113, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_114 - APU_I2C_SDA2 (Pen & Trackpad) */ - { GPIO_114, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_114, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_115 - Unused (TP127) */ - { GPIO_115, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_115, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_116 - PCIE_EMMC_CLKREQ_L */ - { GPIO_116, Function0, }, + { GPIO_116, Function0, INPUT, STAGE_RESET }, /* GPIO_117 - PCH_SPI_CLK_R */ /* GPIO_118 - PCH_SPI_CS0_L */ - { GPIO_118, Function0, }, + { GPIO_118, Function0, INPUT, STAGE_RESET }, /* GPIO_119 - SPK_PA_EN */ - { GPIO_119, Function2, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_119, Function2, OUTPUT_H, STAGE_RESET }, /* GPIO_120 - PCH_SPI_MISO */ /* GPIO_121 - PCH_SPI_MOSI */ /* GPIO_122 - APU_BIOS_FLASH_WP_L */ - { GPIO_122, Function1, }, + { GPIO_122, Function1, INPUT, STAGE_RESET }, /* GPIO_126 - DMIC_CLK2_EN */ - { GPIO_126, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_126, Function1, OUTPUT_H, STAGE_RESET }, /* GPIO_129 - APU_KBRST_L */ - { GPIO_129, Function0, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_129, Function0, PULL_UP | INPUT, STAGE_RESET }, /* GPIO_130 - Unused (TP55) */ - { GPIO_130, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_130, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_131 - CONFIG_STRAP3 */ - { GPIO_131, Function3, }, + { GPIO_131, Function3, INPUT, STAGE_RESET }, /* GPIO_132 - CONFIG_STRAP4 */ - { GPIO_132, Function2, }, + { GPIO_132, Function2, INPUT, STAGE_RESET }, /* GPIO_133 - APU_EDP_BKLTEN_L (backlight - Active LOW) */ - { GPIO_133, Function1, FCH_GPIO_OUTPUT_VALUE }, + { GPIO_133, Function1, FCH_GPIO_OUTPUT_VALUE, STAGE_RESET }, /* GPIO_135 - Unused (TP128) */ - { GPIO_135, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_135, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* GPIO_136 - UART_PCH_RX_DEBUG_TX */ - { GPIO_136, Function0, }, + { GPIO_136, Function0, INPUT, STAGE_RESET }, /* GPIO_137 - AUDIO_CLK_EN (Remove in EVT?) */ - { GPIO_137, Function1, FCH_GPIO_OUTPUT_VALUE | FCH_GPIO_OUTPUT_ENABLE }, + { GPIO_137, Function1, OUTPUT_H, STAGE_RESET }, /* GPIO_138 - UART_PCH_TX_DEBUG_RX */ - { GPIO_138, Function0, }, + { GPIO_138, Function0, INPUT, STAGE_RESET }, /* GPIO_139 - CONFIG_STRAP1 */ - { GPIO_139, Function1, }, + { GPIO_139, Function1, INPUT, STAGE_RESET }, /* GPIO_140 - I2S_BCLK_R (init to func0, used for I2S) */ - { GPIO_140, Function0, }, + { GPIO_140, Function0, INPUT, STAGE_RESET }, /* GPIO_141 - I2S2_DATA_MIC2 (init to func0, used for I2S) */ - { GPIO_141, Function0, }, + { GPIO_141, Function0, INPUT, STAGE_RESET }, /* GPIO_142 - CONFIG_STRAP2 */ - { GPIO_142, Function1, }, + { GPIO_142, Function1, INPUT, STAGE_RESET }, /* GPIO_143 - I2S2_DATA (init to func0, used for I2S) */ - { GPIO_143, Function0, }, + { GPIO_143, Function0, INPUT, STAGE_RESET }, /* GPIO_144 - I2S_LR_R (init to func0, used for I2S) */ - { GPIO_144, Function0, }, + { GPIO_144, Function0, INPUT, STAGE_RESET }, /* GPIO_145 - PCH_I2C_AUDIO_SCL */ - { GPIO_145, Function0, }, + { GPIO_145, Function0, INPUT, STAGE_RESET }, /* GPIO_146 - PCH_I2C_AUDIO_SDA */ - { GPIO_146, Function0, }, + { GPIO_146, Function0, INPUT, STAGE_RESET }, /* GPIO_147 - PCH_I2C_HUB_SCL */ - { GPIO_147, Function0, }, + { GPIO_147, Function0, INPUT, STAGE_RESET }, /* GPIO_148 - PCH_I2C_HUB_SDA */ - { GPIO_148, Function0, }, - - {-1} + { GPIO_148, Function0, INPUT, STAGE_RESET }, }; -const __attribute__((weak)) GPIO_CONTROL *get_gpio_table(void) -{ - return agesa_board_gpios; -} - const __attribute__((weak)) const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) { diff --git a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h index 9c54794..bf14ef4 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/kahlee/variants/baseboard/include/baseboard/variants.h @@ -21,7 +21,6 @@ #include <soc/smi.h> #include <amdblocks/agesawrapper.h> -const GPIO_CONTROL *get_gpio_table(void); const struct sci_source *get_gpe_table(size_t *num); uint8_t variant_memory_sku(void); int variant_mainboard_read_spd(uint8_t spdAddress, char *buf, size_t len); diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index 8d76ee9..8eceb24 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -37,93 +37,74 @@ */ const struct soc_amd_stoneyridge_gpio gpio_set_stage[] = { /* AGPIO2, to become event generator */ - { GPIO_2, Function1, PULL_UP | INPUT, STAGE_RESET } -}; + { GPIO_2, Function1, PULL_UP | INPUT, STAGE_RESET }, -static const GPIO_CONTROL agesa_board_gpios[] = { - /* AGPIO2 PCIE/WLAN WAKE# SCI*/ - {2, Function1, FCH_GPIO_PULL_UP_ENABLE }, + /* SER_TX */ + { GPIO_8, Function1, PULL_UP | OUTPUT_H, STAGE_RESET }, - /* SER TX */ - {8, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, /* SER RX */ - {9, Function1, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_9, Function1, PULL_UP | INPUT, STAGE_RESET }, /* AGPIO 12 */ - {12, Function2, FCH_GPIO_PULL_UP_ENABLE }, + { GPIO_12, Function2, PULL_UP | INPUT, STAGE_INIT_LATE }, /* TS_EN_SOC (TouchScreen enable GPIO) */ - {13, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_13, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* CAM_PWRON (Camera enable GPIO) */ - {14, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_14, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* EC_IN_RW */ - {15, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_15, Function1, PULL_UP | INPUT, STAGE_RESET }, /* APU_I2C_3_SCL */ - {19, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_19, Function1, PULL_UP | INPUT, STAGE_RESET }, /* APU_I2C_3_SDA */ - {20, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_20, Function1, PULL_UP | INPUT, STAGE_RESET }, /* AGPIO22 EC_SCI */ - {22, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_22, Function1, PULL_UP | INPUT, STAGE_RESET }, /* APU_BT_ON# */ - {24, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_24, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* DEVSLP1_SSD */ - {67, Function1, FCH_GPIO_PULL_UP_ENABLE}, + {67, Function1, PULL_UP | INPUT, STAGE_INIT_LATE }, /* DEVSLP1_EMMC */ /* No Connect for now. - * {70, Function1, FCH_GPIO_PULL_UP_ENABLE}, + * {GPIO_70, Function1, PULL_UP | INPUT, STAGE_INIT_LATE}, */ /* SPI_TPM_CS_L */ - {76, Function1, FCH_GPIO_PULL_DOWN_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_76, Function1, PULL_DOWN | OUTPUT_H, STAGE_RESET }, /* CAM_LED# */ - {84, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_84, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* TS_RST# (TouchScreen Reset) */ - {85, Function1, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_85, Function1, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* WLAN_RST#_AUX */ - {119, Function2, FCH_GPIO_PULL_UP_ENABLE | FCH_GPIO_OUTPUT_VALUE - | FCH_GPIO_OUTPUT_ENABLE}, + {GPIO_119, Function2, PULL_UP | OUTPUT_H, STAGE_INIT_LATE }, /* BD_ID1 */ - {135, Function1, 0 }, + {GPIO_135, Function1, INPUT, STAGE_RESET }, /* TPM_SERIRQ# */ - {139, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_139, Function1, PULL_UP | INPUT, STAGE_RESET }, /* BD_ID2 */ - {140, Function1, 0 }, + {GPIO_140, Function1, INPUT, STAGE_RESET }, /* APU_SPI_WP */ - {142, Function1, FCH_GPIO_PULL_UP_ENABLE }, + {GPIO_142, Function1, PULL_UP | INPUT, STAGE_RESET }, /* BD_ID3 */ - {144, Function1, 0 }, - - {-1} + {GPIO_144, Function1, INPUT, STAGE_RESET } }; -const GPIO_CONTROL *get_gpio_table(void) -{ - return agesa_board_gpios; -} - const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) { *size = ARRAY_SIZE(gpio_set_stage); -- To view, visit https://review.coreboot.org/22988 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I88bf2c855105a6bc458aedfc6da7725662695667 Gerrit-Change-Number: 22988 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/common/block/pi/agesawrapper.c: Add new function sb_program_g...
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22987 Change subject: soc/amd/common/block/pi/agesawrapper.c: Add new function sb_program_gpio() ...................................................................... soc/amd/common/block/pi/agesawrapper.c: Add new function sb_program_gpio() Add new function sb_program_gpio after AGESA wrapper for RESET and INIT_LATE. BUG=b:64140392 TEST=Build kahlee. Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/soc/amd/common/block/pi/agesawrapper.c 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/22987/1 diff --git a/src/soc/amd/common/block/pi/agesawrapper.c b/src/soc/amd/common/block/pi/agesawrapper.c index 7fb5485..53f1c2d 100644 --- a/src/soc/amd/common/block/pi/agesawrapper.c +++ b/src/soc/amd/common/block/pi/agesawrapper.c @@ -22,6 +22,7 @@ #include <amdblocks/BiosCallOuts.h> #include <string.h> #include <timestamp.h> +#include <soc/southbridge.h> void __attribute__((weak)) SetMemParams(AMD_POST_PARAMS *PostParams) {} void __attribute__((weak)) OemPostParams(AMD_POST_PARAMS *PostParams) {} @@ -90,6 +91,7 @@ timestamp_add_now(TS_AGESA_INIT_RESET_START); status = AmdInitReset(&AmdResetParams); timestamp_add_now(TS_AGESA_INIT_RESET_DONE); + sb_program_gpio(STAGE_RESET); if (status != AGESA_SUCCESS) agesawrapper_readeventlog(AmdParamStruct.StdHeader.HeapStatus); @@ -336,6 +338,7 @@ timestamp_add_now(TS_AGESA_INIT_LATE_START); Status = AmdInitLate(AmdLateParams); timestamp_add_now(TS_AGESA_INIT_LATE_DONE); + sb_program_gpio(STAGE_INIT_LATE); if (Status != AGESA_SUCCESS) { agesawrapper_readeventlog(AmdLateParams->StdHeader.HeapStatus); -- To view, visit https://review.coreboot.org/22987 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I38da26cd1e20617958a6b17d55b7d7c08b8a0230 Gerrit-Change-Number: 22987 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Richard Spiegel has uploaded this change for review. ( https://review.coreboot.org/22986 Change subject: soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function ...................................................................... soc/amd/stoneyridge/southbridge.c: Create a GPIO programming function Create a GPIO programming function that can be called from multiple stages (bootblock, romstage and ramstage) that will program only the GPIO specific to the particular stage. Add dummy table to kahlee to be able to test a build. BUG=b:64140392 TEST=Build kahlee. Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/google/kahlee/variants/baseboard/gpio.c M src/mainboard/google/kahlee/variants/kahlee/gpio.c M src/soc/amd/stoneyridge/include/soc/iomap.h M src/soc/amd/stoneyridge/include/soc/southbridge.h M src/soc/amd/stoneyridge/southbridge.c 5 files changed, 112 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/22986/1 diff --git a/src/mainboard/google/kahlee/variants/baseboard/gpio.c b/src/mainboard/google/kahlee/variants/baseboard/gpio.c index 250fcc1..35b35d1 100644 --- a/src/mainboard/google/kahlee/variants/baseboard/gpio.c +++ b/src/mainboard/google/kahlee/variants/baseboard/gpio.c @@ -21,6 +21,30 @@ #include <stdlib.h> /* + * The definitions bellow are valid only within this file, with the sole + * purpose of making the array below compact and easy to understand. + */ +#define PULL_UP FCH_GPIO_PULL_UP_ENABLE +#define PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE +#define INPUT 0 +#define OUTPUT_H (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE) +#define OUTPUT_L FCH_GPIO_OUTPUT_ENABLE + +/* + * These settings were generated by a spreadsheet. If they need to be updated, + * update the spreadsheet shared with the Grunt development team. + * + * As a rule of thumb, GPIO used by coreboot should be initialized at + * STAGE_RESET while GPIO used only by the OS should be initialized at + * STAGE_INIT_LATE. + */ +const static struct soc_amd_stoneyridge_gpio gpio_set_stage[] = { + + /* GPIO_0 - EC_PCH_PWR_BTN_ODL */ + { GPIO_0, Function0, PULL_UP | INPUT, STAGE_RESET } +}; + +/* * These settings were generated by a spreadsheet. If they need to be updated, * update the spreadsheet shared with the Grunt development team. */ @@ -260,6 +284,14 @@ return agesa_board_gpios; } +const __attribute__((weak)) const struct + soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage); + return gpio_set_stage; +} + + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } diff --git a/src/mainboard/google/kahlee/variants/kahlee/gpio.c b/src/mainboard/google/kahlee/variants/kahlee/gpio.c index e5e15e6..8d76ee9 100644 --- a/src/mainboard/google/kahlee/variants/kahlee/gpio.c +++ b/src/mainboard/google/kahlee/variants/kahlee/gpio.c @@ -20,6 +20,26 @@ #include <stdlib.h> #include <variant/gpio.h> +/* + * The definitions bellow are valid only within this file, with the sole + * purpose of making the array below compact and easy to understand. + */ +#define PULL_UP FCH_GPIO_PULL_UP_ENABLE +#define PULL_DOWN FCH_GPIO_PULL_DOWN_ENABLE +#define INPUT 0 +#define OUTPUT_H (FCH_GPIO_OUTPUT_ENABLE | FCH_GPIO_OUTPUT_VALUE) +#define OUTPUT_L FCH_GPIO_OUTPUT_ENABLE + +/* + * As a rule of thumb, GPIO used by coreboot should be initialized at + * STAGE_RESET while GPIO used only by the OS should be initialized at + * STAGE_INIT_LATE. + */ +const struct soc_amd_stoneyridge_gpio gpio_set_stage[] = { + /* AGPIO2, to become event generator */ + { GPIO_2, Function1, PULL_UP | INPUT, STAGE_RESET } +}; + static const GPIO_CONTROL agesa_board_gpios[] = { /* AGPIO2 PCIE/WLAN WAKE# SCI*/ {2, Function1, FCH_GPIO_PULL_UP_ENABLE }, @@ -104,6 +124,12 @@ return agesa_board_gpios; } +const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size) +{ + *size = ARRAY_SIZE(gpio_set_stage); + return gpio_set_stage; +} + /* * GPE setup table must match ACPI GPE ASL * { gevent, gpe, direction, level } diff --git a/src/soc/amd/stoneyridge/include/soc/iomap.h b/src/soc/amd/stoneyridge/include/soc/iomap.h index 64a9b30..9df1e6b 100644 --- a/src/soc/amd/stoneyridge/include/soc/iomap.h +++ b/src/soc/amd/stoneyridge/include/soc/iomap.h @@ -50,4 +50,8 @@ #define AB_DATA (AB_INDX+4) #define SYS_RESET 0xcf9 +/* GPIO control and mux access */ +#define AMD_GPIO_MUX (AMD_SB_ACPI_MMIO_ADDR + 0x00000d00) +#define AMD_GPIO_CONTROL (AMD_SB_ACPI_MMIO_ADDR + 0x00001500) + #endif /* __SOC_STONEYRIDGE_IOMAP_H__ */ diff --git a/src/soc/amd/stoneyridge/include/soc/southbridge.h b/src/soc/amd/stoneyridge/include/soc/southbridge.h index bbf6344..1d03822 100644 --- a/src/soc/amd/stoneyridge/include/soc/southbridge.h +++ b/src/soc/amd/stoneyridge/include/soc/southbridge.h @@ -271,7 +271,6 @@ #define XHCI_PM_INDIRECT_INDEX 0x48 #define XHCI_PM_INDIRECT_DATA 0x4C #define XHCI_OVER_CURRENT_CONTROL 0x30 - #define EHCI_OVER_CURRENT_CONTROL 0x70 #define USB_OC0 0 @@ -293,6 +292,18 @@ #define WIDEIO_RANGE_ERROR -1 #define TOTAL_WIDEIO_PORTS 3 +#define GPIO_CONTROL_MASK 0x00f00000 +#define GPIO_UNKNOWN_BIT 0x00040000 /* cleared by AGESA */ +struct soc_amd_stoneyridge_gpio { + uint8_t gpio; + uint8_t function; + uint8_t control; + enum { + STAGE_RESET, + STAGE_INIT_LATE + } stage; +}; + static inline int sb_sata_enable(void) { /* True if IDE or AHCI. */ @@ -346,6 +357,8 @@ int s3_load_nvram_early(int size, u32 *old_dword, int nvram_pos); int s3_save_nvram_early(u32 dword, int size, int nvram_pos); void bootblock_fch_early_init(void); +const struct soc_amd_stoneyridge_gpio *board_get_gpio(size_t *size); +void sb_program_gpio(int stage); /** * @brief Find the size of a particular wide IO * diff --git a/src/soc/amd/stoneyridge/southbridge.c b/src/soc/amd/stoneyridge/southbridge.c index 1357257..77a424b 100644 --- a/src/soc/amd/stoneyridge/southbridge.c +++ b/src/soc/amd/stoneyridge/southbridge.c @@ -142,6 +142,42 @@ return irq_association; } +void sb_program_gpio(int stage) +{ + uint32_t *control_ptr; + uint8_t *mux_ptr; + const struct soc_amd_stoneyridge_gpio *gpio_ptr; + uint32_t ptr_build, control_value; + int gpio = 0; + size_t size; + uint8_t control, mux, index; + + printk(BIOS_DEBUG, "GPIO programming stage %s\n", + (stage == STAGE_RESET) ? "reset" : "init late"); + gpio_ptr = board_get_gpio(&size); + for (index = 0; index < size; index++) { + if (gpio_ptr[index].stage == stage) { + mux = gpio_ptr[index].function; + control = gpio_ptr[index].control; + gpio = gpio_ptr[index].gpio; + mux_ptr = (uint8_t *) gpio + AMD_GPIO_MUX; + *mux_ptr = (mux & 0x03); /* clear reserved bits */ + ptr_build = gpio * 4; + ptr_build += AMD_GPIO_CONTROL; + control_ptr = (uint32_t *)ptr_build; + control_value = *control_ptr; + control_value &= ~(GPIO_CONTROL_MASK | + GPIO_UNKNOWN_BIT); + control_value |= ((control << 16) & GPIO_CONTROL_MASK); + *control_ptr = control_value; + printk(BIOS_DEBUG, "GPIO%-3d function%d set to" + " 0x%08x\n", + gpio, mux, *control_ptr); + } + } + printk(BIOS_DEBUG, "End GPIO programming\n"); +} + /** * @brief Find the size of a particular wide IO * -- To view, visit https://review.coreboot.org/22986 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I88d65c78a186bed9739bc208d5711a31aa3c3bb6 Gerrit-Change-Number: 22986 Gerrit-PatchSet: 1 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com>

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Change in coreboot[master]: drivers/net: Add deivce index for multiple NIC cards
by Furquan Shaikh (Code Review) 26 Dec '17

26 Dec '17

Furquan Shaikh has posted comments on this change. ( https://review.coreboot.org/22984 ) Change subject: drivers/net: Add deivce index for multiple NIC cards ...................................................................... Patch Set 1: (4 comments) https://review.coreboot.org/#/c/22984/1/src/drivers/net/chip.h File src/drivers/net/chip.h: https://review.coreboot.org/#/c/22984/1/src/drivers/net/chip.h@20 PS1, Line 20: /* Indentify device number */ Can you please add some more details what this device number is used for? Also, specify the set of valid values that are expected for this field. https://review.coreboot.org/#/c/22984/1/src/drivers/net/r8168.c File src/drivers/net/r8168.c: https://review.coreboot.org/#/c/22984/1/src/drivers/net/r8168.c@94 PS1, Line 94: u8 Why not use the same data type in drivers_net_config? https://review.coreboot.org/#/c/22984/1/src/drivers/net/r8168.c@107 PS1, Line 107: key[12] = device_index + 0x30; This is going to break all the older devices using key "ethernet_mac". I think we should maintain backward compatibility. e.g.: Treat device_index 0 as special i.e. no index specified by the board and thus use key --> ethernet_mac\0. Else if device_index is 1-9, use key --> ethernet_macX\0 where X is 1-9. https://review.coreboot.org/#/c/22984/1/src/drivers/net/r8168.c@109 PS1, Line 109: printk(BIOS_DEBUG, "Requesting %s from VPD.\n", key) Maybe combine this and the print in L129 to have something like: printk(BIOS_DEBUG, "Locating %s from VPD...", key); ... printk(BIOS_DEBUG, "Done\n"); -- To view, visit https://review.coreboot.org/22984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Gerrit-Change-Number: 22984 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 13:25:01 +0000 Gerrit-HasComments: Yes Gerrit-HasLabels: No

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Change in coreboot[master]: drivers/net: Add deivce index for multiple NIC cards
by build bot (Jenkins) (Code Review) 26 Dec '17

26 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22984 ) Change subject: drivers/net: Add deivce index for multiple NIC cards ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19754/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64997/ : SUCCESS -- To view, visit https://review.coreboot.org/22984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Gerrit-Change-Number: 22984 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 09:50:02 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/net: Add deivce index for multiple NIC cards
by Gaggery Tsai (Code Review) 26 Dec '17

26 Dec '17

Gaggery Tsai has uploaded this change for review. ( https://review.coreboot.org/22984 Change subject: drivers/net: Add deivce index for multiple NIC cards ...................................................................... drivers/net: Add deivce index for multiple NIC cards This patch adds a member device_index to r8168 chip information which allows driver to indetify which NIC card requests MAC address. In this implmentation, only 10 NIC cards are supported, the device index is in the range of 0 to 9. BUG=b:69950854 BRANCH=None TEST=Added device_indexi = [0-9] under /drivers/net in device tree && Programmed the mac address to VPD in shell vpd -s ethernet_mac[0-9]=<mac address> && reboot the system. Ensure the MAC address was fetched correctly by ifconfig command. Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Signed-off-by: Gaggery Tsai <gaggery.tsai(a)intel.com> --- M src/drivers/net/chip.h M src/drivers/net/r8168.c 2 files changed, 18 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/22984/1 diff --git a/src/drivers/net/chip.h b/src/drivers/net/chip.h index 8e8c02b..5d253dc 100644 --- a/src/drivers/net/chip.h +++ b/src/drivers/net/chip.h @@ -16,7 +16,8 @@ struct drivers_net_config { uint16_t customized_leds; - unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned wake; /* Wake pin for ACPI _PRW */ + unsigned device_index; /* Indentify device number */ }; #endif /* __DRIVERS_R8168_CHIP_H__ */ diff --git a/src/drivers/net/r8168.c b/src/drivers/net/r8168.c index 4c17017..74c8f87 100644 --- a/src/drivers/net/r8168.c +++ b/src/drivers/net/r8168.c @@ -91,13 +91,22 @@ #define MACLEN 17 -static enum cb_err fetch_mac_string_vpd(u8 *macstrbuf) +static enum cb_err fetch_mac_string_vpd(u8 *macstrbuf, const u8 device_index) { struct region_device rdev; void *search_address; size_t search_length; size_t offset; - char key[] = "ethernet_mac"; + char key[] = "ethernet_mac "; /* Leave a space at tail to stuff an index */ + + /* TODO: Limit up to 10 (0-9) NIC MAC address from VPD at this moment + * , but will we have 10 more NIC cards? + */ + + /* Translate index number from integer to ascii, base '0' is 0x30 */ + key[12] = device_index + 0x30; + + printk(BIOS_DEBUG, "Requesting %s from VPD.\n", key); if (fmap_locate_area_as_rdev("RO_VPD", &rdev)) { printk(BIOS_ERR, "Error: Couldn't find RO_VPD region."); @@ -172,10 +181,14 @@ int i = 0; /* Default MAC Address of 00:E0:4C:00:C0:B0 */ u8 mac[6] = { 0x00, 0xe0, 0x4c, 0x00, 0xc0, 0xb0 }; + struct drivers_net_config *config = dev->chip_info; + + if (!config) + return; /* check the VPD for the mac address */ if (IS_ENABLED(CONFIG_RT8168_GET_MAC_FROM_VPD)) { - if (fetch_mac_string_vpd(macstrbuf) != CB_SUCCESS) + if (fetch_mac_string_vpd(macstrbuf, config->device_index) != CB_SUCCESS) printk(BIOS_ERR, "r8168: mac address not found in VPD," " using default 00:e0:4c:00:c0:b0\n"); } else { -- To view, visit https://review.coreboot.org/22984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Gerrit-Change-Number: 22984 Gerrit-PatchSet: 1 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com>

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Change in coreboot[master]: mainboard/hp: Add Elitebook Revolve 810 G1
by build bot (Jenkins) (Code Review) 25 Dec '17

25 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Elitebook Revolve 810 G1 ...................................................................... Patch Set 9: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19753/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64996/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 9 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Dec 2017 15:01:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: mainboard/hp: Add Elitebook Revolve 810 G1
by build bot (Jenkins) (Code Review) 25 Dec '17

25 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Elitebook Revolve 810 G1 ...................................................................... Patch Set 8: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19752/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64995/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 8 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 25 Dec 2017 03:58:20 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: tianocore: fix Makefile to be able to build a custom revision or branch
by build bot (Jenkins) (Code Review) 24 Dec '17

24 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22983 ) Change subject: tianocore: fix Makefile to be able to build a custom revision or branch ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19751/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64994/ : SUCCESS -- To view, visit https://review.coreboot.org/22983 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I9711a370eeade3cba0a9e127deb3d96d82adc512 Gerrit-Change-Number: 22983 Gerrit-PatchSet: 1 Gerrit-Owner: Gergely Kiss <mail.gery(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sun, 24 Dec 2017 22:14:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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coreboot-gerrit December 2017