coreboot-gerrit December 2017

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Change in coreboot[master]: nb/intel/x4x: Implement write leveling
by Arthur Heymans (Code Review) 26 Dec '17

26 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22995 Change subject: nb/intel/x4x: Implement write leveling ...................................................................... nb/intel/x4x: Implement write leveling DDR3 adapter a fly-by topology which allows for better signal integrity but at the same time requires additional calibration. This is done by settings the targeted rank in write leveling mode while disabling output buffer on the other ranks. Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/dq_dqs.c M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/x4x.h 3 files changed, 401 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/22995/1 diff --git a/src/northbridge/intel/x4x/dq_dqs.c b/src/northbridge/intel/x4x/dq_dqs.c index 97bfa42..12e2ab3 100644 --- a/src/northbridge/intel/x4x/dq_dqs.c +++ b/src/northbridge/intel/x4x/dq_dqs.c @@ -16,6 +16,7 @@ #include <arch/io.h> #include <console/console.h> +#include <delay.h> #include <stdint.h> #include <string.h> #include <types.h> @@ -106,6 +107,34 @@ return CB_SUCCESS; } +static int decrement_dq_dqs(const struct sysinfo *s, + struct dll_setting *dq_dqs_setting) +{ + u8 max_tap_val = max_tap[s->selected_timings.mem_clk + - MEM_CLOCK_800MHz]; + /* PI */ + if (dq_dqs_setting->pi > 0) { + dq_dqs_setting->pi -= 1; + } else if (dq_dqs_setting->tap > 0) { + dq_dqs_setting->pi = 6; + dq_dqs_setting->tap -= 1; + } else if (dq_dqs_setting->clk_delay > 0) { + dq_dqs_setting->pi = 6; + dq_dqs_setting->tap = max_tap_val; + dq_dqs_setting->clk_delay -= 1; + } else if (dq_dqs_setting->coarse > 0) { + dq_dqs_setting->pi = 6; + dq_dqs_setting->tap = max_tap_val; + dq_dqs_setting->clk_delay += 1; + dq_dqs_setting->coarse -= 1; + } else { + return CB_ERR; + } + set_db(s, dq_dqs_setting); + return CB_SUCCESS; +} + + #define WT_PATTERN_SIZE 80 static const u32 write_training_schedule[WT_PATTERN_SIZE] = { @@ -476,3 +505,337 @@ printk(BIOS_DEBUG, "Done DQS read training\n"); return CB_SUCCESS; } + +/* Enable write leveling on rank0 + */ +static void set_rank_write_level(struct sysinfo *s, u8 channel, u8 config, + u8 config_rank, u8 target_rank, int wl_enable) +{ + u32 emrs1; + + /* Is shifted by bits 2 later so u8 can be used to reduce size */ + const static u8 emrs1_lut[8][4][4]={ /* [Config][Leveling Rank][Rank] */ + { /* Config 0: 2R2R */ + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x11, 0x91, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x91, 0x00, 0x00, 0x11} + }, + { // Config 1: 2R1R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x11, 0x91, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 2: 1R2R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x91, 0x00, 0x00, 0x11} + }, + { // Config 3: 1R1R + {0x11, 0x00, 0x91, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x91, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 4: 2R0R + {0x11, 0x00, 0x00, 0x00}, + {0x00, 0x11, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 5: 0R2R + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x11} + }, + { // Config 6: 1R0R + {0x11, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00} + }, + { // Config 7: 0R1R + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x00, 0x00}, + {0x00, 0x00, 0x11, 0x00}, + {0x00, 0x00, 0x00, 0x00} + } + }; + + if (wl_enable) { + printk(RAM_DEBUG, "Entering WL mode\n"); + printk(RAM_DEBUG, "Using WL ODT values\n"); + emrs1 = emrs1_lut[config][target_rank][config_rank]; + } else { + printk(RAM_DEBUG, "Exiting WL mode\n"); + emrs1 = ddr3_emrs1_config[s->dimm_config[channel]][config_rank]; + } + printk(RAM_DEBUG, "Setting ODT for rank%d to ", config_rank); + switch (emrs1) { + case 0: + printk(RAM_DEBUG, "0 Ohm\n"); + break; + case 0x11: + printk(RAM_DEBUG, "40 Ohm\n"); + break; + case 0x81: + printk(RAM_DEBUG, "30 Ohm\n"); + break; + case 0x80: + printk(RAM_DEBUG, "20 Ohm\n"); + break; + case 0x10: + printk(RAM_DEBUG, "120 Ohm\n"); + break; + case 0x01: + printk(RAM_DEBUG, "60 Ohm\n"); + break; + default: + printk(BIOS_WARNING, "ODT value Undefined!\n"); + break; + } + + emrs1 <<= 2; + emrs1 |= (1 << 1); + + if (wl_enable && (target_rank != config_rank)) { + printk(RAM_DEBUG, "Disabling output for rank%d\n", config_rank); + emrs1 |= (1 << 12); + } + if (wl_enable && (target_rank == config_rank)) { + printk(RAM_DEBUG, "Enabling WL for rank%d\n", config_rank); + emrs1 |= (1 << 7); + } + send_jedec_cmd(s, config_rank, channel, EMRS1_CMD, emrs1); +} + +#define N_SAMPLES 5 + +static void sample_dq(const struct sysinfo *s, u8 channel, u8 rank, + u8 high_found[8]) { + u32 address = test_address(channel, rank); + int samples, lane; + + memset(high_found, 0, TOTAL_BYTELANES * sizeof(high_found[0])); + for (samples = 0; samples < N_SAMPLES; samples++) { + write32((u32 *)address, 0x12341234); + write32((u32 *)address + 4, 0x12341234); + udelay(5); + FOR_EACH_BYTELANE(lane) { + u8 dq_high = (MCHBAR8(0x561 + 0x400 * channel + + (lane * 4)) >> 7) & 1; + high_found[lane] += dq_high; + } + } +} + +static enum cb_err increment_to_dqs_edge(struct sysinfo *s, u8 channel, u8 rank) +{ + int lane; + u8 saved_24d; + struct dll_setting dqs_setting[TOTAL_BYTELANES]; + u8 bytelane_ok = 0; + u8 dq_sample[TOTAL_BYTELANES]; + + memcpy(dqs_setting, s->dqs_settings[channel], sizeof(dqs_setting)); + FOR_EACH_BYTELANE(lane) + dqsset(channel, lane, &dqs_setting[lane]); + + saved_24d = MCHBAR8(0x24d + 0x400 * channel); + + /* Loop 0: Find DQ sample low, by decreasing */ + while (bytelane_ok != 0xff) { + sample_dq(s, channel, rank, dq_sample); + FOR_EACH_BYTELANE(lane) { + if (bytelane_ok & (1 << lane)) + continue; + + printk(RAM_SPEW, "%d, %d, %02d, %d," + " lane%d sample: %d\n", + dqs_setting[lane].coarse, + dqs_setting[lane].clk_delay, + dqs_setting[lane].tap, + dqs_setting[lane].pi, + lane, + dq_sample[lane]); + + if (dq_sample[lane] > 0) { + if (decrement_dq_dqs(s, &dqs_setting[lane])) { + printk(BIOS_EMERG, + "DQS setting channel%d, " + "lane %d reached a minimum!\n", + channel, lane); + return CB_ERR; + } + } else { + bytelane_ok |= (1 << lane); + } + dqsset(channel, lane, &dqs_setting[lane]); + } + } + + printk(RAM_DEBUG, "DQS settings on PASS #0:\n"); + FOR_EACH_BYTELANE(lane) { + printk(RAM_DEBUG, "lane %d: ", lane); + print_dll_setting(&dqs_setting[lane], 0); + } + + /* Loop 1: Find DQ sample high, by increasing */ + bytelane_ok = 0; + while (bytelane_ok != 0xff) { + sample_dq(s, channel, rank, dq_sample); + FOR_EACH_BYTELANE(lane) { + if (bytelane_ok & (1 << lane)) + continue; + + printk(RAM_SPEW, "%d, %d, %02d, %d, lane%d sample: %d\n", + dqs_setting[lane].coarse, + dqs_setting[lane].clk_delay, + dqs_setting[lane].tap, + dqs_setting[lane].pi, + lane, + dq_sample[lane]); + + + if (dq_sample[lane] == N_SAMPLES) { + bytelane_ok |= (1 << lane); + } else { + if (increment_dq_dqs(s, &dqs_setting[lane])) { + printk(BIOS_EMERG, + "DQS setting channel%d, " + "lane %d reached a maximum!\n", + channel, lane); + return CB_ERR; + + } + } + dqsset(channel, lane, &dqs_setting[lane]); + } + } + + printk(RAM_DEBUG, "DQS settings on PASS #1:\n"); + FOR_EACH_BYTELANE(lane) { + printk(RAM_DEBUG, "lane %d: ", lane); + print_dll_setting(&dqs_setting[lane], 0); + } + + printk(BIOS_DEBUG, "final WL DQS settings on CH%d\n", channel); + FOR_EACH_BYTELANE(lane) { + printk(BIOS_DEBUG, "\tlane%d: ", lane); + print_dll_setting(&dqs_setting[lane], 1); + s->dqs_settings[channel][lane] = dqs_setting[lane]; + } + + MCHBAR8(0x24d + 0x400 * channel) = saved_24d; + return CB_SUCCESS; +} + +void search_write_leveling(struct sysinfo *s) +{ + int i, ch, count; + u8 config, rank0, rank1, lane; + struct dll_setting dq_setting; + + u8 chanconfig_lut[16]={0, 6, 4, 6, 7, 3, 1, 3, 5, 2, 0, 2, 7, 3, 1, 3}; + + u8 odt_force[8][4] = { /* [Config][leveling rank] */ + {0x5, 0x6, 0x5, 0x9}, + {0x5, 0x6, 0x5, 0x0}, + {0x5, 0x0, 0x5, 0x9}, + {0x5, 0x0, 0x5, 0x0}, + {0x1, 0x2, 0x0, 0x0}, + {0x0, 0x0, 0x4, 0x8}, + {0x1, 0x0, 0x0, 0x0}, + {0x0, 0x0, 0x4, 0x0} + }; + + printk(BIOS_DEBUG, "Starting write levelling.\n"); + + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + printk(BIOS_DEBUG, "\tCH%d\n", ch); + config = chanconfig_lut[s->dimm_config[ch]]; + + MCHBAR8(0x5d8 + 0x400 * ch) = + MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e; + MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & + ~0x3fff) | 0x3fff; + MCHBAR8(0x265 + 0x400 * ch) = + MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) { + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank1) { + set_rank_write_level(s, ch, config, rank1, rank0, 1); + } + + MCHBAR8(0x298 + 2 + 0x400 * ch) = + (MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f) + | odt_force[config][rank0]; + MCHBAR8(0x271 + 0x400 * ch) = (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) + | 0x4e; + MCHBAR8(0x5d9 + 0x400 * ch) = + (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04) | 0x04; + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x07ffffff) + | 0x00014000; + + if (increment_to_dqs_edge(s, ch, rank0)) + die("Write Leveling failed!"); + + MCHBAR8(0x298 + 2 + 0x400 * ch) = + MCHBAR8(0x298 + 2 + 0x400 * ch) & ~0x0f; + MCHBAR8(0x271 + 0x400 * ch) = + (MCHBAR8(0x271 + 0x400 * ch) & ~0x7e) + | 0x0e; + MCHBAR8(0x5d9 + 0x400 * ch) = + (MCHBAR8(0x5d9 + 0x400 * ch) & ~0x04); + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) + & ~0x07ffffff) | 0x00555801; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, + rank1) { + if (rank0 == rank1) { + set_rank_write_level(s, ch, config, + rank1, rank0, 0); + send_jedec_cmd(s, rank1, ch, + NORMALOP_CMD, 1 << 12); + } + } + break; /* Break on first populated rank */ + } + MCHBAR8(0x5d8 + 0x400 * ch) = (MCHBAR8(0x5d8 + 0x400 * ch) & ~0x0e) | 0x0e; + MCHBAR16(0x5c4 + 0x400 * ch) = (MCHBAR16(0x5c4 + 0x400 * ch) & + ~0x3fff) | 0x1807; + MCHBAR8(0x265 + 0x400 * ch) = MCHBAR8(0x265 + 0x400 * ch) & ~0x1f; + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, ch, rank0) { + set_rank_write_level(s, ch, config, rank0, rank0, 0); + } + + } + MCHBAR8(0x5dc) = (MCHBAR8(0x5dc) & ~0x80) | 0x80; + + /* + * Increment DQ dll setting by a standard amount past DQS, + * This is further trained in write training. + */ + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + count = 39; + break; + case MEM_CLOCK_1066MHz: + count = 32; + break; + case MEM_CLOCK_1333MHz: + count = 42; + break; + } + + FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(s->dimms, ch, lane) { + dq_setting = s->dqs_settings[ch][lane]; + for (i = 0; i < count; i++) + increment_dq_dqs(s, &dq_setting); + dqset(ch, lane, &dq_setting); + } + + printk(BIOS_DEBUG, "Done write levelling.\n"); +} diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 2835890..13b98ee 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1360,8 +1360,7 @@ return channel * 512 * MiB + rank * 128 * MiB; } -static void send_jedec_cmd(const struct sysinfo *s, u8 r, - u8 ch, u8 cmd, u32 val) +void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val) { u32 addr = test_address(ch, r); volatile u32 rubbish; @@ -1926,6 +1925,23 @@ MCHBAR8(0x561 + (lane << 2)) = MCHBAR8(0x561 + (lane << 2)) & ~(1 << 3); } +static void software_ddr3_reset(struct sysinfo *s) +{ + printk(BIOS_DEBUG, "Software initiated DDR3 reset.\n"); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x02; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02; + MCHBAR8(0x5da) = (MCHBAR8(0x5da) & ~0x03) | 1; + udelay(200); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x02; + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + udelay(500); + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x03; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x03; + jedec_ddr3(s); +} + void do_raminit(struct sysinfo *s, int fast_boot) { u8 ch; @@ -2012,6 +2028,17 @@ MCHBAR8(0x9d8) = MCHBAR8(0x9d8) | 0x7; } + /* DDR3 reset */ + if ((s->spd_type == DDR3) && (s->boot_path != BOOT_PATH_RESUME)) { + printk(BIOS_DEBUG, "DDR3 Reset.\n"); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2; + MCHBAR8(0x5da) = MCHBAR8(0x5da) | 0x80; + udelay(500); + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x2; + MCHBAR8(0x5da) = MCHBAR8(0x5da) & ~0x80; + udelay(500); + } + // Pre jedec MCHBAR8(0x40) = MCHBAR8(0x40) | 0x2; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { @@ -2031,6 +2058,13 @@ printk(BIOS_DEBUG, "Done jedec steps\n"); + if (s->spd_type == DDR3) { + if (!fast_boot) + search_write_leveling(s); + if (s->boot_path == BOOT_PATH_NORMAL) + software_ddr3_reset(s); + } + // After JEDEC reset MCHBAR8(0x40) = MCHBAR8(0x40) & ~0x2; FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index 37215b1..a781a80 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -396,7 +396,8 @@ struct abs_timings *saved_timings); int ddr3_save_dimminfo(u8 dimm_idx, u8 *raw_spd, struct abs_timings *saved_timings, struct sysinfo *s); - +void search_write_leveling(struct sysinfo *s); +void send_jedec_cmd(const struct sysinfo *s, u8 r, u8 ch, u8 cmd, u32 val); extern const struct dll_setting default_ddr2_667_ctrl[7]; extern const struct dll_setting default_ddr2_800_ctrl[7]; -- To view, visit https://review.coreboot.org/22995 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I695969868b4534f87dd1f37244fdfac891a417f0 Gerrit-Change-Number: 22995 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Add DDR3 JEDEC init
by Arthur Heymans (Code Review) 26 Dec '17

26 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22994 Change subject: nb/intel/x4x: Add DDR3 JEDEC init ...................................................................... nb/intel/x4x: Add DDR3 JEDEC init Add DDR3 JEDEC init (Power up and Initialization by setting emrs regs) the ddr3_emrs1_config array is placed externally since it is needed for write leveling. Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c M src/northbridge/intel/x4x/raminit_tables.c M src/northbridge/intel/x4x/spd_ddr3_decode.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 100 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/22994/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index ddb1e01..2835890 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1360,14 +1360,34 @@ return channel * 512 * MiB + rank * 128 * MiB; } -static void dojedec_ddr2(u8 r, u8 ch, u8 cmd, u16 val) +static void send_jedec_cmd(const struct sysinfo *s, u8 r, + u8 ch, u8 cmd, u32 val) { u32 addr = test_address(ch, r); volatile u32 rubbish; + u8 data8 = cmd; + u32 data32; - MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | cmd; - MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | cmd; - rubbish = read32((void *)((val<<3) | addr)); + if (s->spd_type == DDR3 && (r & 1) + && s->dimms[ch * 2 + (r >> 1)].mirrorred) { + data8 &= ~(1 << 4); + data8 |= ((1 << 4) & (cmd >> 1)); + data8 &= ~(1 << 5); + data8 |= ((1 << 5) & (cmd << 1)); + } + + MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | data8; + MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | data8; + data32 = val; + if (s->spd_type == DDR3 && (r & 1) + && s->dimms[ch * 2 + (r >> 1)].mirrorred) { + data32 &= ~(0x1f8); + data32 |= (val & 0xa0) << 1; + data32 |= (val & 0x160) >> 1; + } + data32 <<= 3; + + rubbish = read32((void *)((data32 | addr))); udelay(10); MCHBAR8(0x271) = (MCHBAR8(0x271) & ~0x3e) | NORMALOP_CMD; MCHBAR8(0x671) = (MCHBAR8(0x671) & ~0x3e) | NORMALOP_CMD; @@ -1432,7 +1452,7 @@ default: break; } - dojedec_ddr2(r, ch, jedec[i][0], v); + send_jedec_cmd(s, r, ch, jedec[i][0], v); udelay(1); printk(RAM_SPEW, "Jedec step %d\n", i); } @@ -1440,6 +1460,52 @@ printk(BIOS_DEBUG, "MRS done\n"); } +static void jedec_ddr3(struct sysinfo *s) +{ + int ch, r, dimmconfig, cmd, ddr3_freq; + + u8 ddr3_emrs2_config[16][4] = { /* [config][Rank] */ + {0, 0, 0, 0}, /* NC_NC */ + {0, 0, 0, 0}, /* x8ss_NC */ + {0, 0, 0, 0}, /* x8ds_NC */ + {0, 0, 0, 0}, /* x16ss_NC */ + {0, 0, 0, 0}, /* NC_x8ss */ + {2, 0, 2, 0}, /* x8ss_x8ss */ + {2, 2, 2, 0}, /* x8ds_x8ss */ + {2, 0, 2, 0}, /* x16ss_x8ss */ + {0, 0, 0, 0}, /* NC_x8ss */ + {2, 0, 2, 2}, /* x8ss_x8ds */ + {2, 2, 2, 2}, /* x8ds_x8ds */ + {2, 0, 2, 2}, /* x16ss_x8ds */ + {0, 0, 0, 0}, /* NC_x16ss */ + {2, 0, 2, 0}, /* x8ss_x16ss */ + {2, 2, 2, 0}, /* x8ds_x16ss */ + {2, 0, 2, 0}, /* x16ss_x16ss */ + }; + + printk(BIOS_DEBUG, "MRS...\n"); + + ddr3_freq = s->selected_timings.mem_clk - MEM_CLOCK_800MHz; + FOR_EACH_POPULATED_RANK(s->dimms, ch, r) { + printk(BIOS_DEBUG, "CH%d: Found Rank %d\n", ch, r); + send_jedec_cmd(s, r, ch, NOP_CMD, 0); + udelay(200); + dimmconfig = s->dimm_config[ch]; + cmd = ddr3_freq << 3; /* actually twl - 5 which is same */ + cmd |= ddr3_emrs2_config[dimmconfig][r] << 9; + send_jedec_cmd(s, r, ch, EMRS2_CMD, cmd); + send_jedec_cmd(s, r, ch, EMRS3_CMD, 0); + cmd = ddr3_emrs1_config[dimmconfig][r] << 2; + cmd |= (1 << 1); + send_jedec_cmd(s, r, ch, EMRS1_CMD, cmd); + send_jedec_cmd(s, r, ch, MRS_CMD, (1 << 3) | (1 << 8) + | (1 << 12) | ((s->selected_timings.CAS - 4) << 4) + | ((s->selected_timings.tWR - 4) << 9)); + send_jedec_cmd(s, r, ch, ZQCAL_CMD, (1 << 10)); + } + printk(BIOS_DEBUG, "MRS done\n"); +} + static void sdram_recover_receive_enable(const struct sysinfo *s) { u32 reg32; @@ -1956,8 +2022,12 @@ printk(BIOS_DEBUG, "Done pre-jedec\n"); // JEDEC reset - if (s->boot_path != BOOT_PATH_RESUME) - jedec_ddr2(s); + if (s->boot_path != BOOT_PATH_RESUME) { + if (s->spd_type == DDR2) + jedec_ddr2(s); + else /* DDR3 */ + jedec_ddr3(s); + } printk(BIOS_DEBUG, "Done jedec steps\n"); diff --git a/src/northbridge/intel/x4x/raminit_tables.c b/src/northbridge/intel/x4x/raminit_tables.c index f386b6b..ee64967 100644 --- a/src/northbridge/intel/x4x/raminit_tables.c +++ b/src/northbridge/intel/x4x/raminit_tables.c @@ -269,3 +269,22 @@ {13, 6, 1, 0, 1, 0}, {0, 3, 1, 1, 0, 1}, } }; + +const u8 ddr3_emrs1_config[16][4] = { /* [Config][Rank] */ + {0x00, 0x00, 0x00, 0x00}, /* NC_NC */ + {0x11, 0x00, 0x00, 0x00}, /* 8S_NC */ + {0x11, 0x11, 0x00, 0x00}, /* 8D_NC */ + {0x11, 0x00, 0x00, 0x00}, /* 16S_NC */ + {0x00, 0x00, 0x11, 0x00}, /* NC_8S */ + {0x81, 0x00, 0x81, 0x00}, /* 8S_8S */ + {0x81, 0x81, 0x81, 0x00}, /* 8D_8S */ + {0x81, 0x00, 0x81, 0x00}, /* 16S_8S */ + {0x00, 0x00, 0x11, 0x11}, /* NC_8D */ + {0x81, 0x00, 0x81, 0x81}, /* 8S_8D */ + {0x81, 0x81, 0x81, 0x81}, /* 8D_8D */ + {0x81, 0x00, 0x81, 0x81}, /* 16S_8D */ + {0x00, 0x00, 0x11, 0x00}, /* NC_16S */ + {0x81, 0x00, 0x81, 0x00}, /* 8S_16S */ + {0x81, 0x81, 0x81, 0x00}, /* 8D_16S */ + {0x81, 0x00, 0x81, 0x00}, /* 16S_16S */ +}; diff --git a/src/northbridge/intel/x4x/spd_ddr3_decode.c b/src/northbridge/intel/x4x/spd_ddr3_decode.c index b1ac3ea..a57b14c 100644 --- a/src/northbridge/intel/x4x/spd_ddr3_decode.c +++ b/src/northbridge/intel/x4x/spd_ddr3_decode.c @@ -160,6 +160,8 @@ s->dimms[dimm_idx].rows = decoded_dimm.row_bits; s->dimms[dimm_idx].cols = decoded_dimm.col_bits; + s->dimms[dimm_idx].mirrorred = decoded_dimm.flags.pins_mirrored; + saved_timings->min_tRAS = MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); saved_timings->min_tRP = diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index f374725..37215b1 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -308,6 +308,7 @@ unsigned int ranks; unsigned int rows; unsigned int cols; + u8 mirrorred; u16 checksum; }; @@ -412,6 +413,7 @@ extern const struct dll_setting default_ddr3_800_dq[2][8]; extern const struct dll_setting default_ddr3_1067_dq[2][8]; extern const struct dll_setting default_ddr3_1333_dq[2][8]; +extern const u8 ddr3_emrs1_config[16][4]; struct acpi_rsdp; #ifndef __SIMPLE_DEVICE__ -- To view, visit https://review.coreboot.org/22994 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I510b8669aaa48ba99fb4dcf1ece716aef26741bb Gerrit-Change-Number: 22994 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: nb/intel/x4x: Move decoding DDR2 SPD to separate file
by Arthur Heymans (Code Review) 26 Dec '17

26 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22992 Change subject: nb/intel/x4x: Move decoding DDR2 SPD to separate file ...................................................................... nb/intel/x4x: Move decoding DDR2 SPD to separate file This is needed to avoid type conflicts when decoding DDR3 when using functions in device/dram/ddr3.c. Nothing functional is changed. Change-Id: I965fb8261c14381a35b361df2a3b40a9ea192669 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/Makefile.inc M src/northbridge/intel/x4x/raminit.c A src/northbridge/intel/x4x/spd_ddr2_decode.c M src/northbridge/intel/x4x/x4x.h 4 files changed, 163 insertions(+), 132 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/92/22992/1 diff --git a/src/northbridge/intel/x4x/Makefile.inc b/src/northbridge/intel/x4x/Makefile.inc index 29ece07..ef9b991 100644 --- a/src/northbridge/intel/x4x/Makefile.inc +++ b/src/northbridge/intel/x4x/Makefile.inc @@ -23,6 +23,7 @@ romstage-y += rcven.c romstage-y += raminit_tables.c romstage-y += dq_dqs.c +romstage-y += spd_ddr2_decode.c ramstage-y += acpi.c ramstage-y += ram_calc.c diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 3cd75be..81dcc1d 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -83,59 +83,8 @@ return CB_SUCCESS; } -struct abs_timings { - u32 min_tclk; - u32 min_tRAS; - u32 min_tRP; - u32 min_tRCD; - u32 min_tWR; - u32 min_tRFC; - u32 min_tWTR; - u32 min_tRRD; - u32 min_tRTP; - u32 min_tCLK_cas[8]; - u32 cas_supported; -}; - #define CTRL_MIN_TCLK_DDR2 TCK_400MHZ -static void select_cas_dramfreq_ddr2(struct sysinfo *s, - const struct abs_timings *saved_timings) -{ - u8 try_cas; - /* Currently only these CAS are supported */ - u8 cas_mask = SPD_CAS_LATENCY_DDR2_5 | SPD_CAS_LATENCY_DDR2_6; - - cas_mask &= saved_timings->cas_supported; - try_cas = spd_get_msbs(cas_mask); - - while (cas_mask & (1 << try_cas) && try_cas > 0) { - s->selected_timings.CAS = try_cas; - s->selected_timings.tclk = saved_timings->min_tCLK_cas[try_cas]; - if (s->selected_timings.tclk >= CTRL_MIN_TCLK_DDR2 && - saved_timings->min_tCLK_cas[try_cas] != - saved_timings->min_tCLK_cas[try_cas - 1]) - break; - try_cas--; - } - - - if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0)) - die("Could not find common memory frequency and CAS\n"); - - switch (s->selected_timings.tclk) { - case TCK_200MHZ: - case TCK_266MHZ: - /* FIXME: this works on vendor BIOS */ - die("Selected dram frequency not supported\n"); - case TCK_333MHZ: - s->selected_timings.mem_clk = MEM_CLOCK_667MHz; - break; - case TCK_400MHZ: - s->selected_timings.mem_clk = MEM_CLOCK_800MHz; - break; - } -} static void mchinfo_ddr2(struct sysinfo *s) { @@ -160,87 +109,6 @@ printk(BIOS_WARNING, "VT-d enabled\n"); } -static int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, - struct abs_timings *saved_timings, struct sysinfo *s) -{ - struct dimm_attr_st decoded_dimm; - int i; - - if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) { - printk(BIOS_DEBUG, "Problems decoding SPD\n"); - return CB_ERR; - } - - if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) - dram_print_spd_ddr2(&decoded_dimm); - - if (!(decoded_dimm.width & (0x08 | 0x10))) { - - printk(BIOS_ERR, - "DIMM%d Unsupported width: x%d. Disabling dimm\n", - dimm_idx, s->dimms[dimm_idx].width); - return CB_ERR; - } - s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1; - /* - * This boils down to: - * "Except for the x16 configuration, all DDR2 devices have a - * 1KB page size. For the x16 configuration, the page size is 2KB - * for all densities except the 256Mb device, which has a 1KB page - * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' - * The formula is pagesize in KiB = width * 2^col_bits / 8. - */ - s->dimms[dimm_idx].page_size = decoded_dimm.width * - (1 << decoded_dimm.col_bits) / 8; - - switch (decoded_dimm.banks) { - case 4: - s->dimms[dimm_idx].n_banks = N_BANKS_4; - break; - case 8: - s->dimms[dimm_idx].n_banks = N_BANKS_8; - break; - default: - printk(BIOS_ERR, - "DIMM%d Unsupported #banks: x%d. Disabling dimm\n", - dimm_idx, decoded_dimm.banks); - return CB_ERR; - } - - s->dimms[dimm_idx].ranks = decoded_dimm.ranks; - s->dimms[dimm_idx].rows = decoded_dimm.row_bits; - s->dimms[dimm_idx].cols = decoded_dimm.col_bits; - - saved_timings->cas_supported &= decoded_dimm.cas_supported; - - saved_timings->min_tRAS = - MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); - saved_timings->min_tRP = - MAX(saved_timings->min_tRP, decoded_dimm.tRP); - saved_timings->min_tRCD = - MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); - saved_timings->min_tWR = - MAX(saved_timings->min_tWR, decoded_dimm.tWR); - saved_timings->min_tRFC = - MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); - saved_timings->min_tWTR = - MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); - saved_timings->min_tRRD = - MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); - saved_timings->min_tRTP = - MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); - for (i = 0; i < 8; i++) { - if (!(saved_timings->cas_supported & (1 << i))) - saved_timings->min_tCLK_cas[i] = 0; - else - saved_timings->min_tCLK_cas[i] = - MAX(saved_timings->min_tCLK_cas[i], - decoded_dimm.cycle_time[i]); - } - s->dimms[dimm_idx].checksum = decoded_dimm.checksum; - return CB_SUCCESS; -} - static void select_discrete_timings(struct sysinfo *s, const struct abs_timings *timings) { diff --git a/src/northbridge/intel/x4x/spd_ddr2_decode.c b/src/northbridge/intel/x4x/spd_ddr2_decode.c new file mode 100644 index 0000000..b3415f3 --- /dev/null +++ b/src/northbridge/intel/x4x/spd_ddr2_decode.c @@ -0,0 +1,144 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2015 Damien Zammit <damien(a)zamaudio.com> + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#include <stdint.h> +#include <arch/io.h> +#include <spd.h> +#include <types.h> +#include <console/console.h> +#include <device/dram/ddr2.h> +#include "x4x.h" + +#define CTRL_MIN_TCLK_DDR2 TCK_400MHZ + +void select_cas_dramfreq_ddr2(struct sysinfo *s, + const struct abs_timings *saved_timings) +{ + u8 try_cas; + /* Currently only these CAS are supported */ + u8 cas_mask = SPD_CAS_LATENCY_DDR2_5 | SPD_CAS_LATENCY_DDR2_6; + + cas_mask &= saved_timings->cas_supported; + try_cas = spd_get_msbs(cas_mask); + + while (cas_mask & (1 << try_cas) && try_cas > 0) { + s->selected_timings.CAS = try_cas; + s->selected_timings.tclk = saved_timings->min_tCLK_cas[try_cas]; + if (s->selected_timings.tclk >= CTRL_MIN_TCLK_DDR2 && + saved_timings->min_tCLK_cas[try_cas] != + saved_timings->min_tCLK_cas[try_cas - 1]) + break; + try_cas--; + } + + + if ((s->selected_timings.CAS < 3) || (s->selected_timings.tclk == 0)) + die("Could not find common memory frequency and CAS\n"); + + switch (s->selected_timings.tclk) { + case TCK_200MHZ: + case TCK_266MHZ: + /* FIXME: this works on vendor BIOS */ + die("Selected dram frequency not supported\n"); + case TCK_333MHZ: + s->selected_timings.mem_clk = MEM_CLOCK_667MHz; + break; + case TCK_400MHZ: + s->selected_timings.mem_clk = MEM_CLOCK_800MHz; + break; + } +} + +int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, + struct abs_timings *saved_timings, struct sysinfo *s) +{ + struct dimm_attr_st decoded_dimm; + int i; + + if (spd_decode_ddr2(&decoded_dimm, raw_spd) != SPD_STATUS_OK) { + printk(BIOS_DEBUG, "Problems decoding SPD\n"); + return CB_ERR; + } + + if (IS_ENABLED(CONFIG_DEBUG_RAM_SETUP)) + dram_print_spd_ddr2(&decoded_dimm); + + if (!(decoded_dimm.width & (0x08 | 0x10))) { + printk(BIOS_ERR, + "DIMM%d Unsupported width: x%d. Disabling dimm\n", + dimm_idx, s->dimms[dimm_idx].width); + return CB_ERR; + } + s->dimms[dimm_idx].width = (decoded_dimm.width >> 3) - 1; + /* + * This boils down to: + * "Except for the x16 configuration, all DDR2 devices have a + * 1KB page size. For the x16 configuration, the page size is 2KB + * for all densities except the 256Mb device, which has a 1KB page + * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' + * The formula is pagesize in KiB = width * 2^col_bits / 8 + */ + s->dimms[dimm_idx].page_size = decoded_dimm.width * + (1 << decoded_dimm.col_bits) / 8; + + switch (decoded_dimm.banks) { + case 4: + s->dimms[dimm_idx].n_banks = N_BANKS_4; + break; + case 8: + s->dimms[dimm_idx].n_banks = N_BANKS_8; + break; + default: + printk(BIOS_ERR, + "DIMM%d Unsupported #banks: x%d. Disabling dimm\n", + dimm_idx, decoded_dimm.banks); + return CB_ERR; + } + + s->dimms[dimm_idx].ranks = decoded_dimm.ranks; + s->dimms[dimm_idx].rows = decoded_dimm.row_bits; + s->dimms[dimm_idx].cols = decoded_dimm.col_bits; + + saved_timings->cas_supported &= decoded_dimm.cas_supported; + + saved_timings->min_tRAS = + MAX(saved_timings->min_tRAS, decoded_dimm.tRAS); + saved_timings->min_tRP = + MAX(saved_timings->min_tRP, decoded_dimm.tRP); + saved_timings->min_tRCD = + MAX(saved_timings->min_tRCD, decoded_dimm.tRCD); + saved_timings->min_tWR = + MAX(saved_timings->min_tWR, decoded_dimm.tWR); + saved_timings->min_tRFC = + MAX(saved_timings->min_tRFC, decoded_dimm.tRFC); + saved_timings->min_tWTR = + MAX(saved_timings->min_tWTR, decoded_dimm.tWTR); + saved_timings->min_tRRD = + MAX(saved_timings->min_tRRD, decoded_dimm.tRRD); + saved_timings->min_tRTP = + MAX(saved_timings->min_tRTP, decoded_dimm.tRTP); + for (i = 0; i < 8; i++) { + if (!(saved_timings->cas_supported & (1 << i))) + saved_timings->min_tCLK_cas[i] = 0; + else + saved_timings->min_tCLK_cas[i] = + MAX(saved_timings->min_tCLK_cas[i], + decoded_dimm.cycle_time[i]); + } + s->dimms[dimm_idx].checksum = decoded_dimm.checksum; + return CB_SUCCESS; +} diff --git a/src/northbridge/intel/x4x/x4x.h b/src/northbridge/intel/x4x/x4x.h index b9e683b..4ac901c 100644 --- a/src/northbridge/intel/x4x/x4x.h +++ b/src/northbridge/intel/x4x/x4x.h @@ -354,6 +354,20 @@ CTRL3, }; +struct abs_timings { + u32 min_tclk; + u32 min_tRAS; + u32 min_tRP; + u32 min_tRCD; + u32 min_tWR; + u32 min_tRFC; + u32 min_tWTR; + u32 min_tRRD; + u32 min_tRTP; + u32 min_tCLK_cas[8]; + u32 cas_supported; +}; + #ifndef __BOOTBLOCK__ void x4x_early_init(void); void x4x_late_init(int s3resume); @@ -372,6 +386,10 @@ struct rt_dqs_setting *dqs_setting); int do_write_training(struct sysinfo *s); int do_read_training(struct sysinfo *s); +void select_cas_dramfreq_ddr2(struct sysinfo *s, + const struct abs_timings *saved_timings); +int ddr2_save_dimminfo(u8 dimm_idx, u8 *raw_spd, + struct abs_timings *saved_timings, struct sysinfo *s); extern const struct dll_setting default_ddr2_667_ctrl[7]; extern const struct dll_setting default_ddr2_800_ctrl[7]; -- To view, visit https://review.coreboot.org/22992 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I965fb8261c14381a35b361df2a3b40a9ea192669 Gerrit-Change-Number: 22992 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: nb/intel/x4x/raminit: Support programming initials DD3 DLL setting
by Arthur Heymans (Code Review) 26 Dec '17

26 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22993 Change subject: nb/intel/x4x/raminit: Support programming initials DD3 DLL setting ...................................................................... nb/intel/x4x/raminit: Support programming initials DD3 DLL setting Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 205 insertions(+), 59 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/93/22993/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 5ad4453..a4b11d5 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -583,7 +583,8 @@ MCHBAR16(0x400*i + 0x25b) = ((s->selected_timings.tRP + trpmod) << 9) | s->selected_timings.tRFC; - MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) | (100 << 1); + MCHBAR16(0x400*i + 0x260) = (MCHBAR16(0x400*i + 0x260) & ~0x3fe) + | ((s->spd_type == DDR2 ? 100 : 256) << 1); MCHBAR8(0x400*i + 0x264) = 0xff; MCHBAR8(0x400*i + 0x25d) = (MCHBAR8(0x400*i + 0x25d) & ~0x3f) | s->selected_timings.tRAS; @@ -636,18 +637,32 @@ MCHBAR8(0x400*i + 0x24c) = MCHBAR8(0x400*i + 0x24c) & ~0x3; reg16 = 0; - switch (s->selected_timings.mem_clk) { - default: - case MEM_CLOCK_667MHz: - reg16 = 0x99; - break; - case MEM_CLOCK_800MHz: - if (s->selected_timings.CAS == 5) - reg16 = 0x19a; - else if (s->selected_timings.CAS == 6) - reg16 = 0x9a; - break; + if (s->spd_type == DDR2) { + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_667MHz: + reg16 = 0x99; + break; + case MEM_CLOCK_800MHz: + if (s->selected_timings.CAS == 5) + reg16 = 0x19a; + else if (s->selected_timings.CAS == 6) + reg16 = 0x9a; + break; + } + } else { /* DDR3 */ + switch (s->selected_timings.mem_clk) { + default: + case MEM_CLOCK_800MHz: + case MEM_CLOCK_1066MHz: + reg16 = 1; + break; + case MEM_CLOCK_1333MHz: + reg16 = 2; + break; + } } + reg16 &= 0x7; reg16 += twl + 9; reg16 <<= 10; @@ -683,6 +698,13 @@ MCHBAR8(0x12d) = (MCHBAR8(0x12d) & ~0xf) | reg8; MCHBAR8(0x12f) = 0x4c; reg32 = (1 << 31) | (0x80 << 14) | (1 << 13) | (0xa << 9); + if (s->spd_type == DDR3) { + MCHBAR8(0x114) = 0x42; + reg16 = (512 - MAX(5, s->selected_timings.tRFC + + 10000 / ddr2ps[s->selected_timings.mem_clk])) / 2; + reg16 &= 0x1ff; + reg32 = (reg16 << 22) | (0x80 << 14) | (0xa << 9); + } MCHBAR32(0x6c0) = (MCHBAR32(0x6c0) & ~0xffffff00) | reg32; MCHBAR8(0x6c4) = (MCHBAR8(0x6c4) & ~0x7) | 0x2; } @@ -693,6 +715,9 @@ u16 reg16 = 0; u32 reg32 = 0; + const u8 rank2clken[8] = { 0x04, 0x01, 0x20, 0x08, 0x01, 0x04, + 0x08, 0x10 }; + MCHBAR16(0x180) = (MCHBAR16(0x180) & ~0x7e06) | 0xc04; MCHBAR16(0x182) = (MCHBAR16(0x182) & ~0x3ff) | 0xc8; MCHBAR16(0x18a) = (MCHBAR16(0x18a) & ~0x1f1f) | 0x0f0f; @@ -701,11 +726,15 @@ switch (s->selected_timings.mem_clk) { default: case MEM_CLOCK_667MHz: + case MEM_CLOCK_1333MHz: reg16 = (0xa << 9) | 0xa; break; case MEM_CLOCK_800MHz: reg16 = (0x9 << 9) | 0x9; break; + case MEM_CLOCK_1066MHz: + reg16 = (0x7 << 9) | 0x7; + break; } MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x1e0f) | reg16; MCHBAR16(0x19c) = (MCHBAR16(0x19c) & ~0x2030) | 0x2010; @@ -729,14 +758,26 @@ udelay(1); // 533ns // ME related - MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) | 0x551803; + MCHBAR32(0x1a0) = (MCHBAR32(0x1a0) & ~0x7ffffff) + | (s->spd_type == DDR2 ? 0x551803 : 0x555801); MCHBAR16(0x1b4) = MCHBAR16(0x1b4) & ~0x800; - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; + if (s->spd_type == DDR2) { + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0xf0; + } else { /* DDR3 */ + reg8 = 0x9; /* 0x9 << 4 ?? */ + if (s->dimms[0].ranks == 2) + reg8 &= ~0x80; + if (s->dimms[3].ranks == 2) + reg8 &= ~0x10; + MCHBAR8(0x1a8) = (MCHBAR8(0x1a8) & ~0xf0) | reg8; + } FOR_EACH_CHANNEL(i) { reg16 = 0; - MCHBAR16(0x400*i + 0x59c) = MCHBAR16(0x400*i + 0x59c) & ~0x3000; + if ((s->spd_type == DDR3) && (i == 0)) + reg16 = (0x3 << 12); + MCHBAR16(0x400*i + 0x59c) = (MCHBAR16(0x400*i + 0x59c) & ~0x3000) | reg16; reg32 = 0; FOR_EACH_RANK_IN_CHANNEL(r) { @@ -747,30 +788,49 @@ MCHBAR32(0x400*i + 0x59c) = (MCHBAR32(0x400*i + 0x59c) & ~0xfff) | reg32; MCHBAR8(0x400*i + 0x594) = MCHBAR8(0x400*i + 0x594) & ~1; - if (!CHANNEL_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, "No dimms in channel %d\n", i); - reg8 = 0x3f; - } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, "DimmA populated only in channel %d\n", i); - reg8 = 0x38; - } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, "DimmB populated only in channel %d\n", i); - reg8 = 0x7; - } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { - printk(BIOS_DEBUG, "Both dimms populated in channel %d\n", i); - reg8 = 0; - } else { - die("Unhandled case\n"); + if (s->spd_type == DDR2) { + if (!CHANNEL_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, + "No dimms in channel %d\n", i); + reg8 = 0x3f; + } else if (ONLY_DIMMA_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, + "DimmA populated only in channel %d\n", + i); + reg8 = 0x38; + } else if (ONLY_DIMMB_IS_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, + "DimmB populated only in channel %d\n", + i); + reg8 = 0x7; + } else if (BOTH_DIMMS_ARE_POPULATED(s->dimms, i)) { + printk(BIOS_DEBUG, + "Both dimms populated in channel %d\n", + i); + reg8 = 0; + } else { + die("Unhandled case\n"); + } + MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) + & ~0x3f000000) | ((u32)(reg8 << 24)); + + } else { /* DDR3 */ + FOR_EACH_POPULATED_RANK_IN_CHANNEL(s->dimms, i, r) { + MCHBAR8(0x400 * i + 0x5a0 + 3) = MCHBAR8(0x400 * i + 0x5a0 + 3) + & ~rank2clken[r + i * 4]; + } } //reg8 = 0x00; // FIXME don't switch on all clocks anyway - - MCHBAR32(0x400*i + 0x5a0) = (MCHBAR32(0x400*i + 0x5a0) & ~0x3f000000) | - ((u32)(reg8 << 24)); } // END EACH CHANNEL - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; - MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + if (s->spd_type == DDR2) { + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 1; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~0x4; + } else { /* DDR3 */ + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) & ~1; + MCHBAR8(0x1a8) = MCHBAR8(0x1a8) | 0x4; + } // Update DLL timing MCHBAR8(0x1a4) = MCHBAR8(0x1a4) & ~0x80; @@ -780,12 +840,16 @@ FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { MCHBAR16(0x400*i + 0x5f0) = (MCHBAR16(0x400*i + 0x5f0) & ~0x3fc) | 0x3fc; MCHBAR32(0x400*i + 0x5fc) = MCHBAR32(0x400*i + 0x5fc) & ~0xcccccccc; - MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) | 0x70; - MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) | 0x5555; + MCHBAR8(0x400*i + 0x5d9) = (MCHBAR8(0x400*i + 0x5d9) & ~0xf0) + | (s->spd_type == DDR2 ? 0x70 : 0x60); + MCHBAR16(0x400*i + 0x590) = (MCHBAR16(0x400*i + 0x590) & ~0xffff) + | (s->spd_type == DDR2 ? 0x5555 : 0xa955); } FOR_EACH_POPULATED_CHANNEL(s->dimms, i) { - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz) { + switch(s->selected_timings.mem_clk) { + default: /* Should not happen */ + case MEM_CLOCK_667MHz: clkset0(i, &default_ddr2_667_ctrl[CLKSET0]); clkset1(i, &default_ddr2_667_ctrl[CLKSET1]); ctrlset0(i, &default_ddr2_667_ctrl[CTRL0]); @@ -793,14 +857,65 @@ ctrlset2(i, &default_ddr2_667_ctrl[CTRL2]); ctrlset3(i, &default_ddr2_667_ctrl[CTRL3]); cmdset(i, &default_ddr2_667_ctrl[CMD]); - } else { - clkset0(i, &default_ddr2_800_ctrl[CLKSET0]); - clkset1(i, &default_ddr2_800_ctrl[CLKSET1]); - ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]); - ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]); - ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]); - ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]); - cmdset(i, &default_ddr2_800_ctrl[CMD]); + break; + case MEM_CLOCK_800MHz: + if (s->spd_type == DDR2) { + clkset0(i, &default_ddr2_800_ctrl[CLKSET0]); + clkset1(i, &default_ddr2_800_ctrl[CLKSET1]); + ctrlset0(i, &default_ddr2_800_ctrl[CTRL0]); + ctrlset1(i, &default_ddr2_800_ctrl[CTRL1]); + ctrlset2(i, &default_ddr2_800_ctrl[CTRL2]); + ctrlset3(i, &default_ddr2_800_ctrl[CTRL3]); + cmdset(i, &default_ddr2_800_ctrl[CMD]); + } else { /* DDR3 */ + clkset0(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CLKSET0]); + clkset1(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CLKSET1]); + ctrlset0(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CTRL0]); + ctrlset1(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CTRL1]); + ctrlset2(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CTRL2]); + ctrlset3(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CTRL3]); + cmdset(i, &default_ddr3_800_ctrl[s->nmode - 1] + [CMD]); + } + break; + case MEM_CLOCK_1066MHz: + clkset0(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CLKSET0]); + clkset1(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CLKSET1]); + ctrlset0(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CTRL0]); + ctrlset1(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CTRL1]); + ctrlset2(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CTRL2]); + ctrlset3(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CTRL3]); + cmdset(i, &default_ddr3_1067_ctrl[s->nmode - 1] + [CMD]); + break; + case MEM_CLOCK_1333MHz: + clkset0(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CLKSET0]); + clkset1(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CLKSET1]); + ctrlset0(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CTRL0]); + ctrlset1(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CTRL1]); + ctrlset2(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CTRL2]); + ctrlset3(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CTRL3]); + cmdset(i, &default_ddr3_1333_ctrl[s->nmode - 1] + [CMD]); + break; } } @@ -867,23 +982,39 @@ } clk = 0x1a; + if (s->selected_timings.mem_clk == MEM_CLOCK_1333MHz) + clk = 0x18; if (async != 1) { reg8 = MCHBAR8(0x188) & 0x1e; - if (s->selected_timings.mem_clk == MEM_CLOCK_667MHz && - s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) { - clk = 0x10; - } else if (s->selected_timings.mem_clk == MEM_CLOCK_800MHz) { - clk = 0x10; - } else { + switch (s->selected_timings.mem_clk) { + case MEM_CLOCK_667MHz: clk = 0x1a; + if (s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) + clk = 0x10; + break; + case MEM_CLOCK_800MHz: + case MEM_CLOCK_1066MHz: + clk = 0x10; + break; + case MEM_CLOCK_1333MHz: + clk = 0x18; + break; + default: + clk = 0x1a; + break; } } + MCHBAR8(0x180) = MCHBAR8(0x180) & ~0x80; - if ((s->selected_timings.fsb_clk == FSB_CLOCK_800MHz) && - (s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { + if ((s->spd_type == DDR3 && s->selected_timings.mem_clk == MEM_CLOCK_1066MHz) + || (s->spd_type == DDR2 && s->selected_timings.fsb_clk == FSB_CLOCK_800MHz + && s->selected_timings.mem_clk == MEM_CLOCK_667MHz)) { i = MCHBAR8(0x1c8) & 0xf; - i = (i + 10) % 14; + if (s->spd_type == DDR2) + i = (i + 10) % 14; + else /* DDR3 */ + i = (i + 3) % 12; MCHBAR8(0x1c8) = (MCHBAR8(0x1c8) & ~0x1f) | i; MCHBAR8(0x180) = MCHBAR8(0x180) | 0x10; while (MCHBAR8(0x180) & 0x10) @@ -929,18 +1060,33 @@ s->rt_dqs[ch][lane].tap = 7; s->rt_dqs[ch][lane].pi = 0; } else { /* DDR3 */ - /* TODO: DDR3 write DQ-DQS */ + memcpy(s->dqs_settings[ch], + default_ddr3_800_dqs[s->nmode - 1], + sizeof(s->dqs_settings[ch])); + memcpy(s->dq_settings[ch], + default_ddr3_800_dq[s->nmode - 1], + sizeof(s->dq_settings[ch])); s->rt_dqs[ch][lane].tap = 6; - s->rt_dqs[ch][lane].pi = 2; + s->rt_dqs[ch][lane].pi = 3; } break; case MEM_CLOCK_1066MHz: - /* TODO: DDR3 write DQ-DQS */ + memcpy(s->dqs_settings[ch], + default_ddr3_1067_dqs[s->nmode - 1], + sizeof(s->dqs_settings[ch])); + memcpy(s->dq_settings[ch], + default_ddr3_1067_dq[s->nmode - 1], + sizeof(s->dq_settings[ch])); s->rt_dqs[ch][lane].tap = 5; - s->rt_dqs[ch][lane].pi = 2; + s->rt_dqs[ch][lane].pi = 3; break; case MEM_CLOCK_1333MHz: - /* TODO: DDR3 write DQ-DQS */ + memcpy(s->dqs_settings[ch], + default_ddr3_1333_dqs[s->nmode - 1], + sizeof(s->dqs_settings[ch])); + memcpy(s->dq_settings[ch], + default_ddr3_1333_dq[s->nmode - 1], + sizeof(s->dq_settings[ch])); s->rt_dqs[ch][lane].tap = 7; s->rt_dqs[ch][lane].pi = 0; break; -- To view, visit https://review.coreboot.org/22993 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I67e48b4ae6f2076399133ba7b98ab1dfc0e0ab08 Gerrit-Change-Number: 22993 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Fix computing page_size
by Arthur Heymans (Code Review) 26 Dec '17

26 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22991 Change subject: nb/intel/x4x: Fix computing page_size ...................................................................... nb/intel/x4x: Fix computing page_size This problem was introduced by 3cf94032b "nb/x4x/raminit: Rewrite SPD decode and timing selection", but was probably not encountered because such dimms are rather uncommon. Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/22991/1 diff --git a/src/northbridge/intel/x4x/raminit.c b/src/northbridge/intel/x4x/raminit.c index 0b4d4a5..3cd75be 100644 --- a/src/northbridge/intel/x4x/raminit.c +++ b/src/northbridge/intel/x4x/raminit.c @@ -188,9 +188,10 @@ * 1KB page size. For the x16 configuration, the page size is 2KB * for all densities except the 256Mb device, which has a 1KB page * size." Micron, 'TN-47-16 Designing for High-Density DDR2 Memory' + * The formula is pagesize in KiB = width * 2^col_bits / 8. */ - s->dimms[dimm_idx].page_size = s->dimms[dimm_idx].width * - (1 << decoded_dimm.col_bits); + s->dimms[dimm_idx].page_size = decoded_dimm.width * + (1 << decoded_dimm.col_bits) / 8; switch (decoded_dimm.banks) { case 4: -- To view, visit https://review.coreboot.org/22991 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I2d57f5e584ac7fa1479791c239432005fe8c178d Gerrit-Change-Number: 22991 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table
by build bot (Jenkins) (Code Review) 26 Dec '17

26 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22990 ) Change subject: amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table ...................................................................... Patch Set 2: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19768/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65011/ : SUCCESS -- To view, visit https://review.coreboot.org/22990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd Gerrit-Change-Number: 22990 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Aaron Durbin <adurbin(a)chromium.org> Gerrit-Reviewer: Marc Jones <marc(a)marcjonesconsulting.com> Gerrit-Reviewer: Martin Roth <martinroth(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 19:21:17 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22990 to look at the new patch set (#2). Change subject: amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table ...................................................................... amd/gardenia/bootblock/BiosCallOuts.c: Replace GPIO table As function platform_FchParams_reset() is no longer called or declared, it needs to be removed. Replace GPIO table with the new format, and platform_FchParams_reset() with new function board_get_gpio(). BUG=b:64140392 TEST=Build gardenia. Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c 1 file changed, 15 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/22990/2 -- To view, visit https://review.coreboot.org/22990 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Id2ea63656a7d2f20f55fc5a4c75457db85b80cbd Gerrit-Change-Number: 22990 Gerrit-PatchSet: 2 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset
by build bot (Jenkins) (Code Review) 26 Dec '17

26 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22989 ) Change subject: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset ...................................................................... Patch Set 5: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19767/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65010/ : SUCCESS -- To view, visit https://review.coreboot.org/22989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Gerrit-Change-Number: 22989 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 19:06:10 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/22989 to look at the new patch set (#5). Change subject: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset ...................................................................... google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset Function platform_FchParams_reset() is now an empty function, remove it, its header declaration and its use. BUG=b:64140392 TEST=Build kahlee. Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Signed-off-by: Richard Spiegel <richard.spiegel(a)silverbackltd.com> --- M src/mainboard/amd/gardenia/bootblock/BiosCallOuts.c M src/mainboard/google/kahlee/BiosCallOuts.c M src/soc/amd/common/block/include/amdblocks/BiosCallOuts.h M src/soc/amd/stoneyridge/BiosCallOuts.c 4 files changed, 32 insertions(+), 38 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/89/22989/5 -- To view, visit https://review.coreboot.org/22989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Gerrit-Change-Number: 22989 Gerrit-PatchSet: 5 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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Change in coreboot[master]: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset
by Richard Spiegel (Code Review) 26 Dec '17

26 Dec '17

Richard Spiegel has posted comments on this change. ( https://review.coreboot.org/22989 ) Change subject: google/kahlee/BiosCallOuts.c: Remove platform_FchParams_reset ...................................................................... Patch Set 4: Now I do not understand the failure. It builds gardenia locally, but Jenkins fails gardenia. Investigating. -- To view, visit https://review.coreboot.org/22989 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I3f3efc072a2e198433d0e261dacbbd4a8ff327d7 Gerrit-Change-Number: 22989 Gerrit-PatchSet: 4 Gerrit-Owner: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: Richard Spiegel <richard.spiegel(a)silverbackltd.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 18:35:34 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit December 2017