coreboot-gerrit December 2017

coreboot-gerrit@coreboot.org

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Change in coreboot[master]: nb/intel/x4x: Limit DDR3 speed to 400MHz
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22998 ) Change subject: nb/intel/x4x: Limit DDR3 speed to 400MHz ...................................................................... Patch Set 1: No Builds Executed -- To view, visit https://review.coreboot.org/22998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I11f663a50a42c70ed63ba045bd89fcd96cd047ce Gerrit-Change-Number: 22998 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:33:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22997 ) Change subject: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout ...................................................................... Patch Set 1: No Builds Executed -- To view, visit https://review.coreboot.org/22997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Gerrit-Change-Number: 22997 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:33:38 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout
by Arthur Heymans (Code Review) 27 Dec '17

27 Dec '17

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/22997 ) Change subject: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout ...................................................................... nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. This moves disabling the watchdog reboot to the northbridge code like i945 (even though it technically is southbridge stuff). TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/mainboard/asrock/g41c-gs/romstage.c M src/mainboard/foxconn/g41s-k/romstage.c M src/mainboard/gigabyte/ga-g41m-es2l/romstage.c M src/mainboard/intel/dg43gt/romstage.c M src/northbridge/intel/x4x/early_init.c M src/southbridge/intel/i82801jx/i82801jx.h 6 files changed, 8 insertions(+), 12 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22997/2 -- To view, visit https://review.coreboot.org/22997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Gerrit-Change-Number: 22997 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Fix programming CxDRB
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22911 ) Change subject: nb/intel/x4x: Fix programming CxDRB ...................................................................... Patch Set 5: Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19773/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65016/ : SUCCESS -- To view, visit https://review.coreboot.org/22911 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I7ff3264824c843f84b9eb6c06a06aa3f151fe4b3 Gerrit-Change-Number: 22911 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:33:15 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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Change in coreboot[master]: nb/intel/x4x: Refactor setting default dll settings
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22327 ) Change subject: nb/intel/x4x: Refactor setting default dll settings ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19769/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65012/ : SUCCESS -- To view, visit https://review.coreboot.org/22327 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I0e3676e06586ea84fc0729469946dbc9a8225934 Gerrit-Change-Number: 22327 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:31:21 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Implement both read and write training
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22329 ) Change subject: nb/intel/x4x: Implement both read and write training ...................................................................... Patch Set 10: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19772/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65015/ : SUCCESS -- To view, visit https://review.coreboot.org/22329 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iacdc63b91b4705d1a80437314bfe55385ea5b6c1 Gerrit-Change-Number: 22329 Gerrit-PatchSet: 10 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:29:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Clarify the raminit memory mapping
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22328 ) Change subject: nb/intel/x4x: Clarify the raminit memory mapping ...................................................................... Patch Set 8: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19770/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65013/ : SUCCESS -- To view, visit https://review.coreboot.org/22328 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I58923e4a8a756f4ae65f759e7d46e03fad39fab7 Gerrit-Change-Number: 22328 Gerrit-PatchSet: 8 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Tue, 26 Dec 2017 23:27:16 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: nb/intel/x4x: Limit DDR3 speed to 400MHz
by Arthur Heymans (Code Review) 27 Dec '17

27 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22998 Change subject: nb/intel/x4x: Limit DDR3 speed to 400MHz ...................................................................... nb/intel/x4x: Limit DDR3 speed to 400MHz Faster speeds seem to work much worse compatibility wise with this code. Change-Id: I11f663a50a42c70ed63ba045bd89fcd96cd047ce Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/spd_ddr3_decode.c 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/22998/1 diff --git a/src/northbridge/intel/x4x/spd_ddr3_decode.c b/src/northbridge/intel/x4x/spd_ddr3_decode.c index a57b14c..35d6bf6 100644 --- a/src/northbridge/intel/x4x/spd_ddr3_decode.c +++ b/src/northbridge/intel/x4x/spd_ddr3_decode.c @@ -86,6 +86,7 @@ } min_tCLK = MAX(min_tCLK, saved_timings->min_tclk); + min_tCLK = TCK_400MHZ; /* TODO: other speedsseem to fail */ normalize_tCLK(&min_tCLK); if (min_tCLK == 0) { printk(BIOS_ERR, "DRAM frequency is under lowest supported " -- To view, visit https://review.coreboot.org/22998 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11f663a50a42c70ed63ba045bd89fcd96cd047ce Gerrit-Change-Number: 22998 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout
by Arthur Heymans (Code Review) 27 Dec '17

27 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22997 Change subject: nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout ...................................................................... nb/intel/x4x: Disable watchdog, halt TCO timer and clear timeout Especially on ICH7 failing to do so results in i2c block read being unusable. On ICH10 this problem doesn't manifest itself that much. TESTED on Intel DG41WV: hacking on raminit is much nicer since no need to do a hard power down for +4s are needed to clear the timeouts. Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/early_init.c M src/southbridge/intel/i82801jx/i82801jx.h 2 files changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/97/22997/1 diff --git a/src/northbridge/intel/x4x/early_init.c b/src/northbridge/intel/x4x/early_init.c index cd11dd9..da79cb7 100644 --- a/src/northbridge/intel/x4x/early_init.c +++ b/src/northbridge/intel/x4x/early_init.c @@ -58,6 +58,13 @@ pci_write_config8(d0f0, D0F0_PAM(5), 0x33); pci_write_config8(d0f0, D0F0_PAM(6), 0x33); + printk(BIOS_DEBUG, "Disabling Watchdog reboot..."); + RCBA32(GCS) = RCBA32(GCS) | (1 << 5); /* No reset */ + outw((1 << 11), DEFAULT_PMBASE | 0x60 | 0x08); /* halt timer */ + outw((1 << 3), DEFAULT_PMBASE | 0x60 | 0x04); /* clear timeout */ + outw((1 << 1), DEFAULT_PMBASE | 0x60 | 0x06); /* clear 2nd timeout */ + printk(BIOS_DEBUG, " done.\n"); + if (!(pci_read_config32(d0f0, D0F0_CAPID0 + 4) & (1 << (46 - 32)))) { /* Enable internal GFX */ pci_write_config32(d0f0, D0F0_DEVEN, BOARD_DEVEN); diff --git a/src/southbridge/intel/i82801jx/i82801jx.h b/src/southbridge/intel/i82801jx/i82801jx.h index 9b0f955..88e0ad0 100644 --- a/src/southbridge/intel/i82801jx/i82801jx.h +++ b/src/southbridge/intel/i82801jx/i82801jx.h @@ -166,6 +166,7 @@ #define RCBA_RPFN 0x0238 #define RCBA_DMC 0x2010 #define RCBA_HPTC 0x3404 +#define GCS 0x3410 #define RCBA_BUC 0x3414 #define RCBA_FD 0x3418 /* Function Disable, see below. */ #define RCBA_CG 0x341c -- To view, visit https://review.coreboot.org/22997 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Icfd3789312704f61000a417f23a121d02d2e7fbe Gerrit-Change-Number: 22997 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings
by Arthur Heymans (Code Review) 27 Dec '17

27 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22996 Change subject: nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings ...................................................................... nb/intel/x4x/raminit: Add DDR3 specific dra/drb settings Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/northbridge/intel/x4x/raminit_ddr23.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/22996/1 diff --git a/src/northbridge/intel/x4x/raminit_ddr23.c b/src/northbridge/intel/x4x/raminit_ddr23.c index 13b98ee..8110a1e 100644 --- a/src/northbridge/intel/x4x/raminit_ddr23.c +++ b/src/northbridge/intel/x4x/raminit_ddr23.c @@ -1618,6 +1618,14 @@ MCHBAR8(0x262) = (MCHBAR8(0x262) & ~0xf0) | ((rankpop0 << 4) & 0xf0); MCHBAR8(0x662) = (MCHBAR8(0x662) & ~0xf0) | ((rankpop1 << 4) & 0xf0); + if (s->spd_type == DDR3) { + FOR_EACH_POPULATED_CHANNEL(s->dimms, ch) { + /* ZQCAL enable */ + MCHBAR32(0x269 + 0x400 * ch) = + MCHBAR32(0x269 + 0x400 * ch) | (1 << 26); + } + } + if (ONLY_DIMMA_IS_POPULATED(s->dimms, 0) || ONLY_DIMMB_IS_POPULATED(s->dimms, 0)) MCHBAR8(0x260) = MCHBAR8(0x260) | 1; -- To view, visit https://review.coreboot.org/22996 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I11a79f6800dbfe19c2bd33c0d6caca14b034e384 Gerrit-Change-Number: 22996 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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coreboot-gerrit December 2017