coreboot-gerrit December 2017

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Change in coreboot[master]: sb/intel/i82801ix: Use the common ACPI pirq generator
by Arthur Heymans (Code Review) 23 Dec '17

23 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22980 Change subject: sb/intel/i82801ix: Use the common ACPI pirq generator ...................................................................... sb/intel/i82801ix: Use the common ACPI pirq generator For this to work the northbridge and lpc bridge device need acpi_name functions. This also needs DEFAULT_RCBA being configured in Kconfig. Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- D src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl D src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl D src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl M src/northbridge/intel/gm45/acpi/hostbridge.asl M src/northbridge/intel/gm45/northbridge.c M src/southbridge/intel/i82801ix/Kconfig M src/southbridge/intel/i82801ix/i82801ix.h M src/southbridge/intel/i82801ix/lpc.c 8 files changed, 32 insertions(+), 245 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/22980/1 diff --git a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl deleted file mode 100644 index aefdf94..0000000 --- a/src/mainboard/lenovo/t400/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Onboard GbE - Package() { 0x0019ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard GbE - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl b/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl deleted file mode 100644 index aefdf94..0000000 --- a/src/mainboard/lenovo/x200/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // Onboard GbE - Package() { 0x0019ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - Package() { 0x001cffff, 1, 0, 17 }, - Package() { 0x001cffff, 2, 0, 18 }, - Package() { 0x001cffff, 3, 0, 19 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard GbE - Package() { 0x0019ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001cffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001cffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - Package() { 0x001cffff, 3, \_SB.PCI0.LPCB.LNKD, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // LPC bridge sub devices 0:1f.x - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl b/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl deleted file mode 100644 index 4a9ede8..0000000 --- a/src/mainboard/roda/rk9/acpi/gm45_pci_irqs.asl +++ /dev/null @@ -1,80 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2009 coresystems GmbH - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; version 2 of - * the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -/* This is board specific information: IRQ routing for the - * gm45 - */ - - -// PCI Interrupt Routing -Method(_PRT) -{ - If (PICM) { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, 0, 16 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, 0, 16 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, 0, 16 }, - Package() { 0x001affff, 1, 0, 17 }, - Package() { 0x001affff, 2, 0, 18 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, 0, 16 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, 0, 16 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, 0, 16 }, - Package() { 0x001dffff, 1, 0, 17 }, - Package() { 0x001dffff, 2, 0, 18 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, 0, 22 }, - // Package() { 0x001effff, 1, 0, 20 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, 0, 16 }, - Package() { 0x001fffff, 1, 0, 17 }, - Package() { 0x001fffff, 2, 0, 18 } - }) - } Else { - Return (Package() { - // PCIe Graphics 0:1.0 - Package() { 0x0001ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // Onboard graphics (IGD) 0:2.0 - Package() { 0x0002ffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1a.x - Package() { 0x001affff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001affff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001affff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // High Definition Audio 0:1b.0 - Package() { 0x001bffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // PCIe Root Ports 0:1c.x - Package() { 0x001cffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - // USB and EHCI 0:1d.x - Package() { 0x001dffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001dffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001dffff, 2, \_SB.PCI0.LPCB.LNKC, 0 }, - // FIXME - // CardBus/IEEE1394 0:1e.2, 0:1e.3 - // Package() { 0x001effff, 0, \_SB.PCI0.LPCB.LNKG, 0 }, - // Package() { 0x001effff, 1, \_SB.PCI0.LPCB.LNKE, 0 }, - // LPC device 0:1f.0 - Package() { 0x001fffff, 0, \_SB.PCI0.LPCB.LNKA, 0 }, - Package() { 0x001fffff, 1, \_SB.PCI0.LPCB.LNKB, 0 }, - Package() { 0x001fffff, 2, \_SB.PCI0.LPCB.LNKC, 0 } - }) - } -} diff --git a/src/northbridge/intel/gm45/acpi/hostbridge.asl b/src/northbridge/intel/gm45/acpi/hostbridge.asl index c674df5..afa7a61 100644 --- a/src/northbridge/intel/gm45/acpi/hostbridge.asl +++ b/src/northbridge/intel/gm45/acpi/hostbridge.asl @@ -228,6 +228,3 @@ Return (MCRS) } - -/* IRQ assignment is mainboard specific. Get it from mainboard ACPI code */ -#include "acpi/gm45_pci_irqs.asl" diff --git a/src/northbridge/intel/gm45/northbridge.c b/src/northbridge/intel/gm45/northbridge.c index 8215979..431d98d 100644 --- a/src/northbridge/intel/gm45/northbridge.c +++ b/src/northbridge/intel/gm45/northbridge.c @@ -186,6 +186,22 @@ pci_write_config32(dev, PCI_COMMAND, reg32); } +static const char *northbridge_acpi_name(const struct device *dev) +{ + if (dev->path.type == DEVICE_PATH_DOMAIN) + return "PCI0"; + + if (dev->path.type != DEVICE_PATH_PCI) + return NULL; + + switch (dev->path.pci.devfn) { + case PCI_DEVFN(0, 0): + return "MCHC"; + } + + return NULL; +} + static struct device_operations pci_domain_ops = { .read_resources = mch_domain_read_resources, .set_resources = mch_domain_set_resources, @@ -195,6 +211,7 @@ .ops_pci_bus = pci_bus_default_ops, .write_acpi_tables = northbridge_write_acpi_tables, .acpi_fill_ssdt_generator = generate_cpu_entries, + .acpi_name = northbridge_acpi_name, }; diff --git a/src/southbridge/intel/i82801ix/Kconfig b/src/southbridge/intel/i82801ix/Kconfig index 6879bce..2752e7a 100644 --- a/src/southbridge/intel/i82801ix/Kconfig +++ b/src/southbridge/intel/i82801ix/Kconfig @@ -18,6 +18,7 @@ bool select SOUTHBRIDGE_INTEL_COMMON select SOUTHBRIDGE_INTEL_COMMON_SMBUS + select SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ select IOAPIC select HAVE_USBDEBUG select HAVE_HARD_RESET @@ -33,6 +34,10 @@ hex default 0xfef00000 +config DEFAULT_RCBA + hex + default 0xfed1c000 + config HPET_MIN_TICKS hex default 0x80 diff --git a/src/southbridge/intel/i82801ix/i82801ix.h b/src/southbridge/intel/i82801ix/i82801ix.h index 38dfa38..90e8953 100644 --- a/src/southbridge/intel/i82801ix/i82801ix.h +++ b/src/southbridge/intel/i82801ix/i82801ix.h @@ -26,9 +26,9 @@ #define DEFAULT_TBAR ((u8 *)0xfed1b000) #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_DEFAULT_RCBA) #else -#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_RCBA CONFIG_DEFAULT_RCBA #endif #if IS_ENABLED(CONFIG_BOARD_EMULATION_QEMU_X86_Q35) diff --git a/src/southbridge/intel/i82801ix/lpc.c b/src/southbridge/intel/i82801ix/lpc.c index bc45b9d..dc582c9 100644 --- a/src/southbridge/intel/i82801ix/lpc.c +++ b/src/southbridge/intel/i82801ix/lpc.c @@ -34,6 +34,7 @@ #include "nvs.h" #include <southbridge/intel/common/pciehp.h> #include <drivers/intel/gma/i915.h> +#include <southbridge/intel/common/acpi_pirq_gen.h> #define NMI_OFF 0 @@ -558,12 +559,18 @@ } } +static const char *lpc_acpi_name(const struct device *dev) +{ + return "LPCB"; +} + static void southbridge_fill_ssdt(device_t device) { device_t dev = dev_find_slot(0, PCI_DEVFN(0x1f,0)); config_t *chip = dev->chip_info; intel_acpi_pcie_hotplug_generator(chip->pcie_hotplug_map, 8); + intel_acpi_gen_def_acpi_pirq(device); } static struct pci_operations pci_ops = { @@ -577,6 +584,7 @@ .acpi_inject_dsdt_generator = southbridge_inject_dsdt, .write_acpi_tables = acpi_write_hpet, .acpi_fill_ssdt_generator = southbridge_fill_ssdt, + .acpi_name = lpc_acpi_name, .init = lpc_init, .scan_bus = scan_lpc_bus, .ops_pci = &pci_ops, -- To view, visit https://review.coreboot.org/22980 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I62e520f53fa3f928a8e6f3b3cf33af2acdd53ed9 Gerrit-Change-Number: 22980 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22979 ) Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... Patch Set 3: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19725/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64965/ : SUCCESS -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 22:11:39 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by Arthur Heymans (Code Review) 23 Dec '17

23 Dec '17

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/22979 to look at the new patch set (#3). Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... src/sb/intel/common/pirq_gen: Fix some issues A few thing that are fixed: * Don't declare DEFAULT_RCBA redundantly. * Only loop over PCI devices on bus 0 * Add a license header to rcba_pirq.c * Remove inappropriate use of typedefs Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 6 files changed, 51 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22979/3 -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22979 ) Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19724/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64964/ : SUCCESS -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 21:19:11 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by Arthur Heymans (Code Review) 23 Dec '17

23 Dec '17

Hello build bot (Jenkins), Nico Huber, I'd like you to reexamine a change. Please visit https://review.coreboot.org/22979 to look at the new patch set (#2). Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... src/sb/intel/common/pirq_gen: Fix some issues A few thing that are fixed: * Don't declare DEFAULT_RCBA redundantly. * Only loop over PCI devices on bus 0 * Add a license header to rcba_pirq.c * Remove inappropriate use of typedefs Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 6 files changed, 52 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22979/2 -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22979 ) Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... Patch Set 1: Verified-1 Build Unstable https://qa.coreboot.org/job/coreboot-gerrit/64963/ : UNSTABLE https://qa.coreboot.org/job/coreboot-checkpatch/19723/ : SUCCESS -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 21:04:06 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

1 0

Change in coreboot[master]: src/sb/intel/common/pirq_gen: Fix some issues
by Arthur Heymans (Code Review) 23 Dec '17

23 Dec '17

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/22979 Change subject: src/sb/intel/common/pirq_gen: Fix some issues ...................................................................... src/sb/intel/common/pirq_gen: Fix some issues A few thing that are fixed: * Don't declare DEFAULT_RCBA redundantly. * Only loop over PCI devices on bus 0 * Add a license header to rcba_pirq.c * Remove inappropriate use of typedefs Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> --- M src/southbridge/intel/bd82x6x/Kconfig M src/southbridge/intel/bd82x6x/pch.h M src/southbridge/intel/common/acpi_pirq_gen.c M src/southbridge/intel/common/acpi_pirq_gen.h M src/southbridge/intel/common/rcba_pirq.c M src/southbridge/intel/common/rcba_pirq.h 6 files changed, 52 insertions(+), 35 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/22979/1 diff --git a/src/southbridge/intel/bd82x6x/Kconfig b/src/southbridge/intel/bd82x6x/Kconfig index ed2b979..0ef1168 100644 --- a/src/southbridge/intel/bd82x6x/Kconfig +++ b/src/southbridge/intel/bd82x6x/Kconfig @@ -46,6 +46,10 @@ hex default 0xfef00000 +config DEFAULT_RCBA + hex + default 0xfed1c000 + config DRAM_RESET_GATE_GPIO int default 60 diff --git a/src/southbridge/intel/bd82x6x/pch.h b/src/southbridge/intel/bd82x6x/pch.h index 83d9d8d..0bb5306 100644 --- a/src/southbridge/intel/bd82x6x/pch.h +++ b/src/southbridge/intel/bd82x6x/pch.h @@ -46,9 +46,9 @@ #define DEFAULT_PMBASE 0x0500 #ifndef __ACPI__ -#define DEFAULT_RCBA ((u8 *)0xfed1c000) +#define DEFAULT_RCBA ((u8 *)CONFIG_DEFAULT_RCBA) #else -#define DEFAULT_RCBA 0xfed1c000 +#define DEFAULT_RCBA CONFIG_DEFAUL_RCBA #endif #if IS_ENABLED(CONFIG_SOUTHBRIDGE_INTEL_BD82X6X) diff --git a/src/southbridge/intel/common/acpi_pirq_gen.c b/src/southbridge/intel/common/acpi_pirq_gen.c index 3ff591c..944b202 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.c +++ b/src/southbridge/intel/common/acpi_pirq_gen.c @@ -32,18 +32,14 @@ { char buffer[DEVICE_PATH_MAX]; device_t dev; - pci_pin_t prev_int_pin = PCI_INT_NONE; + u8 prev_int_pin_mask = 0; u8 prev_pci_dev = 0; size_t num_devs = 0; - for (dev = all_devices; dev; dev = dev->next) { + for (dev = dev_find_slot(0, PCI_DEVFN(0, 0)); dev; dev = dev->sibling) { u8 pci_dev; u8 int_pin; - pirq_t pirq; - - if (dev->path.type != DEVICE_PATH_PCI || - dev->bus->secondary != 0) - continue; + enum pirq pirq; pci_dev = PCI_SLOT(dev->path.pci.devfn); int_pin = pci_read_config8(dev, PCI_INTERRUPT_PIN); @@ -53,19 +49,23 @@ pirq = intel_common_map_pirq(dev, int_pin); if (emit == EMIT_NONE) /* Only print on the first pass */ - printk(BIOS_SPEW, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n", + printk(BIOS_DEBUG, "ACPI_PIRQ_GEN: %s: pin=%d pirq=%d\n", dev_path(dev), int_pin, pirq); if (pirq == PIRQ_NONE) continue; /* Avoid duplicate entries */ - if (prev_pci_dev == pci_dev && prev_int_pin == int_pin) { - continue; + if (prev_pci_dev == pci_dev) { + if (prev_int_pin_mask & (1 << int_pin)) { + continue; + } + prev_int_pin_mask |= (1 << int_pin); } else { - prev_int_pin = int_pin; + prev_int_pin_mask = 0; prev_pci_dev = pci_dev; } + if (emit != EMIT_NONE) { acpigen_write_package(4); acpigen_write_dword((pci_dev << 16) | 0xffff); @@ -87,13 +87,15 @@ return num_devs; } -void intel_acpi_gen_def_acpi_pirq(device_t dev) +void intel_acpi_gen_def_acpi_pirq(struct device *dev) { const char *lpcb_path = acpi_device_path(dev); const size_t num_devs = enumerate_root_pci_pins(EMIT_NONE, lpcb_path); - if (!lpcb_path) - die("ACPI_PIRQ_GEN: Missing LPCB ACPI path\n"); + if (!lpcb_path) { + printk(BIOS_ERR,"ACPI_PIRQ_GEN: Missing LPCB ACPI path\n"); + return; + } acpigen_write_scope("\\_SB.PCI0"); acpigen_write_method("_PRT", 0); diff --git a/src/southbridge/intel/common/acpi_pirq_gen.h b/src/southbridge/intel/common/acpi_pirq_gen.h index bd702da..9fdee1a 100644 --- a/src/southbridge/intel/common/acpi_pirq_gen.h +++ b/src/southbridge/intel/common/acpi_pirq_gen.h @@ -16,15 +16,15 @@ #ifndef INTEL_COMMON_ACPI_PIRQ_GEN_H #define INTEL_COMMON_ACPI_PIRQ_GEN_H -typedef enum pci_pin { +enum pci_pin { PCI_INT_NONE = 0, PCI_INT_A, PCI_INT_B, PCI_INT_C, PCI_INT_D, -} pci_pin_t; +}; -typedef enum pirq { +enum pirq { PIRQ_NONE = 0, PIRQ_A, PIRQ_B, @@ -34,9 +34,10 @@ PIRQ_F, PIRQ_G, PIRQ_H, -} pirq_t; +}; -void intel_acpi_gen_def_acpi_pirq(device_t dev); -enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin); +void intel_acpi_gen_def_acpi_pirq(struct device *dev); +enum pirq intel_common_map_pirq(const struct device *dev, + const enum pci_pin pci_pin); #endif diff --git a/src/southbridge/intel/common/rcba_pirq.c b/src/southbridge/intel/common/rcba_pirq.c index 1861154..6bed9ee 100644 --- a/src/southbridge/intel/common/rcba_pirq.c +++ b/src/southbridge/intel/common/rcba_pirq.c @@ -1,3 +1,18 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2017 Arthur Heymans <arthur(a)aheymans.xyz> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + #include <console/console.h> #include <device/device.h> #include <device/pci.h> @@ -12,31 +27,28 @@ D26IR, D27IR, D28IR, D29IR, D30IR, D31IR, }; -enum pirq intel_common_map_pirq(const device_t dev, const pci_pin_t pci_pin) +enum pirq intel_common_map_pirq(const struct device *dev, + const enum pci_pin pci_pin) { u8 slot = PCI_SLOT(dev->path.pci.devfn); u8 shift = 4 * (pci_pin - PCI_INT_A); u8 pirq; u16 reg; - if (pci_pin < 1 || pci_pin > 4) { + if (pci_pin < PCI_INT_A || pci_pin > PCI_INT_D) { printk(BIOS_ERR, "Slot %d PCI pin %d out of bounds\n", slot, pci_pin); return PIRQ_NONE; } - if (slot < MIN_SLOT || slot > MAX_SLOT) { + if (slot < MIN_SLOT || slot > MAX_SLOT || slot == 24) { /* non-PCH devices use 1:1 mapping. */ return pci_pin; } reg = pirq_dir_route_reg[slot - MIN_SLOT]; - pirq = ((RCBA16(reg) >> shift) & 0xf); - if (pirq > 8) { - printk(BIOS_ERR, "Reg 0x%04x PIRQ %c out of bounds\n", - reg, 'A' + pirq); - return PIRQ_NONE; - } - return PIRQ_A + pirq; + pirq = (RCBA16(reg) >> shift) & 0x7; + + return (enum pirq)(PIRQ_A + pirq); } diff --git a/src/southbridge/intel/common/rcba_pirq.h b/src/southbridge/intel/common/rcba_pirq.h index cf76fb3..8158079 100644 --- a/src/southbridge/intel/common/rcba_pirq.h +++ b/src/southbridge/intel/common/rcba_pirq.h @@ -37,8 +37,6 @@ #define D20IR 0x3160 /* 16bit */ #define D19IR 0x3168 /* 16bit */ -#define DEFAULT_RCBA 0xfed1c000 - -#define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) +#define RCBA16(x) (*((volatile u16 *)(CONFIG_DEFAULT_RCBA + (x)))) #endif /* SOUTHBRIDGE_INTEL_COMMON_RCBA_PIRQ_H */ -- To view, visit https://review.coreboot.org/22979 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ic68a91d0cb55942a4d928b30f73e1c779142420d Gerrit-Change-Number: 22979 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>

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Change in coreboot[master]: mainboard/hp: Add Elitebook Revolve 810 G1
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Elitebook Revolve 810 G1 ...................................................................... Patch Set 7: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19722/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64962/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 7 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 19:26:29 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mainboard/hp: Add Elitebook Revolve 810 G1
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22972 ) Change subject: mainboard/hp: Add Elitebook Revolve 810 G1 ...................................................................... Patch Set 6: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19721/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64961/ : SUCCESS -- To view, visit https://review.coreboot.org/22972 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: Iba9c361591697e6a2b3b7b485f7f1649c2a83524 Gerrit-Change-Number: 22972 Gerrit-PatchSet: 6 Gerrit-Owner: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Bill XIE <persmule(a)gmail.com> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 16:32:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: ec/hp/kbc1126: change the default offset of the blobs
by build bot (Jenkins) (Code Review) 23 Dec '17

23 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22978 ) Change subject: ec/hp/kbc1126: change the default offset of the blobs ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19720/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/64960/ : SUCCESS -- To view, visit https://review.coreboot.org/22978 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I8754e43ff318a03447633f7a9a8326d315328607 Gerrit-Change-Number: 22978 Gerrit-PatchSet: 1 Gerrit-Owner: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Sat, 23 Dec 2017 14:46:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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