coreboot-gerrit December 2017

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Change in coreboot[master]: google/fizz: Enable SataPwrOptEnable FSP UPD
by Kane Chen (Code Review) 28 Dec '17

28 Dec '17

Kane Chen has uploaded a new patch set (#2). ( https://review.coreboot.org/23019 ) Change subject: google/fizz: Enable SataPwrOptEnable FSP UPD ...................................................................... google/fizz: Enable SataPwrOptEnable FSP UPD This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23019/2 -- To view, visit https://review.coreboot.org/23019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newpatchset Gerrit-Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Gerrit-Change-Number: 23019 Gerrit-PatchSet: 2 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: google/fizz: Enable SataPwrOptEnable
by Kane Chen (Code Review) 28 Dec '17

28 Dec '17

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/23019 Change subject: google/fizz: Enable SataPwrOptEnable ...................................................................... google/fizz: Enable SataPwrOptEnable This change is to enable SataPwrOptEnable. With this change, we no longer see SError message in kernel during suspend_stress_test. BUG=b:70491485 Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/mainboard/google/fizz/devicetree.cb 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/23019/1 diff --git a/src/mainboard/google/fizz/devicetree.cb b/src/mainboard/google/fizz/devicetree.cb index e94dd26..c000a54 100644 --- a/src/mainboard/google/fizz/devicetree.cb +++ b/src/mainboard/google/fizz/devicetree.cb @@ -62,6 +62,7 @@ register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" register "SataPortsDevSlp[1]" = "1" + register "SataPwrOptEnable" = "1" register "EnableAzalia" = "1" register "DspEnable" = "1" register "IoBufferOwnership" = "3" -- To view, visit https://review.coreboot.org/23019 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: Ieb991f6889c5ff3181a670bc7702314049fa983c Gerrit-Change-Number: 23019 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: soc/intel/skylake: Add device setting for sata power optimization
by Kane Chen (Code Review) 28 Dec '17

28 Dec '17

Kane Chen has uploaded this change for review. ( https://review.coreboot.org/23018 Change subject: soc/intel/skylake: Add device setting for sata power optimization ...................................................................... soc/intel/skylake: Add device setting for sata power optimization This change provides option in devicetree and feeds the option to FSP SataPwrOptEnable UPD for power saving purpose BUG=b:70491485 Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Signed-off-by: Kane Chen <kane.chen(a)intel.com> --- M src/soc/intel/skylake/chip.h M src/soc/intel/skylake/chip_fsp20.c 2 files changed, 4 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/23018/1 diff --git a/src/soc/intel/skylake/chip.h b/src/soc/intel/skylake/chip.h index 00088b9..4e8cb81 100644 --- a/src/soc/intel/skylake/chip.h +++ b/src/soc/intel/skylake/chip.h @@ -542,6 +542,9 @@ /* PCH Trip Temperature */ u8 pch_trip_temp; + + /* Enable/Disable Sata power optimization */ + u8 SataPwrOptEnable; }; typedef struct soc_intel_skylake_config config_t; diff --git a/src/soc/intel/skylake/chip_fsp20.c b/src/soc/intel/skylake/chip_fsp20.c index 24a239e..ccda303 100644 --- a/src/soc/intel/skylake/chip_fsp20.c +++ b/src/soc/intel/skylake/chip_fsp20.c @@ -219,6 +219,7 @@ params->SataEnable = config->EnableSata; params->SataMode = config->SataMode; params->SataSpeedLimit = config->SataSpeedLimit; + params->SataPwrOptEnable = config->SataPwrOptEnable; tconfig->PchLockDownGlobalSmi = config->LockDownConfigGlobalSmi; tconfig->PchLockDownRtcLock = config->LockDownConfigRtcLock; -- To view, visit https://review.coreboot.org/23018 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I9099c5c97765a118bdee64da303cb3ba6ceb951b Gerrit-Change-Number: 23018 Gerrit-PatchSet: 1 Gerrit-Owner: Kane Chen <kane.chen(a)intel.com>

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: enable digitizer pen device
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23010 ) Change subject: mb/google/poppy/variants/nautilus: enable digitizer pen device ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19808/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65052/ : SUCCESS -- To view, visit https://review.coreboot.org/23010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Gerrit-Change-Number: 23010 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com> Gerrit-Reviewer: Chris Wang <chriswang(a)ami.com.tw> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 02:02:12 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: drivers/net: Add device index for multiple NIC cards
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22984 ) Change subject: drivers/net: Add device index for multiple NIC cards ...................................................................... Patch Set 4: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19809/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65053/ : SUCCESS -- To view, visit https://review.coreboot.org/22984 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I108b9bfba39370c8906a2fa4d2b39b106e884e0c Gerrit-Change-Number: 22984 Gerrit-PatchSet: 4 Gerrit-Owner: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Furquan Shaikh <furquan(a)google.com> Gerrit-Reviewer: Gaggery Tsai <gaggery.tsai(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 02:00:30 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: mb/google/poppy/variants/nautilus: enable digitizer pen device
by shkim (Code Review) 28 Dec '17

28 Dec '17

shkim has uploaded this change for review. ( https://review.coreboot.org/23010 Change subject: mb/google/poppy/variants/nautilus: enable digitizer pen device ...................................................................... mb/google/poppy/variants/nautilus: enable digitizer pen device - Add pen device property into devicetree.cb. - Add new ACPI device for pen eject event. It will be used by OS. BUG=none BRANCH=master TEST=emerge-nautilus coreboot and check pen device operation Signed-off-by: sh.kim <sh_.kim(a)samsung.com> Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f --- M src/mainboard/google/poppy/Kconfig M src/mainboard/google/poppy/dsdt.asl M src/mainboard/google/poppy/variants/nautilus/devicetree.cb M src/mainboard/google/poppy/variants/nautilus/gpio.c A src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/pen_eject.asl M src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h 6 files changed, 61 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/10/23010/1 diff --git a/src/mainboard/google/poppy/Kconfig b/src/mainboard/google/poppy/Kconfig index 9315d96..f0bad35 100644 --- a/src/mainboard/google/poppy/Kconfig +++ b/src/mainboard/google/poppy/Kconfig @@ -115,6 +115,11 @@ select SPI_TPM select TPM2 +# Select this option to add an ACPI device for pen eject event on the variant. +config VARIANT_HAS_PEN_EJECT_ACPI + bool + default n + config VARIANT_SPECIFIC_OPTIONS_POPPY def_bool n select DRIVERS_I2C_MAX98927 @@ -137,6 +142,7 @@ select DRIVERS_I2C_DA7219 select DRIVERS_PS2_KEYBOARD select VARIANT_HAS_I2C_TPM if !VBOOT_MOCK_SECDATA + select VARIANT_HAS_PEN_EJECT_ACPI config VARIANT_SPECIFIC_OPTIONS_SORAKA def_bool n diff --git a/src/mainboard/google/poppy/dsdt.asl b/src/mainboard/google/poppy/dsdt.asl index a922d10..2634f31 100644 --- a/src/mainboard/google/poppy/dsdt.asl +++ b/src/mainboard/google/poppy/dsdt.asl @@ -73,5 +73,10 @@ { /* Dynamic Platform Thermal Framework */ #include <variant/acpi/dptf.asl> + +#if IS_ENABLED(CONFIG_VARIANT_HAS_PEN_EJECT_ACPI) + /* Pen eject event */ + #include <variant/acpi/pen_eject.asl> +#endif } } diff --git a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb index a548ac9..d74588d 100644 --- a/src/mainboard/google/poppy/variants/nautilus/devicetree.cb +++ b/src/mainboard/google/poppy/variants/nautilus/devicetree.cb @@ -308,7 +308,20 @@ end end # I2C #1 device pci 15.2 on end # I2C #2 - device pci 15.3 on end # I2C #3 + device pci 15.3 on + chip drivers/i2c/hid + register "generic.hid" = ""ACPI0C50"" + register "generic.cid" = ""PNP0C50"" + register "generic.desc" = ""Digitizer device"" + register "generic.irq" = "ACPI_IRQ_LEVEL_LOW(GPP_A22_IRQ)" + register "generic.enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C9)" + register "generic.has_power_resource" = "1" + register "generic.disable_gpio_export_in_crs" = "1" + register "generic.wake" = "GPE0_DW0_21" + register "hid_desc_reg_offset" = "0x1" + device i2c 0x9 on end + end + end # I2C #3 device pci 16.0 on end # Management Engine Interface 1 device pci 16.1 off end # Management Engine Interface 2 device pci 16.2 off end # Management Engine IDE-R diff --git a/src/mainboard/google/poppy/variants/nautilus/gpio.c b/src/mainboard/google/poppy/variants/nautilus/gpio.c index ca05ae9..2a76fd1 100644 --- a/src/mainboard/google/poppy/variants/nautilus/gpio.c +++ b/src/mainboard/google/poppy/variants/nautilus/gpio.c @@ -130,7 +130,7 @@ /* C8 : UART0_RXD ==> NC */ PAD_CFG_NC(GPP_C8), /* C9 : UART0_TXD ==> CHP3_P3.3V_DX_DIG_EN */ - PAD_CFG_GPO(GPP_C9, 1, DEEP), + PAD_CFG_GPO(GPP_C9, 0, DEEP), /* C10 : UART0_RTS# ==> CHP3_CAM_PMIC_RST_L */ PAD_CFG_GPO(GPP_C10, 1, DEEP), /* C11 : UART0_CTS# ==> CHP3_P3.3V_DX_CAM_EN */ diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/pen_eject.asl b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/pen_eject.asl new file mode 100644 index 0000000..ffe2f03 --- /dev/null +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/acpi/pen_eject.asl @@ -0,0 +1,33 @@ +/* + * This file is part of the coreboot project. + * + * Copyright 2017 Google Inc. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ +Device (PENH) +{ + Name (_HID, "PRP0001") + + Name (_CRS, ResourceTemplate () { + GpioIo (Exclusive, PullNone, 0, 0, IoRestrictionInputOnly, + "\\_SB.PCI0.GPIO", 0, ResourceConsumer) { GPIO_DIG_EJECT } + }) + + Name (_DSD, Package () { + ToUUID("daffd814-6eba-4d8c-8a91-bc9bbf4aa301"), + Package () { + Package () { + "compatible", + Package () { "gpio-keys"} + }, + } + }) +} diff --git a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h index 4f79495..98f6d6e 100644 --- a/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h +++ b/src/mainboard/google/poppy/variants/nautilus/include/variant/gpio.h @@ -18,4 +18,6 @@ #include <baseboard/gpio.h> +#define GPIO_DIG_EJECT GPP_B19 + #endif /* __MAINBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/23010 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I050671c8b46fd92b1dd9164be2646727cd67da9f Gerrit-Change-Number: 23010 Gerrit-PatchSet: 1 Gerrit-Owner: shkim <sh_.kim(a)samsung.com>

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Change in coreboot[master]: lenovo: increase backlight PWM frequency for SNB/IVB laptops
by build bot (Jenkins) (Code Review) 28 Dec '17

28 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/22592 ) Change subject: lenovo: increase backlight PWM frequency for SNB/IVB laptops ...................................................................... Patch Set 2: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19807/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65051/ : SUCCESS -- To view, visit https://review.coreboot.org/22592 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I71434233b50e8e2adf47326cd4c4dd98ca38a542 Gerrit-Change-Number: 22592 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Patrick Rudolph <siro(a)das-labor.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)users.sourceforge.net> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Thu, 28 Dec 2017 00:28:18 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio: move files to match the common naming scheme
by build bot (Jenkins) (Code Review) 27 Dec '17

27 Dec '17

build bot (Jenkins) has posted comments on this change. ( https://review.coreboot.org/23009 ) Change subject: superio: move files to match the common naming scheme ...................................................................... Patch Set 1: Verified+1 Build Successful https://qa.coreboot.org/job/coreboot-checkpatch/19806/ : SUCCESS https://qa.coreboot.org/job/coreboot-gerrit/65050/ : SUCCESS -- To view, visit https://review.coreboot.org/23009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448 Gerrit-Change-Number: 23009 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Dec 2017 22:22:33 +0000 Gerrit-HasComments: No Gerrit-HasLabels: Yes

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Change in coreboot[master]: superio: move files to match the common naming scheme
by Felix Held (Code Review) 27 Dec '17

27 Dec '17

Felix Held has uploaded this change for review. ( https://review.coreboot.org/23009 Change subject: superio: move files to match the common naming scheme ...................................................................... superio: move files to match the common naming scheme Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448 Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/superio/smsc/sio10n268/Makefile.inc R src/superio/smsc/sio10n268/superio.c M src/superio/via/vt1211/Makefile.inc R src/superio/via/vt1211/superio.c 4 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/23009/1 diff --git a/src/superio/smsc/sio10n268/Makefile.inc b/src/superio/smsc/sio10n268/Makefile.inc index ab15abe..2241db3 100644 --- a/src/superio/smsc/sio10n268/Makefile.inc +++ b/src/superio/smsc/sio10n268/Makefile.inc @@ -13,4 +13,4 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += sio10n268.c +ramstage-$(CONFIG_SUPERIO_SMSC_SIO10N268) += superio.c diff --git a/src/superio/smsc/sio10n268/sio10n268.c b/src/superio/smsc/sio10n268/superio.c similarity index 100% rename from src/superio/smsc/sio10n268/sio10n268.c rename to src/superio/smsc/sio10n268/superio.c diff --git a/src/superio/via/vt1211/Makefile.inc b/src/superio/via/vt1211/Makefile.inc index a0c8f8b..d3044af 100644 --- a/src/superio/via/vt1211/Makefile.inc +++ b/src/superio/via/vt1211/Makefile.inc @@ -14,4 +14,4 @@ ## GNU General Public License for more details. ## -ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += vt1211.c +ramstage-$(CONFIG_SUPERIO_VIA_VT1211) += superio.c diff --git a/src/superio/via/vt1211/vt1211.c b/src/superio/via/vt1211/superio.c similarity index 100% rename from src/superio/via/vt1211/vt1211.c rename to src/superio/via/vt1211/superio.c -- To view, visit https://review.coreboot.org/23009 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: newchange Gerrit-Change-Id: I1a8fc34aaaf42514c8af97ab155ff2712e7a5448 Gerrit-Change-Number: 23009 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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Change in coreboot[master]: superio/ite: pass the chip-specific ops struct to pnp_enable_devices
by Arthur Heymans (Code Review) 27 Dec '17

27 Dec '17

Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/23006 ) Change subject: superio/ite: pass the chip-specific ops struct to pnp_enable_devices ...................................................................... Patch Set 1: Are those not passed on through the pnp_info array above? I don't think it matters but it's good to be consistent. -- To view, visit https://review.coreboot.org/23006 To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-MessageType: comment Gerrit-Change-Id: I5f03a4064778c419f4b9c50e70db1296addf6c9e Gerrit-Change-Number: 23006 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Wed, 27 Dec 2017 22:05:46 +0000 Gerrit-HasComments: No Gerrit-HasLabels: No

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coreboot-gerrit December 2017